JP2022547126A5 - - Google Patents

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Publication number
JP2022547126A5
JP2022547126A5 JP2022514988A JP2022514988A JP2022547126A5 JP 2022547126 A5 JP2022547126 A5 JP 2022547126A5 JP 2022514988 A JP2022514988 A JP 2022514988A JP 2022514988 A JP2022514988 A JP 2022514988A JP 2022547126 A5 JP2022547126 A5 JP 2022547126A5
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JP
Japan
Prior art keywords
metal
layer
recess
recessed
film
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Application number
JP2022514988A
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English (en)
Japanese (ja)
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JP7554538B2 (ja
JP2022547126A (ja
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Priority claimed from PCT/US2020/050962 external-priority patent/WO2021055399A1/en
Publication of JP2022547126A publication Critical patent/JP2022547126A/ja
Publication of JP2022547126A5 publication Critical patent/JP2022547126A5/ja
Application granted granted Critical
Publication of JP7554538B2 publication Critical patent/JP7554538B2/ja
Active legal-status Critical Current
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JP2022514988A 2019-09-16 2020-09-16 陥凹特徴部におけるボトムアップ金属化の方法 Active JP7554538B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962900794P 2019-09-16 2019-09-16
US62/900,794 2019-09-16
PCT/US2020/050962 WO2021055399A1 (en) 2019-09-16 2020-09-16 Method of bottom-up metallization in a recessed feature

Publications (3)

Publication Number Publication Date
JP2022547126A JP2022547126A (ja) 2022-11-10
JP2022547126A5 true JP2022547126A5 (enExample) 2023-07-25
JP7554538B2 JP7554538B2 (ja) 2024-09-20

Family

ID=74868656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022514988A Active JP7554538B2 (ja) 2019-09-16 2020-09-16 陥凹特徴部におけるボトムアップ金属化の方法

Country Status (6)

Country Link
US (1) US11450562B2 (enExample)
JP (1) JP7554538B2 (enExample)
KR (1) KR102781731B1 (enExample)
CN (1) CN114600232B (enExample)
TW (1) TWI857139B (enExample)
WO (1) WO2021055399A1 (enExample)

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US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
KR20210081436A (ko) 2018-11-19 2021-07-01 램 리써치 코포레이션 텅스텐을 위한 몰리브덴 템플릿들
SG11202108217UA (en) 2019-01-28 2021-08-30 Lam Res Corp Deposition of metal films
WO2021046058A1 (en) 2019-09-03 2021-03-11 Lam Research Corporation Molybdenum deposition
CN114667600A (zh) 2019-10-15 2022-06-24 朗姆研究公司 钼填充
JP7686761B2 (ja) 2021-02-23 2025-06-02 ラム リサーチ コーポレーション 3d-nand用の酸化物表面上へのモリブデン膜の堆積
WO2022221210A1 (en) 2021-04-14 2022-10-20 Lam Research Corporation Deposition of molybdenum
US12588475B2 (en) 2021-05-14 2026-03-24 Lam Research Corporation High selectivity doped hardmask films
WO2023286192A1 (ja) * 2021-07-14 2023-01-19 株式会社日立ハイテク プラズマ処理方法
US12394660B2 (en) 2021-11-22 2025-08-19 International Business Machines Corporation Buried power rail after replacement metal gate
WO2023215135A1 (en) * 2022-05-05 2023-11-09 Lam Research Corporation Molybdenum halides in memory applications
US12506029B2 (en) * 2022-06-30 2025-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Gap filling method in semiconductor manufacturing process
US20240290655A1 (en) * 2023-02-28 2024-08-29 Applied Materials, Inc. Selective via-fill with conformal sidewall coverage

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Publication number Priority date Publication date Assignee Title
US20040197541A1 (en) * 2001-08-02 2004-10-07 Joseph Zahka Selective electroless deposition and interconnects made therefrom
US20070190362A1 (en) * 2005-09-08 2007-08-16 Weidman Timothy W Patterned electroless metallization processes for large area electronics
DE102007004884A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht
KR101556238B1 (ko) * 2009-02-17 2015-10-01 삼성전자주식회사 매립형 배선라인을 갖는 반도체 소자의 제조방법
KR20120033640A (ko) 2010-09-30 2012-04-09 주식회사 하이닉스반도체 텅스텐 갭필을 이용한 반도체장치 제조 방법
KR101185990B1 (ko) * 2010-12-20 2012-09-25 에스케이하이닉스 주식회사 반도체 소자의 형성방법
JP5599350B2 (ja) * 2011-03-29 2014-10-01 東京エレクトロン株式会社 成膜装置及び成膜方法
WO2016204771A1 (en) * 2015-06-18 2016-12-22 Intel Corporation Bottom-up fill (buf) of metal features for semiconductor structures
US10316406B2 (en) * 2015-10-21 2019-06-11 Ultratech, Inc. Methods of forming an ALD-inhibiting layer using a self-assembled monolayer
EP3171409B1 (en) * 2015-11-18 2020-12-30 IMEC vzw Method for forming a field effect transistor device having an electrical contact
KR102432719B1 (ko) * 2015-12-23 2022-08-17 에스케이하이닉스 주식회사 매립금속게이트구조를 구비한 반도체장치 및 그 제조 방법, 그를 구비한 메모리셀, 그를 구비한 전자장치
JP2018207110A (ja) * 2017-06-06 2018-12-27 東京エレクトロン株式会社 二重金属電力レールを有する集積回路の製造方法
US10453740B2 (en) * 2017-06-29 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure without barrier layer on bottom surface of via
JP2019106538A (ja) * 2017-12-07 2019-06-27 マイクロマテリアルズ エルエルシー 制御可能な金属およびバリアライナー凹部のための方法
US20190198392A1 (en) * 2017-12-22 2019-06-27 Applied Materials, Inc. Methods of etching a tungsten layer
US10546815B2 (en) * 2018-05-31 2020-01-28 International Business Machines Corporation Low resistance interconnect structure with partial seed enhancement liner
US10573725B1 (en) * 2018-09-20 2020-02-25 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US11784091B2 (en) * 2019-08-30 2023-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature

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