JP2022545091A5 - - Google Patents

Info

Publication number
JP2022545091A5
JP2022545091A5 JP2022511079A JP2022511079A JP2022545091A5 JP 2022545091 A5 JP2022545091 A5 JP 2022545091A5 JP 2022511079 A JP2022511079 A JP 2022511079A JP 2022511079 A JP2022511079 A JP 2022511079A JP 2022545091 A5 JP2022545091 A5 JP 2022545091A5
Authority
JP
Japan
Prior art keywords
copper
layer
conductive
multilayer substrate
iron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022511079A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022545091A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/EP2020/073186 external-priority patent/WO2021032776A1/en
Publication of JP2022545091A publication Critical patent/JP2022545091A/ja
Publication of JP2022545091A5 publication Critical patent/JP2022545091A5/ja
Pending legal-status Critical Current

Links

JP2022511079A 2019-08-19 2020-08-19 銅で充填されたマイクロビアを含む高密度相互接続プリント回路基板の製造方法 Pending JP2022545091A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP19192196.4 2019-08-19
EP19192196 2019-08-19
PCT/EP2020/073186 WO2021032776A1 (en) 2019-08-19 2020-08-19 Method of preparing a high density interconnect printed circuit board including microvias filled with copper

Publications (2)

Publication Number Publication Date
JP2022545091A JP2022545091A (ja) 2022-10-25
JP2022545091A5 true JP2022545091A5 (https=) 2023-08-29

Family

ID=67659208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022511079A Pending JP2022545091A (ja) 2019-08-19 2020-08-19 銅で充填されたマイクロビアを含む高密度相互接続プリント回路基板の製造方法

Country Status (7)

Country Link
US (2) US12245383B2 (https=)
EP (1) EP4018791A1 (https=)
JP (1) JP2022545091A (https=)
KR (2) KR102875198B1 (https=)
CN (1) CN114303447A (https=)
TW (1) TWI886142B (https=)
WO (1) WO2021032776A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI816388B (zh) * 2021-05-17 2023-09-21 美商麥克達米德恩索龍股份有限公司 在印刷電路板或其它基板上填充穿孔的單步電解法
KR20230067984A (ko) 2021-11-10 2023-05-17 (주)티에스이 극미세 비아를 포함하는 다층 회로 기판의 제조 방법 및 이에 의해 제조된 다층 회로 기판

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DE502007005345D1 (de) 2006-03-30 2010-11-25 Atotech Deutschland Gmbh Elektrolytisches verfahren zum füllen von löchern und vertiefungen mit metallen
US20080053688A1 (en) * 2006-09-01 2008-03-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
KR100843367B1 (ko) * 2007-03-06 2008-07-03 삼성전기주식회사 인쇄회로기판 및 그 제조방법
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