JP2022509506A5 - - Google Patents
Info
- Publication number
- JP2022509506A5 JP2022509506A5 JP2021548528A JP2021548528A JP2022509506A5 JP 2022509506 A5 JP2022509506 A5 JP 2022509506A5 JP 2021548528 A JP2021548528 A JP 2021548528A JP 2021548528 A JP2021548528 A JP 2021548528A JP 2022509506 A5 JP2022509506 A5 JP 2022509506A5
- Authority
- JP
- Japan
- Prior art keywords
- stage
- substrate
- wiring
- thickness direction
- along
- Prior art date
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862752112P | 2018-10-29 | 2018-10-29 | |
| US62/752,112 | 2018-10-29 | ||
| PCT/US2019/058554 WO2020092361A1 (en) | 2018-10-29 | 2019-10-29 | Architecture for monolithic 3d integration of semiconductor devices |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2022509506A JP2022509506A (ja) | 2022-01-20 |
| JPWO2020092361A5 JPWO2020092361A5 (https=) | 2022-07-29 |
| JP2022509506A5 true JP2022509506A5 (https=) | 2022-07-29 |
| JP7426547B2 JP7426547B2 (ja) | 2024-02-02 |
Family
ID=70327689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021548528A Active JP7426547B2 (ja) | 2018-10-29 | 2019-10-29 | 半導体素子のモノリシック３ｄ集積を行うためのアーキテクチャ |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11201148B2 (https=) |
| JP (1) | JP7426547B2 (https=) |
| KR (1) | KR102672379B1 (https=) |
| CN (1) | CN112956024B (https=) |
| TW (1) | TWI856983B (https=) |
| WO (1) | WO2020092361A1 (https=) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7376805B2 (ja) * | 2018-11-09 | 2023-11-09 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| JP7364922B2 (ja) * | 2018-12-26 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US11437376B2 (en) * | 2019-05-31 | 2022-09-06 | Tokyo Electron Limited | Compact 3D stacked-CFET architecture for complex logic cells |
| US12451430B2 (en) | 2020-05-28 | 2025-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby |
| DE102021107950A1 (de) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zum fertigen von halbleiterbauelementen mit unterschiedlichen architekturen und damit gefertigte halbleiterbauelemente |
| US11646318B2 (en) * | 2020-09-30 | 2023-05-09 | Tokyo Electron Limited | Connections from buried interconnects to device terminals in multiple stacked devices structures |
| US11322197B1 (en) * | 2020-10-21 | 2022-05-03 | Arm Limited | Power-gating techniques with buried metal |
| US11948886B2 (en) | 2020-10-23 | 2024-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and methods of manufacturing same |
| US12176293B2 (en) * | 2020-12-04 | 2024-12-24 | Tokyo Electron Limited | Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration |
| US12374623B2 (en) | 2021-01-18 | 2025-07-29 | Samsung Electronics Co., Ltd. | Stacked semiconductor device architecture |
| US12183738B2 (en) * | 2021-01-29 | 2024-12-31 | Samsung Electronics Co., Ltd. | Cross-coupled gate design for stacked device with separated top-down gate |
| US12446291B2 (en) * | 2021-02-19 | 2025-10-14 | Tokyo Electron Limited | Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di) |
| US11968818B2 (en) | 2021-03-19 | 2024-04-23 | Samsung Electronics Co., Ltd. | SRAM memory cell for stacked transistors with different channel width |
| US11670363B2 (en) * | 2021-04-23 | 2023-06-06 | Arm Limited | Multi-tier memory architecture |
| US12557377B2 (en) * | 2021-05-13 | 2026-02-17 | Tokyo Electron Limited | Inverted cross-couple for top-tier FET for multi-tier gate-on-gate 3DI |
| US11764154B2 (en) | 2021-07-30 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power rail and signal line arrangement in integrated circuits having stacked transistors |
| EP4434092A4 (en) * | 2021-11-16 | 2025-10-08 | Hsu Fu Chang | ADVANCED STRUCTURES WITH MOSFET TRANSISTORS AND METAL LAYERS |
| US12588489B2 (en) | 2022-02-25 | 2026-03-24 | Samsung Electronics Co., Ltd. | Integrated circuit devices including stacked elements and methods of forming the same |
| US12131996B2 (en) | 2022-03-28 | 2024-10-29 | Samsung Electronics Co., Ltd. | Stacked device with backside power distribution network and method of manufacturing the same |
| US20230317717A1 (en) * | 2022-03-30 | 2023-10-05 | Arm Limited | Multi-Device Stack Structure |
| EP4293721A1 (en) * | 2022-06-15 | 2023-12-20 | Imec VZW | Bit cell for sram |
| US20240290719A1 (en) * | 2023-02-24 | 2024-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit device, system and method |
| US20250309093A1 (en) * | 2024-03-28 | 2025-10-02 | International Business Machines Corporation | Power rail in stacked fet devices |
| EP4665106A1 (en) * | 2024-06-13 | 2025-12-17 | Imec VZW | A static random access memory device |
| US20260096411A1 (en) * | 2024-09-27 | 2026-04-02 | Intel Corporation | Complementary field-effect transistor static random-access memory |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3119177B2 (ja) * | 1996-10-24 | 2000-12-18 | 日本電気株式会社 | 半導体装置 |
| US6800883B2 (en) * | 2000-09-21 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | CMOS basic cell and method for fabricating semiconductor integrated circuit using the same |
| KR100505658B1 (ko) * | 2002-12-11 | 2005-08-03 | 삼성전자주식회사 | ＭＩＭ(Ｍｅｔａｌ-Ｉｎｓｕｌａｔｏｒ-Ｍｅｔａｌ)커패시터를 갖는 반도체 소자 |
| KR101036158B1 (ko) * | 2003-07-29 | 2011-05-23 | 매그나칩 반도체 유한회사 | Ｓｒａｍ 및 로직 복합 소자의 제조 방법 |
| KR100629364B1 (ko) * | 2004-12-28 | 2006-09-29 | 삼성전자주식회사 | 에스램 셀들 및 플래쉬 메모리 셀들을 구비하는 반도체직접회로 소자들 및 그 제조방법들 |
| JP2008117864A (ja) * | 2006-11-01 | 2008-05-22 | Nec Electronics Corp | 半導体装置 |
| US8624328B2 (en) * | 2008-11-19 | 2014-01-07 | Renesas Electronics Corporation | Semiconductor device |
| JP2011114049A (ja) * | 2009-11-25 | 2011-06-09 | Renesas Electronics Corp | 半導体装置 |
| JP2011165966A (ja) * | 2010-02-10 | 2011-08-25 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
| JP2012059830A (ja) * | 2010-09-07 | 2012-03-22 | Toshiba Corp | 半導体記憶装置 |
| JP5959162B2 (ja) * | 2011-06-09 | 2016-08-02 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP5947580B2 (ja) * | 2012-03-23 | 2016-07-06 | ローム株式会社 | デカップルキャパシタセル、セルベースｉｃ、セルベースｉｃのレイアウトシステムおよびレイアウト方法 |
| JP6113500B2 (ja) * | 2012-12-27 | 2017-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
| US9536840B2 (en) * | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
| US9177890B2 (en) * | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
| US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
| DE112013007061T5 (de) * | 2013-06-25 | 2016-01-28 | Intel Corp. | Monolithische dreidimensionale (3D) ICS mit örtlichen ebenenübergreifenden Zwischenverbindungen |
| US10134729B2 (en) | 2013-09-27 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical noise reduction in 3D stacked semiconductor devices |
| US9070552B1 (en) * | 2014-05-01 | 2015-06-30 | Qualcomm Incorporated | Adaptive standard cell architecture and layout techniques for low area digital SoC |
| US20160211250A1 (en) * | 2015-01-15 | 2016-07-21 | Infineon Technologies Ag | Semiconductor substrate arrangement, a semiconductor device, and a method for processing a semiconductor substrate |
| US9431300B1 (en) * | 2015-08-27 | 2016-08-30 | Globalfoundries Inc. | MOL architecture enabling ultra-regular cross couple |
| US9691695B2 (en) | 2015-08-31 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure |
| US9935100B2 (en) * | 2015-11-09 | 2018-04-03 | Qualcomm Incorporated | Power rail inbound middle of line (MOL) routing |
| US9799741B2 (en) * | 2015-12-16 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method for manufacturing the same |
| FR3045869B1 (fr) * | 2015-12-18 | 2020-02-07 | Stmicroelectronics (Crolles 2) Sas | Routage ameliore pour structure integree tridimensionnelle |
| US9754923B1 (en) * | 2016-05-09 | 2017-09-05 | Qualcomm Incorporated | Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) |
| US9929149B2 (en) | 2016-06-21 | 2018-03-27 | Arm Limited | Using inter-tier vias in integrated circuits |
| US10510592B2 (en) * | 2016-07-25 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit (IC) structure for high performance and functional density |
| US10651178B2 (en) * | 2018-02-14 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Compact electrical connection that can be used to form an SRAM cell and method of making the same |
-
2019
- 2019-10-29 JP JP2021548528A patent/JP7426547B2/ja active Active
- 2019-10-29 WO PCT/US2019/058554 patent/WO2020092361A1/en not_active Ceased
- 2019-10-29 KR KR1020217015002A patent/KR102672379B1/ko active Active
- 2019-10-29 US US16/667,442 patent/US11201148B2/en active Active
- 2019-10-29 CN CN201980071531.0A patent/CN112956024B/zh active Active
- 2019-10-29 TW TW108139025A patent/TWI856983B/zh active
-
2021
- 2021-10-28 US US17/513,143 patent/US20220052038A1/en not_active Abandoned
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2022509506A5 (https=) | ||
| JP7426547B2 (ja) | 半導体素子のモノリシック３ｄ集積を行うためのアーキテクチャ | |
| JPWO2020092361A5 (https=) | ||
| US12040271B2 (en) | Power delivery network for CFET with buried power rails | |
| CN112771655B (zh) | 半导体集成电路装置以及半导体封装件构造 | |
| JP7415176B2 (ja) | 半導体集積回路装置 | |
| US9324715B2 (en) | Flip-flop layout architecture implementation for semiconductor device | |
| EP3038156B1 (en) | Semiconductor package assembly with through silicon via interconnects | |
| JP2022534858A (ja) | 複合ロジックセルのための小型３ｄ積層ｃｆｅｔアーキテクチャ | |
| KR102819717B1 (ko) | 반도체 소자 및 반도체 소자의 설계 방법 | |
| US12464819B2 (en) | Semiconductor integrated circuit device | |
| JP7610127B2 (ja) | 半導体集積回路装置 | |
| JPWO2018042986A1 (ja) | 半導体集積回路装置 | |
| WO2022224847A1 (ja) | 出力回路 | |
| TW201705407A (zh) | 半導體裝置、系統晶片、行動裝置以及半導體系統 | |
| JP6215645B2 (ja) | 半導体集積回路 | |
| US10777579B2 (en) | Semiconductor integrated circuit device | |
| TWI847046B (zh) | 半導體結構 | |
| CN119855165B (zh) | 一种存储芯片、逻辑芯片、芯片堆叠结构和存储器 | |
| WO2023209971A1 (ja) | 半導体集積回路装置 | |
| KR20120045351A (ko) | Ｍｏｓ 트랜지스터를 포함하는 반도체 소자의 레이아웃 구조 및 그 제조 방법 | |
| JPH09246393A (ja) | 半導体集積回路のレイアウト方法 |