JP2021528845A5 - - Google Patents

Info

Publication number
JP2021528845A5
JP2021528845A5 JP2020569781A JP2020569781A JP2021528845A5 JP 2021528845 A5 JP2021528845 A5 JP 2021528845A5 JP 2020569781 A JP2020569781 A JP 2020569781A JP 2020569781 A JP2020569781 A JP 2020569781A JP 2021528845 A5 JP2021528845 A5 JP 2021528845A5
Authority
JP
Japan
Prior art keywords
package
pads
posts
die
height
Prior art date
Application number
JP2020569781A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021528845A (ja
JPWO2019241610A5 (https=
JP7563986B2 (ja
Filing date
Publication date
Priority claimed from US16/008,119 external-priority patent/US10580715B2/en
Application filed filed Critical
Publication of JP2021528845A publication Critical patent/JP2021528845A/ja
Publication of JPWO2019241610A5 publication Critical patent/JPWO2019241610A5/ja
Publication of JP2021528845A5 publication Critical patent/JP2021528845A5/ja
Application granted granted Critical
Publication of JP7563986B2 publication Critical patent/JP7563986B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020569781A 2018-06-14 2019-06-14 埋め込みパッケージにおける応力緩衝層 Active JP7563986B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/008,119 US10580715B2 (en) 2018-06-14 2018-06-14 Stress buffer layer in embedded package
US16/008,119 2018-06-14
PCT/US2019/037149 WO2019241610A1 (en) 2018-06-14 2019-06-14 Stress buffer layer in embedded package

Publications (4)

Publication Number Publication Date
JP2021528845A JP2021528845A (ja) 2021-10-21
JPWO2019241610A5 JPWO2019241610A5 (https=) 2022-06-21
JP2021528845A5 true JP2021528845A5 (https=) 2022-06-21
JP7563986B2 JP7563986B2 (ja) 2024-10-08

Family

ID=68840287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020569781A Active JP7563986B2 (ja) 2018-06-14 2019-06-14 埋め込みパッケージにおける応力緩衝層

Country Status (5)

Country Link
US (2) US10580715B2 (https=)
EP (1) EP3807923A4 (https=)
JP (1) JP7563986B2 (https=)
CN (1) CN112074934B (https=)
WO (1) WO2019241610A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10580715B2 (en) * 2018-06-14 2020-03-03 Texas Instruments Incorporated Stress buffer layer in embedded package
TWI734545B (zh) * 2020-07-03 2021-07-21 財團法人工業技術研究院 半導體封裝結構
CN114093840A (zh) * 2021-10-27 2022-02-25 珠海越亚半导体股份有限公司 信热分离tmv封装结构及其制作方法
CN114678335B (zh) * 2022-05-27 2022-08-16 合肥矽迈微电子科技有限公司 一种芯片散热结构、工艺及半导体器件
KR102684858B1 (ko) * 2023-03-03 2024-07-17 제엠제코(주) 열방출 포스트 접합 반도체 패키지 및 이의 제조방법
US20250112107A1 (en) * 2023-09-28 2025-04-03 Stmicroelectronics International N.V. Heat sink, slug, or spreader and method of manufacturing the same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766332A (ja) * 1993-08-25 1995-03-10 Seiko Epson Corp 半導体装置
JPH0997930A (ja) * 1995-07-27 1997-04-08 Aisin Seiki Co Ltd 熱電冷却モジュール及びその製造方法
JP2001217340A (ja) * 2000-02-01 2001-08-10 Nec Corp 半導体装置及びその製造方法
TW579555B (en) * 2000-03-13 2004-03-11 Ibm Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7299639B2 (en) * 2004-06-22 2007-11-27 Intel Corporation Thermoelectric module
US7355289B2 (en) * 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
US7855397B2 (en) * 2007-09-14 2010-12-21 Nextreme Thermal Solutions, Inc. Electronic assemblies providing active side heat pumping
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US7960827B1 (en) * 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8241955B2 (en) * 2009-06-19 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with mountable inward and outward interconnects and method of manufacture thereof
US20120032350A1 (en) * 2010-08-06 2012-02-09 Conexant Systems, Inc. Systems and Methods for Heat Dissipation Using Thermal Conduits
KR101698932B1 (ko) * 2010-08-17 2017-01-23 삼성전자 주식회사 반도체 패키지 및 그 제조방법
US8946888B2 (en) * 2011-09-30 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package on packaging structure and methods of making same
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
KR101928005B1 (ko) * 2011-12-01 2019-03-13 삼성전자주식회사 열전 냉각 패키지 및 이의 열관리 방법
US9299688B2 (en) * 2013-12-10 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
DE102014101366B3 (de) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
US10340199B2 (en) * 2014-11-20 2019-07-02 Mediatek Inc. Packaging substrate with block-type via and semiconductor packages having the same
US9875988B2 (en) * 2015-10-29 2018-01-23 Semtech Corporation Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
CN107424973B (zh) * 2016-05-23 2020-01-21 凤凰先驱股份有限公司 封装基板及其制法
KR102448099B1 (ko) * 2016-06-02 2022-09-27 에스케이하이닉스 주식회사 히트 스프레더 구조를 포함하는 반도체 패키지
DE112016007304T5 (de) * 2016-09-30 2019-06-19 Intel Corporation Eingebetteter die in interposer-gehäusen
US9865570B1 (en) * 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
US10510704B2 (en) * 2018-01-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10580715B2 (en) * 2018-06-14 2020-03-03 Texas Instruments Incorporated Stress buffer layer in embedded package

Similar Documents

Publication Publication Date Title
JP2021528845A5 (https=)
US11901348B2 (en) Semiconductor package and method of manufacturing the semiconductor package
KR102385549B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
TWI815209B (zh) 半導體封裝及其製造方法
TW558929B (en) Flip chip type semiconductor device and method for manufacturing the same
US7215017B2 (en) Wafer level package, wafer level packaging procedure for making wafer level package
TW503496B (en) Chip packaging structure and manufacturing process of the same
KR102619532B1 (ko) 반도체 패키지
TW544882B (en) Chip package structure and process thereof
CN110120373A (zh) 半导体封装结构和其制造方法
JP2003031730A5 (https=)
US8907227B2 (en) Multiple surface integrated devices on low resistivity substrates
CN104916623A (zh) 半导体封装和制造半导体封装基底的方法
TW200816437A (en) An electronics package with an integrated circuit device having post wafer fabrication integrated passive components
TW200936000A (en) Wire bonding substrate and fabrication thereof
CN101534607B (zh) 打线基板及其制作方法
JP2010054496A (ja) プローブカード及びその製造方法
US7651886B2 (en) Semiconductor device and manufacturing process thereof
TW201448072A (zh) 用於電子封裝之多孔的氧化鋁基板
JPWO2019241610A5 (https=)
US20060006504A1 (en) Multilayer leadframe module with embedded passive component and method of fabricating the same
JP2018507556A5 (https=)
TWI421992B (zh) 封裝基板及其製法
JP2010010248A (ja) インターポーザ基板とその製造方法
TW200933831A (en) Integrated circuit package and the method for fabricating thereof