JP2021522680A5 - - Google Patents
Info
- Publication number
- JP2021522680A5 JP2021522680A5 JP2020559409A JP2020559409A JP2021522680A5 JP 2021522680 A5 JP2021522680 A5 JP 2021522680A5 JP 2020559409 A JP2020559409 A JP 2020559409A JP 2020559409 A JP2020559409 A JP 2020559409A JP 2021522680 A5 JP2021522680 A5 JP 2021522680A5
- Authority
- JP
- Japan
- Prior art keywords
- metal
- dielectric layer
- layer
- steps include
- metal layer
- Prior art date
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023075430A JP7541430B2 (ja) | 2018-04-27 | 2023-05-01 | 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862663916P | 2018-04-27 | 2018-04-27 | |
| US62/663,916 | 2018-04-27 | ||
| PCT/US2019/029444 WO2019210234A1 (en) | 2018-04-27 | 2019-04-26 | Area selective deposition for cap layer formation in advanced contacts |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023075430A Division JP7541430B2 (ja) | 2018-04-27 | 2023-05-01 | 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積 |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2021522680A JP2021522680A (ja) | 2021-08-30 |
| JP2021522680A5 true JP2021522680A5 (https=) | 2022-01-18 |
| JPWO2019210234A5 JPWO2019210234A5 (https=) | 2022-01-18 |
| JP7369895B2 JP7369895B2 (ja) | 2023-10-27 |
Family
ID=68292714
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020559409A Active JP7369895B2 (ja) | 2018-04-27 | 2019-04-26 | 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積 |
| JP2023075430A Active JP7541430B2 (ja) | 2018-04-27 | 2023-05-01 | 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023075430A Active JP7541430B2 (ja) | 2018-04-27 | 2023-05-01 | 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11170992B2 (https=) |
| JP (2) | JP7369895B2 (https=) |
| KR (1) | KR102742954B1 (https=) |
| TW (1) | TWI894126B (https=) |
| WO (1) | WO2019210234A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12327764B2 (en) | 2021-07-30 | 2025-06-10 | Applied Materials, Inc. | Two-dimension self-aligned scheme with subtractive metal etch |
| KR20230074952A (ko) | 2021-11-22 | 2023-05-31 | 삼성전자주식회사 | 커패시터 구조체를 포함하는 반도체 장치 및 이의 제조 방법 |
| JP2024163650A (ja) * | 2023-05-12 | 2024-11-22 | 東京エレクトロン株式会社 | 基板処理方法および基板処理装置 |
| KR102901082B1 (ko) * | 2023-08-17 | 2025-12-16 | 한양대학교 에리카산학협력단 | 영역 선택적 원자층 증착법, 이를 위한 장치, 및 이를 통해 제조된 hzo 물질막 구조체 |
Family Cites Families (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854127A (en) * | 1997-03-13 | 1998-12-29 | Micron Technology, Inc. | Method of forming a contact landing pad |
| US6184138B1 (en) * | 1999-09-07 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create a controllable and reproducible dual copper damascene structure |
| JP2007042662A (ja) * | 2003-10-20 | 2007-02-15 | Renesas Technology Corp | 半導体装置 |
| US7779782B2 (en) * | 2004-08-09 | 2010-08-24 | Lam Research | Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes |
| US7972897B2 (en) * | 2007-02-05 | 2011-07-05 | Intermolecular, Inc. | Methods for forming resistive switching memory elements |
| JP2009200255A (ja) * | 2008-02-21 | 2009-09-03 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7830010B2 (en) * | 2008-04-03 | 2010-11-09 | International Business Machines Corporation | Surface treatment for selective metal cap applications |
| US7745324B1 (en) | 2009-01-09 | 2010-06-29 | International Business Machines Corporation | Interconnect with recessed dielectric adjacent a noble metal cap |
| JP5775288B2 (ja) * | 2009-11-17 | 2015-09-09 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体装置 |
| US8404582B2 (en) * | 2010-05-04 | 2013-03-26 | International Business Machines Corporation | Structure and method for manufacturing interconnect structures having self-aligned dielectric caps |
| DE102011004922B4 (de) * | 2011-03-01 | 2016-12-15 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung von Transistoren mit Metallgatestapeln mit erhöhter Integrität |
| US20120252210A1 (en) * | 2011-03-30 | 2012-10-04 | Tokyo Electron Limited | Method for modifying metal cap layers in semiconductor devices |
| US8501566B1 (en) * | 2012-09-11 | 2013-08-06 | Nanya Technology Corp. | Method for fabricating a recessed channel access transistor device |
| CN105474359B (zh) * | 2013-06-27 | 2019-04-12 | 英特尔公司 | 以非光刻方式图案化的定向自组装对准促进层 |
| US9932671B2 (en) * | 2014-03-27 | 2018-04-03 | Intel Corporation | Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) |
| WO2015153040A1 (en) * | 2014-04-01 | 2015-10-08 | Applied Materials, Inc. | Integrated metal spacer and air gap interconnect |
| US10047435B2 (en) * | 2014-04-16 | 2018-08-14 | Asm Ip Holding B.V. | Dual selective deposition |
| US9384985B2 (en) * | 2014-07-18 | 2016-07-05 | United Microelectronics Corp. | Semiconductor structure including silicon and oxygen-containing metal layer and process thereof |
| US9673091B2 (en) * | 2015-06-25 | 2017-06-06 | Globalfoundries Inc. | Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion |
| US20170092533A1 (en) * | 2015-09-29 | 2017-03-30 | Applied Materials, Inc. | Selective silicon dioxide deposition using phosphonic acid self assembled monolayers as nucleation inhibitor |
| CN108780777B (zh) * | 2016-02-02 | 2023-02-17 | 东京毅力科创株式会社 | 利用选择性沉积对金属和通孔进行自对准 |
| US9530691B1 (en) * | 2016-02-19 | 2016-12-27 | Globalfoundries Inc. | Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias |
| US10068764B2 (en) * | 2016-09-13 | 2018-09-04 | Tokyo Electron Limited | Selective metal oxide deposition using a self-assembled monolayer surface pretreatment |
| EP3520136A4 (en) * | 2016-09-30 | 2020-05-06 | Applied Materials, Inc. | METHOD FOR SHAPING SELF-ALIGNED VIA CONTACTS |
| TWI719262B (zh) * | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | 用於圖案化之薄膜的沉積與處理 |
| TW201833991A (zh) * | 2016-11-08 | 2018-09-16 | 美商應用材料股份有限公司 | 自對準圖案化之方法 |
| WO2018089351A1 (en) * | 2016-11-08 | 2018-05-17 | Applied Materials, Inc. | Geometric control of bottom-up pillars for patterning applications |
| TWI760540B (zh) * | 2017-08-13 | 2022-04-11 | 美商應用材料股份有限公司 | 自對準高深寬比結構及製作方法 |
| US11315943B2 (en) * | 2017-09-05 | 2022-04-26 | Applied Materials, Inc. | Bottom-up approach to high aspect ratio hole formation in 3D memory structures |
| US10586734B2 (en) * | 2017-11-20 | 2020-03-10 | Tokyo Electron Limited | Method of selective film deposition for forming fully self-aligned vias |
-
2019
- 2019-04-26 WO PCT/US2019/029444 patent/WO2019210234A1/en not_active Ceased
- 2019-04-26 JP JP2020559409A patent/JP7369895B2/ja active Active
- 2019-04-26 KR KR1020207033206A patent/KR102742954B1/ko active Active
- 2019-04-26 TW TW108114640A patent/TWI894126B/zh active
- 2019-04-26 US US16/396,360 patent/US11170992B2/en active Active
-
2023
- 2023-05-01 JP JP2023075430A patent/JP7541430B2/ja active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2021522680A5 (https=) | ||
| TWI726210B (zh) | 三維反及閘(3d-nand)元件中用於字元線分離之方法 | |
| US10700072B2 (en) | Cap layer for bit line resistance reduction | |
| US20140367833A1 (en) | Low-Temperature Sidewall Image Transfer Process Using ALD Metals, Metal Oxides and Metal Nitrides | |
| CN102473709A (zh) | 形成具有带内陷电极的电容器的存储器设备的方法 | |
| KR20200137016A (ko) | 접촉이 향상된 캡 층 형성용 영역 선택적 증착 | |
| CN109585363A (zh) | 一种半导体器件的形成方法及半导体器件 | |
| CN106910708B (zh) | 具有局部互连结构的器件及其制造方法 | |
| TW202240671A (zh) | 用於選擇性釕金屬層形成的雜散釕金屬核移除 | |
| JPWO2020077112A5 (https=) | ||
| JPH06283613A (ja) | 半導体素子の金属コンタクト形成方法 | |
| JPWO2019210234A5 (https=) | ||
| CN113130380B (zh) | 半导体结构及其形成方法 | |
| CN101572242B (zh) | 防止结区域损耗的半导体器件的制造方法 | |
| JP4662943B2 (ja) | コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 | |
| US8409986B2 (en) | Method for improving within die uniformity of metal plug chemical mechanical planarization process in gate last route | |
| CN101882610B (zh) | 半导体结构及其制造方法 | |
| CN213716906U (zh) | 氮化镓半导体器件 | |
| CN102592993B (zh) | 提高后栅工程金属插塞化学机械平坦化工艺均匀性的方法 | |
| TWI864613B (zh) | 半導體結構的製造方法 | |
| CN101192563A (zh) | 避免金属布线制程中晶圆边界剥离的方法 | |
| CN110100303B (zh) | 一种石墨烯晶体管的制备方法 | |
| US10777522B2 (en) | Semiconductor structure and method of manufacturing the same | |
| TWI855730B (zh) | 使用改善的蝕刻製程的半導體結構的製備方法 | |
| US20260107748A1 (en) | Forming method of semiconductor structure |