WO2019210234A1 - Area selective deposition for cap layer formation in advanced contacts - Google Patents

Area selective deposition for cap layer formation in advanced contacts Download PDF

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Publication number
WO2019210234A1
WO2019210234A1 PCT/US2019/029444 US2019029444W WO2019210234A1 WO 2019210234 A1 WO2019210234 A1 WO 2019210234A1 US 2019029444 W US2019029444 W US 2019029444W WO 2019210234 A1 WO2019210234 A1 WO 2019210234A1
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Prior art keywords
dielectric layer
metal
metal layer
layer
selectively depositing
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Ceased
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PCT/US2019/029444
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English (en)
French (fr)
Inventor
Kandabara Tapily
Gerrit Leusink
Takaaki Tsunomura
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Priority to JP2020559409A priority Critical patent/JP7369895B2/ja
Priority to KR1020207033206A priority patent/KR102742954B1/ko
Publication of WO2019210234A1 publication Critical patent/WO2019210234A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
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    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts

Definitions

  • This invention relates to methods for processing a substrate, and more particularly to area selective deposition for cap layer formation in advanced contacts.
  • An area selective deposition method for cap layer formation in advanced semiconductor contacts is described.
  • the area selective deposition enables a simplified metallization scheme that requires reduced lithography-based patterning.
  • the method includes a cap layer formation in advanced semiconductor contacts.
  • the method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized surface of the first metal layer.
  • the selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.
  • the method includes providing a planarized substrate including a first dielectric layer and a first metal layer, selectively depositing a second dielectric layer on the first dielectric layer, where the selectively depositing forms a recessed feature above the first metal layer, filling the recessed feature with a second metal layer, removing the second dielectric layer from the substrate, and selectively depositing a third dielectric layer on the second metal layer.
  • the method includes providing a planarized substrate including a first dielectric layer and a first metal layer, recessing the first dielectric layer below an upper surface of the first metal layer, and selectively depositing a second dielectric layer on the first metal layer.
  • FIGS. 1 A-iC schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention
  • FIGS. 2A-2E schematically show through cross-sectional view's a method of processing a substrate according to an embodiment of the invention.
  • FIGS. 3A-3C schematically show through cross-sectional view ' s a method of processing a substrate according to an embodiment of the invention.
  • FIGS. 1 A-1C schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
  • the exemplary' substrate 100 shown in FIG. 1 A contains various material layers commonly found in semiconductor devices, however, embodiments of the invention may be applied to simpler or more advanced semiconductor devices.
  • the substrate 100 contains an oxide layer 102 (e.g., SiO 2 ), a nitride layer 104 (e.g., SiN), a gate contact layer 106, a cap layer 108 (e.g., SiN or SiCN), a source/drain layer 112 (e.g., Si or SiC), a dielectric layer 110 (e.g., SiO 2 ), and a metal-containing layer 114 (e.g., a trench silicide layer: CoSi2, NiSi, or MoSi2).
  • the metal- containing layer 114 and the source/drain layer 112 may be part of a contact region.
  • the substrate 100 further includes a first dielectric layer 130 and a first metal layer 118.
  • the first dielectric layer 130 can, for example, include SiO 2 or a low-k material.
  • the first metal layer 118 may, for example, be selected from the group consisting of tungsten (W) metal, ruthenium (Ru) metal, cobalt (Co) metal, molybdenum (Mo), and a combination of thereof.
  • the substrate 100 may be planarized using a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • FIG.1B shows the substrate 100 following an oxidation process that oxidizes the exposed first metal layer 118 to form an oxidized metal layer 132 on the first metal layer 118.
  • the oxidation process can include a exposing the substrate 100 to plasma-excited O 2 gas.
  • a W metal layer is oxidized to form an oxidized W metal layer.
  • the oxidation process is accompanied by an increase in in volume since oxidized W (e.g., WO 3 ) occupies a larger volume than W metal. This results in the oxidized W metal layer extending a few nanometers (nm) above the horizontal plane of the W metal layer and the first dielectric layer 130.
  • FIG.1C shows the substrate 100 following selective deposition of a second dielectric layer 134 on the oxidized metal layer 132.
  • the second dielectric layer 134 can include a metal oxide layer or a metal nitride layer.
  • the second dielectric layer 134 may be selected from the group consisting of TiO 2 , HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , SiN, and a combination thereof.
  • the selective deposition of the second dielectric layer 134 is, at least in part, enabled by the oxidized metal layer 132 extending above the horizontal plane of the first metal layer 118 and the first dielectric layer 130.
  • the second dielectric layer 134 may be deposited by spatial deposition by moving the substrate 100 below a gas inlet dispensing a deposition gas during spatial vapor phase deposition process, for example a spatial atomic layer deposition (ALD) process or a spatial chemical vapor deposition (CVD).
  • a rotation speed of the substrate support and the gas exposure parameters may be selected such that the deposition gas is preferentially exposed to a top surface of the raised oxidized metal layer 132 but not to a surface of the first dielectric layer 130 that is below the top surface of the raised oxidized metal layer 132.
  • the second dielectric layer 134 may be deposited carefully controlling the precursor exposure, including gas flow, exposure time) in order to preferentially expose the top surface of the raised oxidized metal layer 132.
  • the second dielectric layer 134 also known as a cap layer, may be used as a hard mask for a subsequent etching process to form a fully self-aligned via, a self-aligned contact, a supervia, or a self-aligned gate contact in the first dielectric layer 130 adjacent the first metal layer 118.
  • the second dielectric layer 134 protects the first metal layer 118 during the etching process by preventing or reducing etching of the first metal layer 118.
  • FIGS.2A-2E schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
  • the substrate 100 shown in FIG.1A has been reproduced as substrate 200 in FIG.2A.
  • FIG.2B shows the substrate 200 following selective deposition of a second dielectric layer 140 on the first dielectric layer 130.
  • the selective deposition of the second dielectric layer 140 forms a recessed feature 133 above the first metal layer 118.
  • the second dielectric layer 140 may be selected from the group consisting of TiO 2 , HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , SiN, and a combination thereof.
  • the second dielectric layer 140 can contain SiO 2 , and the selective deposition may be achieved by alternating exposures of a metal-containing precursor and a silanol gas.
  • the metal-containing precursor selectively adsorbs on the first dielectric layer 130 and subsequently catalyzes reaction of the silanol gas to deposit SiO 2 material.
  • the silanol gas may be selected from the group consisting of tris(tert-pentoxy) silanol (TPSOL), tris(tert- butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.
  • the exposures to the silanol gas may be performed in the absence of any oxidizing and hydrolyzing agent, and the substrate may be exposed, at a substrate temperature of approximately 150°C or less, to a process gas containing a silanol gas to deposit a SiO 2 film.
  • the thickness of the SiO 2 film is controlled by self-limiting adsorption of the silanol gas on the metal-containing precursor layer. This catalytic effect has been observed until the SiO 2 films were about 3nm thick, thereafter the SiO 2 deposition stopped.
  • the substrate temperature may be approximately 120°C or less. In yet another embodiment, the substrate temperature may be approximately 100°C or less.
  • metal-containing precursor examples include aluminum (Al), titanium (Ti), or both aluminum and titanium.
  • aluminum-containing precursors include: AlMe 3 , AlEt 3 , AlMe2H, [Al(O s Bu)3]4, Al(CH3COCHCOCH3)3, AlCl3, AlBr3, AlI3, Al(O i Pr)3, [Al(NMe2)3]2, Al( i Bu)2Cl, Al( i Bu)3, Al( i Bu)2H, AlEt2Cl, Et3Al2(O s Bu)3, and Al(THD)3.
  • titanium-containing precursors that have“Ti-N” intra-molecular bonds include Ti(NEt2)4 (TDEAT), Ti(NMeEt)4 (TEMAT), Ti(NMe2)4 (TDMAT).
  • Other examples include titanium-containing precursors containing“Ti-C” intra-molecular bonds include Ti(COCH3)(h5- C 5 H 5 ) 2 Cl, Ti(h5-C 5 H 5 )Cl 2 , Ti(h5-C 5 H 5 )Cl 3 , Ti(h5-C 5 H 5 ) 2 Cl 2 , Ti(h5-C 5 (CH 3 ) 5 )Cl 3 , Ti(CH 3 )(h5- C 5 H 5 ) 2 Cl, Ti(h5-C 9 H 7 ) 2 Cl 2 , Ti((h5-C 5 (CH 3 ) 5 ) 2 Cl, Ti((h5-C 5 (CH 3 ) 5 ) 2 Cl 2 , Ti(h5-C 5 H 5 ) 2 (m-C
  • the second dielectric layer 140 can contain TiO2, and the selective deposition may be achieved by alternating exposures of a Ti-containing precursor and an oxygen-containing gas.
  • FIG.2C shows the substrate 200 following selective deposition of a second metal layer 136 on the first metal layer 118 in the recessed feature 133.
  • the first metal layer 118 may fully fill the recessed feature 133.
  • the second metal layer 136 can be selected from the group consisting of tungsten (W) metal, ruthenium (Ru) metal, cobalt (Co) metal, molybdenum (Mo), and a combination of thereof.
  • the selective deposition of the second metal layer 136 may be performed in a bottom-up fashion by blocking metal deposition on the first dielectric layer 130.
  • the metal deposition may be blocked by exposing the substrate 200 to a reactant gas containing a hydrophilic functional group that adsorbs on the first dielectric layer 130 but not on the first metal layer 118.
  • the reactant gas can contain a silicon-containing gas, including an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or any combination thereof.
  • the reactant gas may be selected from
  • DMSDMA dimethylsilane dimethylamine
  • TMSDMA trimethylsilane dimethylamine
  • BDMADMS bis(dimethylamino) dimethylsilane
  • FIG.2D shows the substrate 200 following removal of the first dielectric layer 130.
  • the removal can include a dry etching process or a wet etching process.
  • FIG.2E shows the substrate 200 following selective deposition of a third dielectric layer 138 on the second metal layer 136.
  • a surface of the second metal layer 136 may be oxidized using an oxidation process to form an oxidized metal layer and, thereafter, the third dielectric layer 138 selectively deposited on the oxidized metal layer.
  • the third dielectric layer 138 can include a metal oxide layer or a metal nitride layer.
  • the third dielectric layer 138 may be selected from the group consisting of TiO2, HfO2, ZrO2, Al 2 O 3 , SiO 2 , SiN, and a combination thereof.
  • the selective deposition of the third dielectric layer 138 is, at least in part, enabled by the second metal layer 136 extending above the horizontal plane of the first metal layer 118 and the first dielectric layer 130.
  • the third dielectric layer 138 may be deposited by spatial deposition by moving the substrate 100 below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, for example a spatial atomic layer deposition (ALD) process or a spatial chemical vapor deposition (CVD).
  • a rotation speed of the substrate support and the gas exposure parameters may be selected such that the deposition gas is preferentially exposed to a top surface of the raised second metal layer 136 but not to a surface of the first dielectric layer 130 that is below the top surface of the raised second metal layer 136.
  • the third dielectric layer 138 may be deposited carefully controlling the precursor exposure, including gas flow, exposure time) in order to preferentially expose the top surface of the raised second metal layer 136.
  • FIGS.3A-3C schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
  • the substrate 100 shown in FIG.1A has been reproduced as substrate 300 in FIG.3A.
  • FIG.3B shows the substrate 300 following an etching process that recesses the first dielectric layer below an upper surface of the first metal layer 118. Thereafter, the substrate 300 may be processed as described in FIG.2E, including selectively depositing a second dielectric layer 140 deposited on the first metal layer 118.
  • a surface of the first metal layer 118 may be oxidized using an oxidation process to form an oxidized metal layer and, thereafter, the second dielectric layer 140 selectively deposited on the oxidized metal layer.
  • the second dielectric layer 140 can include a metal oxide layer or a metal nitride layer.
  • the second dielectric layer 140 may be selected from the group consisting of TiO 2 , HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , SiN, and a combination thereof.
  • the selective deposition of the second dielectric layer 140 is, at least in part, enabled by the first metal layer 118 extending above the horizontal plane of the first dielectric layer 130.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/US2019/029444 2018-04-27 2019-04-26 Area selective deposition for cap layer formation in advanced contacts Ceased WO2019210234A1 (en)

Priority Applications (2)

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JP2020559409A JP7369895B2 (ja) 2018-04-27 2019-04-26 高度なコンタクトにおけるキャップ層形成のためのエリア選択的堆積
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