JP6466498B2 - 凹状フィーチャ内の膜のボトムアップ形成方法 - Google Patents
凹状フィーチャ内の膜のボトムアップ形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 72
- 230000015572 biosynthetic process Effects 0.000 title description 3
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- 239000002184 metal Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 28
- 238000000231 atomic layer deposition Methods 0.000 claims description 20
- 239000002243 precursor Substances 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- 238000003672 processing method Methods 0.000 claims description 10
- 239000011261 inert gas Substances 0.000 claims description 8
- 238000010926 purge Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 241000019011 Tasa Species 0.000 claims 2
- 241000894007 species Species 0.000 claims 1
- 239000010410 layer Substances 0.000 description 67
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- 230000008021 deposition Effects 0.000 description 20
- 238000005530 etching Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 12
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- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 6
- 229910004541 SiN Inorganic materials 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910010413 TiO 2 Inorganic materials 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000000059 patterning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910052914 metal silicate Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 2
- 239000002094 self assembled monolayer Substances 0.000 description 2
- 239000013545 self-assembled monolayer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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Description
この出願は、2016年4月12日に出願された米国仮特許出願第62/321,481号に関連し、その優先権を主張するものであり、その全内容は、参照によりここに組み込まれる。
Claims (13)
- 基板処理方法であって、
a)第1層及び該第1層の上の第2層を含む基板を提供するステップであって、前記第2層は、該第2層を貫通して延在する凹状フィーチャを有するステップと、
b)前記基板の上に非コンフォーマルなマスク層を堆積させるステップであって、前記マスク層は前記凹状フィーチャの開口部にオーバーハングを有するステップと、
c)前記開口部に前記オーバーハングの少なくとも一部を維持しながら、前記凹状フィーチャの底部から前記マスク層を除去するステップと、
d)前記凹状フィーチャの前記底部に膜を選択的に堆積させるステップと、
e)前記基板から前記マスク層のオーバーハングを除去するステップと、
を含む方法。 - 前記膜が前記凹状フィーチャ内で所望の厚さを有するまで、ステップb)〜e)を少なくとも1回繰り返すステップを、さらに含む請求項1に記載の方法。
- 前記凹状フィーチャが前記膜で少なくとも満たされるまで、ステップb)〜e)を繰り返すステップを、さらに含む請求項1に記載の方法。
- 前記第1層及び第2層が同じ材料を含む、請求項1に記載の方法。
- 前記第1層及び第2層が異なる材料を含む、請求項1に記載の方法。
- 前記非コンフォーマルなマスク層は、物理蒸着(PVD)又はスパッタリングによって堆積される、請求項1に記載の方法。
- 前記膜が、原子層堆積(ALD)を使用して堆積される、請求項1に記載の方法。
- 前記膜は金属酸化物の膜を含み、
前記金属酸化物は、原子層堆積(ALD)を用いて、
1)前記基板を含むプロセスチャンバ内に金属含有前駆体をパルシングするステップと、
2)前記プロセスチャンバを不活性ガスでパージするステップと、
3)前記プロセスチャンバ内に酸素含有前駆体をパルシングするステップと、
4)前記プロセスチャンバを不活性ガスでパージするステップと、
5)ステップ1)〜4)を少なくとも1回繰り返すステップと、
によって堆積される、請求項1に記載の方法。 - 基板処理方法であって、
a)第1層及び該第1層の上の第2層を含む基板を提供するステップであって、前記第2層は、該第2層を貫通して延在する凹状フィーチャを有するステップと、
b)前記凹状フィーチャの側壁部及び底部に均一な厚さを有する膜をコンフォーマルに堆積させるステップと、
c)前記の堆積された膜をプラズマエッチングにより前記側壁部から選択的に除去することにより、前記底部の上にのみ前記膜を残すステップであって、前記底部に前記側壁部よりも少ないエッチング種を曝露する、ステップと、
d) 前記膜が前記凹状フィーチャ内で所望の厚さを有するまで、ステップb)及びc)を少なくとも1回繰り返し、それにより前記凹状フィーチャ内で前記膜を前記底部から上方へ順に形成するステップと、
を備える方法。 - 前記凹状フィーチャが前記膜で少なくとも満たされるまで、ステップb)及びc)を繰り返すステップを、さらに含む請求項9に記載の方法。
- 前記第1層及び第2層が同じ材料を含む、請求項9に記載の方法。
- 前記第1層及び第2層が異なる材料を含む、請求項9に記載の方法。
- 前記膜が、化学蒸着(CVD)又は原子層堆積(ALD)によって堆積される、請求項9に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US201662321481P | 2016-04-12 | 2016-04-12 | |
US62/321,481 | 2016-04-12 |
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JP2017208534A JP2017208534A (ja) | 2017-11-24 |
JP6466498B2 true JP6466498B2 (ja) | 2019-02-06 |
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JP7040257B2 (ja) * | 2018-04-25 | 2022-03-23 | 東京エレクトロン株式会社 | 成膜装置、及び成膜方法 |
US10741442B2 (en) | 2018-05-31 | 2020-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
JP7048433B2 (ja) * | 2018-06-22 | 2022-04-05 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
JP7065728B2 (ja) * | 2018-08-17 | 2022-05-12 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
JP7018849B2 (ja) * | 2018-08-17 | 2022-02-14 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
US20200135464A1 (en) * | 2018-10-30 | 2020-04-30 | Applied Materials, Inc. | Methods and apparatus for patterning substrates using asymmetric physical vapor deposition |
KR102095710B1 (ko) * | 2019-11-05 | 2020-04-01 | 주식회사 유진테크 머티리얼즈 | 표면 보호 물질을 이용한 박막 형성 방법 |
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JP2004128074A (ja) * | 2002-09-30 | 2004-04-22 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
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US20040127014A1 (en) * | 2002-12-30 | 2004-07-01 | Cheng-Lin Huang | Method of improving a barrier layer in a via or contact opening |
JP4695824B2 (ja) | 2003-03-07 | 2011-06-08 | 富士電機ホールディングス株式会社 | 半導体ウエハの製造方法 |
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