JP6946463B2 - ワードライン抵抗を低下させる方法 - Google Patents
ワードライン抵抗を低下させる方法 Download PDFInfo
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- JP6946463B2 JP6946463B2 JP2019557809A JP2019557809A JP6946463B2 JP 6946463 B2 JP6946463 B2 JP 6946463B2 JP 2019557809 A JP2019557809 A JP 2019557809A JP 2019557809 A JP2019557809 A JP 2019557809A JP 6946463 B2 JP6946463 B2 JP 6946463B2
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Description
Claims (13)
- 基板表面に、間にギャップを有する複数の離間された酸化物層と、前記離間された酸化物層の間の前記ギャップ内に付与されたポリシリコン層とを、提供することと、
前記離間された酸化物層の表面下のある深さまで前記ポリシリコン層に凹部形成することと、
前記離間された酸化物層の上にライナーを形成し、凹部形成された前記ポリシリコン層の上にはライナーを形成しないことと、
ワードラインを形成するため、前記ライナー上の前記ギャップ内に金属層を堆積することと、
を含む処理方法。 - 前記金属層がタングステンを含む、請求項1に記載の方法。
- 前記金属層は、原子ベースで95%以上タングステンである組成を有する、請求項2に記載の方法。
- 前記金属層を堆積させることが、前記基板をタングステン前駆体と反応物質に曝露することを含む、請求項2または3に記載の方法。
- 前記タングステン前駆体は、WF6、WCl6又はWCl5のうちの一又は複数を含み、前記反応物質はH2を含む、請求項4に記載の方法。
- 前記ライナーは、TiN、TiSiN、TiAlN、Al2O3又はTaNのうちの一又は複数を含む、請求項1から5のいずれか一項に記載の方法。
- 前記ライナーは、約20Åから約50Åの範囲の厚みを有する、請求項6に記載の方法。
- 前記ライナーを形成することは、チタン前駆体と窒素反応物質への順次曝露を含む、請求項6または7に記載の方法。
- 前記チタン前駆体はTiCl4を含み、前記窒素反応物質はNH3を含む、請求項8に記載の方法。
- 50より多くのワードラインがある、請求項1から9のいずれか一項に記載の方法。
- 前記ポリシリコン層に凹部形成することは、HF、CFx、HCl、Cl2、HBr、Br2又はH2のうちの一又は複数を含むエッチャントに前記基板を曝露することを含む、請求項1から10のいずれか一項に記載の方法。
- 前記ポリシリコン層に凹部形成することは、プラズマへの曝露を含む、請求項11に記載の方法。
- 前記金属層は、前記離間された酸化物層と同一面をなす、請求項1から12のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201762515533P | 2017-06-05 | 2017-06-05 | |
US62/515,533 | 2017-06-05 | ||
PCT/US2018/036060 WO2018226696A1 (en) | 2017-06-05 | 2018-06-05 | Methods of lowering wordline resistance |
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JP2020522877A JP2020522877A (ja) | 2020-07-30 |
JP6946463B2 true JP6946463B2 (ja) | 2021-10-06 |
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Application Number | Title | Priority Date | Filing Date |
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JP2019557809A Active JP6946463B2 (ja) | 2017-06-05 | 2018-06-05 | ワードライン抵抗を低下させる方法 |
Country Status (5)
Country | Link |
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US (1) | US10854511B2 (ja) |
JP (1) | JP6946463B2 (ja) |
KR (1) | KR102270458B1 (ja) |
CN (1) | CN110678972B (ja) |
WO (1) | WO2018226696A1 (ja) |
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JP7270722B2 (ja) * | 2019-03-28 | 2023-05-10 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US11808715B2 (en) * | 2020-04-17 | 2023-11-07 | Onto Innovation Inc. | Target for optical measurement of trenches |
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JP2001237218A (ja) | 2000-02-21 | 2001-08-31 | Nec Corp | 半導体装置の製造方法 |
WO2002073696A1 (fr) * | 2001-03-12 | 2002-09-19 | Hitachi, Ltd. | Procede pour fabriquer un dispositif semi-conducteur a circuit integre |
KR100777016B1 (ko) | 2006-06-20 | 2007-11-16 | 재단법인서울대학교산학협력재단 | 기둥 구조를 갖는 낸드 플래시 메모리 어레이 및 그제조방법 |
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