US10777522B2 - Semiconductor structure and method of manufacturing the same - Google Patents

Semiconductor structure and method of manufacturing the same Download PDF

Info

Publication number
US10777522B2
US10777522B2 US16/275,921 US201916275921A US10777522B2 US 10777522 B2 US10777522 B2 US 10777522B2 US 201916275921 A US201916275921 A US 201916275921A US 10777522 B2 US10777522 B2 US 10777522B2
Authority
US
United States
Prior art keywords
layer
metallic
semiconductor structure
protrusions
pillars
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/275,921
Other versions
US20200211991A1 (en
Inventor
Chih-Ching Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to US16/275,921 priority Critical patent/US10777522B2/en
Assigned to NANYA TECHNOLOGY CORPORATION reassignment NANYA TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, CHIH-CHING
Priority to TW108109568A priority patent/TWI701791B/en
Priority to CN201910349745.1A priority patent/CN111384013B/en
Publication of US20200211991A1 publication Critical patent/US20200211991A1/en
Application granted granted Critical
Publication of US10777522B2 publication Critical patent/US10777522B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H01L2224/11614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0534—4th Group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0534—4th Group
    • H01L2924/05342—ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2

Definitions

  • the present disclosure relates to a semiconductor structure and a method of manufacturing the same, and more particularly, to a high-aspect ratio metallic interconnect on a semiconductor substrate and a method of manufacturing the same.
  • interconnect layers are patterned and then etched to form conducting lines.
  • reentrant undercutting has been observed at the interface of the metallic layer and the anti-reflection coating layer, which can lead to undesirable voids during subsequent filling with an inter-metal layer dielectric or, in the worst case, subsequent lifting of the aluminum layer, either of which degrades the yield of semiconductor devices.
  • the semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer.
  • the metallic pillars are disposed on the substrate.
  • the metallic protrusions extend from an upper surface of the metallic pillars.
  • the capping layer is disposed on the metallic protrusions.
  • the passivation layer is disposed on sidewalls of the metallic protrusions and the capping layer.
  • the sidewalls of the metallic protrusions are discontinuous with sidewalls of the metallic pillars.
  • the metallic protrusions have a width substantially less than a width of the metallic pillars.
  • an included angle between a sidewall and a bottom wall of the metallic pillar is in a range between 80 and 90 degrees.
  • the semiconductor structure further includes an anti-reflective coating layer sandwiched between the metallic protrusion and the capping layer.
  • the metallic protrusions have a height substantially greater than twice a height of the anti-reflective coating layer.
  • the semiconductor structure further includes an insulating layer and a barrier layer; the insulating layer separates the metallic pillars from the substrate, and the barrier layer is sandwiched between the insulating layer and the metallic pillars.
  • the passivation layer comprises at least one first layer and at least one second layer arranged in a staggered configuration.
  • the metallic pillars and the metallic protrusions are integrally formed.
  • an outer periphery of the passivation layer is continuous with the sidewalls of the metallic pillars.
  • Another aspect of the present disclosure provides a method of manufacturing the semiconductor structure.
  • the method includes steps of providing a substrate; depositing a metallic layer and a capping layer on the substrate; patterning the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer, wherein the remaining metallic layer includes a base and a plurality of metallic protrusions connected to the base; depositing a passivation layer on sidewalls of the capping layer and the metallic protrusions; and etching the base through the trenches to form a plurality of metallic pillars underlying the respective metallic protrusions.
  • the deposition of the passivation layer on the sidewalls of the capping layer and the metallic protrusions includes steps of depositing the passivation layer on a top surface of the capping layer, the sidewalls of the capping layer and the protrusions, and an upper surface of the base; and performing an etching process to remove the passivation layer from the top surface and the upper surface.
  • included angles between the upper surface of the base and the sidewalls of the metallic protrusions substantially equal to 90 degrees.
  • the passivation layer is formed by an atomic layer deposition process.
  • the passivation layer has a uniform thickness.
  • the patterning of the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer includes steps of coating a photoresist layer on the capping layer; patterning the photoresist layer to form a photoresist pattern having a plurality of openings; and removing a portion of the capping layer exposed through the openings.
  • the method further includes steps of forming an insulating layer on the substrate; and depositing a barrier layer on the insulating layer before the deposition of the metallic layer.
  • the method further includes a step of depositing an anti-reflective coating layer on the metallic layer before the deposition of the capping layer.
  • the etching of the base using Cl 2 and BCl 3 as etchant gases is performed using Cl 2 and BCl 3 as etchant gases.
  • FIG. 1 is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the present disclosure.
  • FIG. 2 is a flow diagram illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
  • FIGS. 3 through 9 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
  • FIG. 1 is a cross-sectional view of a semiconductor structure 10 in accordance with some embodiments of the present disclosure.
  • the semiconductor structure 10 includes a semiconductor substrate 110 , an insulating layer 120 disposed on the semiconductor substrate 110 , a plurality of metallic pillars 133 disposed on the insulating layer 120 , a plurality of metallic protrusions 134 extending from an upper surface 1332 of the metallic pillars 133 , a capping layer 140 disposed on the metallic protrusions 134 , and a passivation layer 150 disposed on sidewalls 1402 of the capping layer 140 and sidewalls 1342 of the metallic protrusions 134 .
  • the insulating layer 120 including oxide may be a thermal oxidation layer or a deposition layer.
  • the metallic pillars 133 and the metallic protrusions 134 are integrally formed.
  • the metallic pillars 133 have sidewalls 1334 that are discontinuous with the sidewalls 1342 of the metallic protrusions 134 .
  • the metallic pillars 133 have a width W 1 substantially greater than a width W 2 of the metallic pillars 134 .
  • the capping layer 140 includes dielectric such as nitride.
  • the passivation layer 150 provides passivation in the etch environment to protect against undercutting or notches of the sidewalls 1342 of the metallic protrusions 134 .
  • the passivation layer 150 includes dielectric.
  • the passivation layer 150 may include one or more first layers 152 and one or more second layers 154 arranged in a staggered configuration.
  • the first layers 152 include silicon dioxide (SiO 2 ).
  • the second layers 154 include zirconium dioxide (ZrO 2 ) or hafnium dioxide (HfO 2 ).
  • an outer periphery 152 of the passivation layer 150 is continuous with the sidewalls 1334 of the metallic pillars 133 .
  • the semiconductor structure 10 further includes a barrier layer 160 sandwiched between the insulating layer 120 and the metallic pillars 133 .
  • the barrier layer 160 acts as a glue layer.
  • the barrier layer 160 may be a single-layered structure including titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN).
  • the barrier layer 160 may have a multi-layered structure including one or more titanium layers and one or more titanium nitride layers; however, in some embodiments, the barrier layer 160 may be the multi-layered structure including one or more tantalum layers and one or more tantalum nitride layers.
  • sidewalls 1602 of the barrier layer 160 are continuous with sidewalls 1334 of the metallic pillars 133 .
  • the semiconductor structure 10 further includes an anti-reflective coating (ARC) layer 170 sandwiched between the metallic protrusions 134 and the capping layer 140 .
  • the ARC layer 170 may be a multi-layered structure including at least one titanium layer and at least one titanium nitride layer.
  • the ARC layer 170 may be the multi-layered structure including at least one tantalum layer and at least one tantalum nitride layer.
  • the ARC layer 170 may be single-layered structure.
  • sidewalls 1702 of the ARC layer 170 are continuous with the sidewalls 1342 of the metallic protrusions 134 .
  • FIG. 2 is a flow diagram illustrating a method 200 of manufacturing a semiconductor structure 10 in accordance with some embodiments of the present disclosure.
  • FIGS. 3 to 9 are schematic diagrams illustrating various fabrication stages constructed according to the method 200 for manufacturing the semiconductor structure 10 in accordance with some embodiments of the present disclosure. The stages shown in FIGS. 3 to 9 are also illustrated schematically in the flow diagram in FIG. 2 . In the subsequent discussion, the fabrication stages shown in FIGS. 3 to 9 are discussed in reference to the process steps in FIG. 2 .
  • a semiconductor substrate 110 is provided according to a step 202 in FIG. 2 .
  • the semiconductor substrate 110 is a bulk substrate.
  • examples of the material suitable for the semiconductor substrate 110 include, but are not limited to, silicon, silicon on insulator, and silicon on sapphire.
  • an insulating layer 120 , a metallic layer 130 and a capping layer 140 are formed over the semiconductor substrate 110 according to a step 204 in FIG. 2 .
  • the insulating layer 120 is in contact with the semiconductor substrate 110 .
  • the insulating layer 120 includes oxide such as silicon dioxide (SiO 2 ).
  • the insulating layer 120 is formed using a chemical vapor deposition (CVD) process or a thermal oxidation process.
  • the metallic layer 130 is deposited on the insulating layer 120 .
  • the metallic layer 130 includes aluminum (Al), copper (Cu), or a combination thereof, e.g., aluminum copper (AlCu).
  • the metallic layer 130 may be separated from the insulating layer 120 by a barrier layer 160 .
  • the barrier layer 160 may improve adhesion of the metallic layer 130 to the insulating layer 120 .
  • the barrier layer 160 may be a single-layered structure or a multi-layered structure.
  • refractory metals, refractory metal nitrides, and combinations thereof are typically used for the barrier layer 160 .
  • the barrier layer 160 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN), tantalum silicon nitride (TaSiN), or the like.
  • the barrier layer 160 may be formed by a physical vapor deposition (PVD) process or a CVD process, for example.
  • the capping layer 140 is disposed on the metallic layer 130 .
  • the capping layer 140 acts as a hard mask for patterning the metallic layer 130 .
  • the capping layer 140 includes dielectric such as nitride.
  • an anti-reflective coating (ARC) layer 170 between the metallic layer 130 and the capping layer 140 .
  • the ARC layer 170 may be a single-layered structure or a multi-layered structure.
  • the ARC layer 170 includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN) when it is a single-layered structure.
  • the ARC layer 170 may be formed by a PVD process or a CVD process, for example.
  • a photoresist layer 180 is coated on the capping layer 140 according to a step 206 in FIG. 2 .
  • the photoresist layer 180 is then patterned to define a region where the capping layer 140 and the ARC layer 170 are to be subsequently etched according to a step 208 in FIG. 2 .
  • the photoresist layer 180 is patterned by steps including (1) exposing the photoresist layer 180 to a pattern (not shown), (2) performing a post-exposure back process, and (3) developing the photoresist layer 180 , thereby forming a photoresist pattern 182 , as shown in FIG. 4 , having at least one opening 184 .
  • a portion of the capping layer 140 to be subsequently etched is exposed through the openings 184 .
  • a patterning process is performed to etch the capping layer 140 and the ARC layer 170 according to a step 210 in FIG. 2 . Accordingly, at least one trench 190 penetrating through the capping layer 140 and the ARC layer 160 and in the metallic layer 130 are formed.
  • the etching process includes a dry etching process. In some embodiments, the dry etching process may be an anisotropic etching process.
  • the remaining metallic layer 130 includes a base 132 and a plurality of protrusions 134 extending from a surface 1322 of the base 132 .
  • a height H 1 of the metallic protrusions 134 is greater than twice a height of the ARC layer 170 .
  • an included angle ⁇ 1 between sidewalls 1342 of the protrusions 134 and the surface 1322 may be equal to 90 degrees.
  • the remaining ARC layer 170 and the remaining capping layer 140 overlap the protrusions 134 .
  • a width of the metallic protrusions 134 is defined by a width of the photoresist pattern 182 .
  • the photoresist pattern 182 is removed according to a step 212 in FIG. 2 .
  • an ashing process or a wet strip process may be used to remove the photoresist pattern 182 , wherein the wet strip process may chemically alter the photoresist pattern 182 so that it no longer adheres to the remaining capping layer 140 .
  • a passivation layer 150 is deposited on the capping layer 130 and into the trenches 190 according to a step 214 in FIG. 2 .
  • the passivation layer 150 is deposited on a top surface 142 of the capping layer 140 , sidewalls 144 of the capping layer 140 , sidewalls 172 of the ARC layer 170 , sidewalls 1342 of the protrusions 134 , and the upper surface 1322 of the base 132 .
  • the passivation layer 150 is a substantially conformal layer.
  • the passivation layer 150 has a uniform thickness.
  • the passivation layer 150 includes two or more atomic layer deposition (ALD) oxides.
  • the passivation layer 150 may include at least one first layer 152 and at least one second layer 154 arranged in a staggered configuration.
  • the first layer 152 includes silicon dioxide.
  • the second layer 154 includes zirconium dioxide or hafnium dioxide.
  • the passivation layer 150 may be formed using atomic layer deposition processes.
  • a portion of the passivation layer 150 is removed to expose the top surface 142 and the upper surface 1322 .
  • the portion of the passivation layer 150 disposed on the top surface 132 and upper surface 1322 is removed, while the portion of the passivation layer 170 disposed on the sidewalls 144 , 172 , 1342 is left to protect against undercutting or notches in the protrusions 134 when the base 132 is subsequently etched.
  • the portion of the passivation layer 150 is removed using an anisotropic etching process.
  • the base 132 and the barrier layer 160 are etched through the trenches 190 (shown in FIG. 8 ) to form a plurality of metallic pillars 133 underlying the respective metallic protrusions 134 according to a step 216 in FIG. 2 . Accordingly, the semiconductor structure 10 is completely formed.
  • the metallic pillar 133 has a sidewall 1334 and a bottom surface 1336 adjacent to the sidewall 1334 . In some embodiments, an included angle ⁇ 2 between sidewalls 1334 and the bottom surface 1336 is in a range between 80 and 90 degrees.
  • the base 132 and the barrier layer 160 are etched using an etching process, such as a reactive ion etching (RIE) process.
  • RIE reactive ion etching
  • the RIE etching process utilizes Cl 2 and BCl 3 etchant gasses got the removal of the exposed portions of the base 132 and the barrier layer 160 to from the metallic pillars 133 .
  • the etching process stops at the insulating layer 120 .
  • the semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer.
  • the metallic pillars are disposed on the substrate.
  • the metallic protrusions extend from an upper surface of the metallic pillars.
  • the capping layer is disposed on the metallic protrusions.
  • the passivation layer is disposed on sidewalls of the protrusions and the capping layer.
  • One aspect of the present disclosure provides a method of manufacturing the semiconductor structure.
  • the method includes steps of providing a substrate; depositing a metallic layer and a capping layer on the substrate; patterning the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer, wherein the remaining metallic layer includes a base and a plurality of metallic protrusions connected to the base; depositing a passivation layer on sidewalls of the capping layer and the metallic protrusions; and patterning the base through the trenches to form a plurality of metallic pillars underlying the respective metallic protrusions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.

Description

PRIORITY CLAIM AND CROSS-REFERENCE
This application claims the priority benefit of U.S. provisional application Ser. No. 62/785,387, filed on Dec. 27, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
TECHNICAL FIELD
The present disclosure relates to a semiconductor structure and a method of manufacturing the same, and more particularly, to a high-aspect ratio metallic interconnect on a semiconductor substrate and a method of manufacturing the same.
DISCUSSION OF THE BACKGROUND
Semiconductor devices and integrated circuits are becoming more highly integrated. As a result, research is ongoing to improve characteristics of these devices and circuits, and to achieve desirable process margins. Therefore, photolithography processes for forming a pattern over a wafer are important parts of a microlithography process.
In general, interconnect layers are patterned and then etched to form conducting lines. However, at the completion of the etching process, reentrant undercutting has been observed at the interface of the metallic layer and the anti-reflection coating layer, which can lead to undesirable voids during subsequent filling with an inter-metal layer dielectric or, in the worst case, subsequent lifting of the aluminum layer, either of which degrades the yield of semiconductor devices.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
SUMMARY
One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the metallic protrusions and the capping layer.
In some embodiments, the sidewalls of the metallic protrusions are discontinuous with sidewalls of the metallic pillars.
In some embodiments, the metallic protrusions have a width substantially less than a width of the metallic pillars.
In some embodiments, an included angle between a sidewall and a bottom wall of the metallic pillar is in a range between 80 and 90 degrees.
In some embodiments, the semiconductor structure further includes an anti-reflective coating layer sandwiched between the metallic protrusion and the capping layer.
In some embodiments, the metallic protrusions have a height substantially greater than twice a height of the anti-reflective coating layer.
In some embodiments, the semiconductor structure further includes an insulating layer and a barrier layer; the insulating layer separates the metallic pillars from the substrate, and the barrier layer is sandwiched between the insulating layer and the metallic pillars.
In some embodiments, the passivation layer comprises at least one first layer and at least one second layer arranged in a staggered configuration.
In some embodiments, the metallic pillars and the metallic protrusions are integrally formed.
In some embodiments, wherein an outer periphery of the passivation layer is continuous with the sidewalls of the metallic pillars.
Another aspect of the present disclosure provides a method of manufacturing the semiconductor structure. The method includes steps of providing a substrate; depositing a metallic layer and a capping layer on the substrate; patterning the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer, wherein the remaining metallic layer includes a base and a plurality of metallic protrusions connected to the base; depositing a passivation layer on sidewalls of the capping layer and the metallic protrusions; and etching the base through the trenches to form a plurality of metallic pillars underlying the respective metallic protrusions.
In some embodiments, the deposition of the passivation layer on the sidewalls of the capping layer and the metallic protrusions includes steps of depositing the passivation layer on a top surface of the capping layer, the sidewalls of the capping layer and the protrusions, and an upper surface of the base; and performing an etching process to remove the passivation layer from the top surface and the upper surface.
In some embodiments, included angles between the upper surface of the base and the sidewalls of the metallic protrusions substantially equal to 90 degrees.
In some embodiments, the passivation layer is formed by an atomic layer deposition process.
In some embodiments, the passivation layer has a uniform thickness.
In some embodiments, the patterning of the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer includes steps of coating a photoresist layer on the capping layer; patterning the photoresist layer to form a photoresist pattern having a plurality of openings; and removing a portion of the capping layer exposed through the openings.
In some embodiments, the method further includes steps of forming an insulating layer on the substrate; and depositing a barrier layer on the insulating layer before the deposition of the metallic layer.
In some embodiments, the method further includes a step of depositing an anti-reflective coating layer on the metallic layer before the deposition of the capping layer.
In some embodiments, the etching of the base using Cl2 and BCl3 as etchant gases.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims. The disclosure should also be understood to be coupled to the figures' reference numbers, which refer to similar elements throughout the description.
FIG. 1 is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the present disclosure.
FIG. 2 is a flow diagram illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
FIGS. 3 through 9 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure.
 DETAILED DESCRIPTION
Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.
It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
FIG. 1 is a cross-sectional view of a semiconductor structure 10 in accordance with some embodiments of the present disclosure. Referring to FIG. 1, the semiconductor structure 10 includes a semiconductor substrate 110, an insulating layer 120 disposed on the semiconductor substrate 110, a plurality of metallic pillars 133 disposed on the insulating layer 120, a plurality of metallic protrusions 134 extending from an upper surface 1332 of the metallic pillars 133, a capping layer 140 disposed on the metallic protrusions 134, and a passivation layer 150 disposed on sidewalls 1402 of the capping layer 140 and sidewalls 1342 of the metallic protrusions 134.
In some embodiments, the insulating layer 120 including oxide may be a thermal oxidation layer or a deposition layer. In some embodiments, the metallic pillars 133 and the metallic protrusions 134 are integrally formed. In some embodiments, the metallic pillars 133 have sidewalls 1334 that are discontinuous with the sidewalls 1342 of the metallic protrusions 134. In some embodiments, the metallic pillars 133 have a width W1 substantially greater than a width W2 of the metallic pillars 134. In some embodiments, the capping layer 140 includes dielectric such as nitride.
In some embodiments, the passivation layer 150 provides passivation in the etch environment to protect against undercutting or notches of the sidewalls 1342 of the metallic protrusions 134. In some embodiments, the passivation layer 150 includes dielectric. In some embodiments, the passivation layer 150 may include one or more first layers 152 and one or more second layers 154 arranged in a staggered configuration. In some embodiments, the first layers 152 include silicon dioxide (SiO2). In some embodiments, the second layers 154 include zirconium dioxide (ZrO2) or hafnium dioxide (HfO2). In some embodiments, an outer periphery 152 of the passivation layer 150 is continuous with the sidewalls 1334 of the metallic pillars 133.
In some embodiments, the semiconductor structure 10 further includes a barrier layer 160 sandwiched between the insulating layer 120 and the metallic pillars 133. In some embodiments, the barrier layer 160 acts as a glue layer. In some embodiments, the barrier layer 160 may be a single-layered structure including titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). In some embodiments, the barrier layer 160 may have a multi-layered structure including one or more titanium layers and one or more titanium nitride layers; however, in some embodiments, the barrier layer 160 may be the multi-layered structure including one or more tantalum layers and one or more tantalum nitride layers. In some embodiments, sidewalls 1602 of the barrier layer 160 are continuous with sidewalls 1334 of the metallic pillars 133.
In some embodiments, the semiconductor structure 10 further includes an anti-reflective coating (ARC) layer 170 sandwiched between the metallic protrusions 134 and the capping layer 140. In some embodiments, the ARC layer 170 may be a multi-layered structure including at least one titanium layer and at least one titanium nitride layer. In some embodiments, the ARC layer 170 may be the multi-layered structure including at least one tantalum layer and at least one tantalum nitride layer. In some embodiments, the ARC layer 170 may be single-layered structure. In some embodiments, sidewalls 1702 of the ARC layer 170 are continuous with the sidewalls 1342 of the metallic protrusions 134.
FIG. 2 is a flow diagram illustrating a method 200 of manufacturing a semiconductor structure 10 in accordance with some embodiments of the present disclosure. FIGS. 3 to 9 are schematic diagrams illustrating various fabrication stages constructed according to the method 200 for manufacturing the semiconductor structure 10 in accordance with some embodiments of the present disclosure. The stages shown in FIGS. 3 to 9 are also illustrated schematically in the flow diagram in FIG. 2. In the subsequent discussion, the fabrication stages shown in FIGS. 3 to 9 are discussed in reference to the process steps in FIG. 2.
Referring to FIG. 3, a semiconductor substrate 110 is provided according to a step 202 in FIG. 2. In some embodiments, the semiconductor substrate 110 is a bulk substrate. In some embodiments, examples of the material suitable for the semiconductor substrate 110 include, but are not limited to, silicon, silicon on insulator, and silicon on sapphire.
Next, an insulating layer 120, a metallic layer 130 and a capping layer 140 are formed over the semiconductor substrate 110 according to a step 204 in FIG. 2. In some embodiments, the insulating layer 120 is in contact with the semiconductor substrate 110. In some embodiments, the insulating layer 120 includes oxide such as silicon dioxide (SiO2). In some embodiments, the insulating layer 120 is formed using a chemical vapor deposition (CVD) process or a thermal oxidation process.
In some embodiments, the metallic layer 130 is deposited on the insulating layer 120. In some embodiments, the metallic layer 130 includes aluminum (Al), copper (Cu), or a combination thereof, e.g., aluminum copper (AlCu). In some embodiments, the metallic layer 130 may be separated from the insulating layer 120 by a barrier layer 160. In some embodiments, the barrier layer 160 may improve adhesion of the metallic layer 130 to the insulating layer 120. In some embodiments, the barrier layer 160 may be a single-layered structure or a multi-layered structure. In some embodiments, refractory metals, refractory metal nitrides, and combinations thereof are typically used for the barrier layer 160. In some embodiments, the barrier layer 160 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN), tantalum silicon nitride (TaSiN), or the like. In some embodiments, the barrier layer 160 may be formed by a physical vapor deposition (PVD) process or a CVD process, for example.
The capping layer 140 is disposed on the metallic layer 130. In some embodiments, the capping layer 140 acts as a hard mask for patterning the metallic layer 130. In some embodiments, the capping layer 140 includes dielectric such as nitride.
In order to eliminate problems associated with back reflection of light during the patterning of the capping layer 140, it is common to form an anti-reflective coating (ARC) layer 170 between the metallic layer 130 and the capping layer 140. In some embodiments, the ARC layer 170 may be a single-layered structure or a multi-layered structure.
In some embodiments, the ARC layer 170 includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN) when it is a single-layered structure. In some embodiments, the ARC layer 170 may be formed by a PVD process or a CVD process, for example.
Next, a photoresist layer 180 is coated on the capping layer 140 according to a step 206 in FIG. 2. In some embodiments, the photoresist layer 180 is then patterned to define a region where the capping layer 140 and the ARC layer 170 are to be subsequently etched according to a step 208 in FIG. 2. In some embodiments, the photoresist layer 180 is patterned by steps including (1) exposing the photoresist layer 180 to a pattern (not shown), (2) performing a post-exposure back process, and (3) developing the photoresist layer 180, thereby forming a photoresist pattern 182, as shown in FIG. 4, having at least one opening 184. In some embodiments, a portion of the capping layer 140 to be subsequently etched is exposed through the openings 184.
Referring to FIG. 5, in some embodiments, a patterning process is performed to etch the capping layer 140 and the ARC layer 170 according to a step 210 in FIG. 2. Accordingly, at least one trench 190 penetrating through the capping layer 140 and the ARC layer 160 and in the metallic layer 130 are formed. In some embodiments, the etching process includes a dry etching process. In some embodiments, the dry etching process may be an anisotropic etching process.
In some embodiments, the remaining metallic layer 130 includes a base 132 and a plurality of protrusions 134 extending from a surface 1322 of the base 132. In some embodiments, a height H1 of the metallic protrusions 134 is greater than twice a height of the ARC layer 170. In some embodiments, an included angle θ1 between sidewalls 1342 of the protrusions 134 and the surface 1322 may be equal to 90 degrees. In some embodiments, the remaining ARC layer 170 and the remaining capping layer 140 overlap the protrusions 134. In some embodiments, a width of the metallic protrusions 134 is defined by a width of the photoresist pattern 182.
Referring to FIG. 6, after the patterning process, the photoresist pattern 182 is removed according to a step 212 in FIG. 2. In some embodiments, an ashing process or a wet strip process may be used to remove the photoresist pattern 182, wherein the wet strip process may chemically alter the photoresist pattern 182 so that it no longer adheres to the remaining capping layer 140.
Referring to FIG. 7, in some embodiments, a passivation layer 150 is deposited on the capping layer 130 and into the trenches 190 according to a step 214 in FIG. 2. In some embodiments, the passivation layer 150 is deposited on a top surface 142 of the capping layer 140, sidewalls 144 of the capping layer 140, sidewalls 172 of the ARC layer 170, sidewalls 1342 of the protrusions 134, and the upper surface 1322 of the base 132. In some embodiments, the passivation layer 150 is a substantially conformal layer. In some embodiments, the passivation layer 150 has a uniform thickness. In some embodiments, the passivation layer 150 includes two or more atomic layer deposition (ALD) oxides. In some embodiments, the passivation layer 150 may include at least one first layer 152 and at least one second layer 154 arranged in a staggered configuration. In some embodiments, the first layer 152 includes silicon dioxide. In some embodiments, the second layer 154 includes zirconium dioxide or hafnium dioxide. In some embodiments, the passivation layer 150 may be formed using atomic layer deposition processes.
Referring to FIG. 8, in some embodiments, a portion of the passivation layer 150 is removed to expose the top surface 142 and the upper surface 1322. In some embodiments, the portion of the passivation layer 150 disposed on the top surface 132 and upper surface 1322 is removed, while the portion of the passivation layer 170 disposed on the sidewalls 144, 172, 1342 is left to protect against undercutting or notches in the protrusions 134 when the base 132 is subsequently etched. In some embodiments, the portion of the passivation layer 150 is removed using an anisotropic etching process.
Referring to FIG. 9, in some embodiments, the base 132 and the barrier layer 160 are etched through the trenches 190 (shown in FIG. 8) to form a plurality of metallic pillars 133 underlying the respective metallic protrusions 134 according to a step 216 in FIG. 2. Accordingly, the semiconductor structure 10 is completely formed. In some embodiments, the metallic pillar 133 has a sidewall 1334 and a bottom surface 1336 adjacent to the sidewall 1334. In some embodiments, an included angle θ2 between sidewalls 1334 and the bottom surface 1336 is in a range between 80 and 90 degrees. In some embodiments, the base 132 and the barrier layer 160 are etched using an etching process, such as a reactive ion etching (RIE) process. In some embodiments, the RIE etching process utilizes Cl2 and BCl3 etchant gasses got the removal of the exposed portions of the base 132 and the barrier layer 160 to from the metallic pillars 133. In some embodiments, the etching process stops at the insulating layer 120.
One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.
One aspect of the present disclosure provides a method of manufacturing the semiconductor structure. The method includes steps of providing a substrate; depositing a metallic layer and a capping layer on the substrate; patterning the capping layer to form a plurality of trenches penetrating through the capping layer and in the metallic layer, wherein the remaining metallic layer includes a base and a plurality of metallic protrusions connected to the base; depositing a passivation layer on sidewalls of the capping layer and the metallic protrusions; and patterning the base through the trenches to form a plurality of metallic pillars underlying the respective metallic protrusions.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.

Claims (10)

What is claimed is:
1. A semiconductor structure, comprising:
a substrate;
a plurality of metallic pillars disposed on the substrate;
a plurality of metallic protrusions extending from an upper surface of the metallic pillars;
a plurality of capping layers disposed on the plurality of metallic protrusions, wherein each of the plurality of capping layers overlaps each of the plurality of metallic protrusions and each of the plurality of capping layers has a width substantially the same as a width of each of the plurality of metallic protrusions; and
a passivation layer disposed on sidewalls of the metallic protrusions and the capping layer.
2. The semiconductor structure of claim 1, wherein the sidewalls of the metallic protrusions are discontinuous with sidewalls of the metallic pillars.
3. The semiconductor structure of claim 2, wherein the metallic protrusions have the width substantially less than a width of the metallic pillars.
4. The semiconductor structure of claim 1, wherein an included angle between a sidewall and a bottom wall of the metallic pillar is in a range between 80 and 90 degrees.
5. The semiconductor structure of claim 1, further comprising an anti-reflective coating layer sandwiched between the metallic protrusion and the capping layer.
6. The semiconductor structure of claim 5, wherein the metallic protrusions have a height substantially greater than twice a height of the anti-reflective coating layer.
7. The semiconductor structure of claim 1, further comprising:
an insulating layer separating the metallic pillars from the substrate; and
a barrier layer sandwiched between the insulating layer and the metallic pillars.
8. The semiconductor structure of claim 1, wherein the passivation layer comprises at least one first layer and at least one second layer arranged in a staggered configuration.
9. The semiconductor structure of claim 1, wherein the metallic pillars and the metallic protrusions are integrally formed.
10. The semiconductor structure of claim 1, wherein an outer periphery of the passivation layer is continuous with the sidewalls of the metallic pillars.
US16/275,921 2018-12-27 2019-02-14 Semiconductor structure and method of manufacturing the same Active US10777522B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US16/275,921 US10777522B2 (en) 2018-12-27 2019-02-14 Semiconductor structure and method of manufacturing the same
TW108109568A TWI701791B (en) 2018-12-27 2019-03-20 Semiconductor structure and method of manufacturing the same
CN201910349745.1A CN111384013B (en) 2018-12-27 2019-04-28 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862785387P 2018-12-27 2018-12-27
US16/275,921 US10777522B2 (en) 2018-12-27 2019-02-14 Semiconductor structure and method of manufacturing the same

Publications (2)

Publication Number Publication Date
US20200211991A1 US20200211991A1 (en) 2020-07-02
US10777522B2 true US10777522B2 (en) 2020-09-15

Family

ID=71123148

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/275,921 Active US10777522B2 (en) 2018-12-27 2019-02-14 Semiconductor structure and method of manufacturing the same

Country Status (3)

Country Link
US (1) US10777522B2 (en)
CN (1) CN111384013B (en)
TW (1) TWI701791B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100221888A1 (en) 2006-01-09 2010-09-02 Macronix International Co., Ltd. Programmable Resistive RAM and Manufacturing Method
US20140273430A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Integrated cluster to enable next generation interconnect
US20140264853A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesion between Post-Passivation Interconnect Structure and Polymer
TW201730996A (en) 2014-05-23 2017-09-01 艾馬克科技公司 Copper pillar sidewall protection
TW201803171A (en) 2016-03-24 2018-01-16 台灣積體電路製造股份有限公司 Method for manufacturing semiconductor device
US20180151525A1 (en) 2016-11-29 2018-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layer structure and fabrication method therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100455387B1 (en) * 2002-05-17 2004-11-06 삼성전자주식회사 Method for forming a bump on semiconductor chip and COG package including the bump
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9978656B2 (en) * 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
KR101313690B1 (en) * 2011-12-30 2013-10-02 주식회사 동부하이텍 Method for fabricating bonding structure of semiconductor device
CN103325751A (en) * 2013-06-09 2013-09-25 华进半导体封装先导技术研发中心有限公司 Step-type micro convex point structure and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100221888A1 (en) 2006-01-09 2010-09-02 Macronix International Co., Ltd. Programmable Resistive RAM and Manufacturing Method
US20140264853A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesion between Post-Passivation Interconnect Structure and Polymer
US20140273430A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Integrated cluster to enable next generation interconnect
TW201730996A (en) 2014-05-23 2017-09-01 艾馬克科技公司 Copper pillar sidewall protection
TW201803171A (en) 2016-03-24 2018-01-16 台灣積體電路製造股份有限公司 Method for manufacturing semiconductor device
US20180151525A1 (en) 2016-11-29 2018-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layer structure and fabrication method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Office Action dated Dec. 4, 2019 related to Taiwanese Application No. 108109568.

Also Published As

Publication number Publication date
CN111384013B (en) 2021-09-21
TW202025423A (en) 2020-07-01
CN111384013A (en) 2020-07-07
TWI701791B (en) 2020-08-11
US20200211991A1 (en) 2020-07-02

Similar Documents

Publication Publication Date Title
US6083822A (en) Fabrication process for copper structures
TWI559367B (en) Lithography process using directed self assembly
US6268287B1 (en) Polymerless metal hard mask etching
US11121027B2 (en) High aspect ratio via etch using atomic layer deposition protection layer
US7659196B2 (en) Soluble hard mask for interlayer dielectric patterning
US8124537B2 (en) Method for etching integrated circuit structure
US6495452B1 (en) Method to reduce capacitance for copper interconnect structures
US8748323B2 (en) Patterning method
US20080085606A1 (en) Method for Fabricating a Structure for a Semiconductor Component, and Semiconductor Component
US7557038B2 (en) Method for fabricating self-aligned contact hole
TWI578440B (en) Conductive plug and method of forming the same
US10777522B2 (en) Semiconductor structure and method of manufacturing the same
JP2001093888A (en) Method for manufacturing semiconductor device
TWI717173B (en) Memory devices and methods for forming the same
US10903110B2 (en) Method of forming fine interconnection for a semiconductor device
US20200176377A1 (en) Electronic device and method of manufacturing the same
TWI638440B (en) Sacrificial amorphous silicon hard mask for beol
CN111986989A (en) Semiconductor structure and forming method thereof
CN109585363A (en) A kind of forming method and semiconductor devices of semiconductor devices
US8409938B2 (en) Method for fabricating semiconductor device
KR100750804B1 (en) The semiconductor device and the manufacturing method thereof
US10777450B2 (en) Semiconductor substrate and method of processing the same
US20240071769A1 (en) Method of manufacturing semiconductor structure with improved etching process
US20230317520A1 (en) Semiconductor structure and manufacturing method of the same
TW202412171A (en) Method of manufacturing semiconductor structure

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: NANYA TECHNOLOGY CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, CHIH-CHING;REEL/FRAME:048396/0257

Effective date: 20190107

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4