TWI726210B - 三維反及閘(3d-nand)元件中用於字元線分離之方法 - Google Patents

三維反及閘(3d-nand)元件中用於字元線分離之方法 Download PDF

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TWI726210B
TWI726210B TW107118233A TW107118233A TWI726210B TW I726210 B TWI726210 B TW I726210B TW 107118233 A TW107118233 A TW 107118233A TW 107118233 A TW107118233 A TW 107118233A TW I726210 B TWI726210 B TW I726210B
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metal
stack
oxide
tungsten
etching
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陳一宏
段子青
愛柏亥吉巴蘇 馬里克
勁文 陳
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美商應用材料股份有限公司
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Abstract

描述半導體元件(例如,3D-NAND)中字元線分離之方法。金屬膜沉積在字元線中及在間隔的氧化物層之堆疊之表面上。藉由高溫氧化及蝕刻氧化物,或藉由以單層方式氧化表面及蝕刻氧化物的低溫原子層蝕刻,來移除金屬膜。在移除金屬覆蓋層之後,字元線被金屬膜填充。

Description

三維反及閘(3D-NAND)元件中用於字元線分離之方法
本揭示案之實施例大致上關於填充半導體元件中的間隙或特徵之方法。更具體而言,本揭示案之實施例關於在三維半導體元件中藉由鎢的間隙填充之方法。
半導體及電子處理產業持續努力於更大的生產良率(production yield),同時增加沉積在具有更大表面積的基板上的層之均勻性。與新材料組合的這些相同因素亦提供基板之每面積的更高的積體電路集成度(integration)。隨著電路集成度提高,關於層厚度的更大的均勻性及製程控制的需求也提高。結果,已開發了各種技術以便以成本效益的方式在基板上沉積層,同時維持對層之特性的控制。
V-NAND或3D-NAND結構用於快閃記憶體應用中。V-NAND元件為垂直堆疊的NAND結構,具有以塊的形式排列的大量單元。後閘極(Gate-last)字元線形成為當前3D-NAND製造中的主流製造流程。在字元線形成之前,基板為由記憶體串(memory string)支撐的分層氧化物堆疊。使用CVD或ALD藉由鎢填充間隙空間。記憶體堆疊之頂部/側壁亦塗佈有鎢。藉由蝕刻製 程(例如,反應性離子蝕刻(RIE)製程或基於自由基的蝕刻製程)從堆疊之頂部/側壁移除鎢,使得鎢僅存在於間隙空間內並且每個鎢填充物與其他鎢填充物完全分離。然而,由於蝕刻製程之負載效應(loading effect),分離蝕刻經常造成在堆疊之頂部處與在底部處不同的字元線凹陷(recess)。隨著氧化物堆疊層增加,這種差異變得更加明顯。
因此,本領域需要在三維結構化元件中用於字元線分離的方法。
本揭示案之一或更多個實施例針對處理基板之方法。提供基板,該基板具有間隔的氧化物層之堆疊,且該等氧化物層之間具有間隙。該堆疊具有頂部及側面,且每個間隙可形成字元線。在該堆疊上沉積金屬,使得該金屬填充間隙並且以金屬覆蓋層(metal overburden)之厚度來覆蓋該堆疊之頂部及側面。將金屬進行氧化達約覆蓋層之厚度的深度,以在該堆疊之頂部及側面上形成金屬氧化物,並且將該金屬留在間隙中作為字元線。從該堆疊之頂部及側面蝕刻金屬氧化物,將金屬留在字元線中。
本揭示案之另外的實施例針對處理基板之方法。提供基板,該基板具有間隔的氧化物層之堆疊,且該等氧化物層之間具有間隙。該堆疊具有頂部及側面,且每個間隙可形成字元線。在該堆疊上沉積金屬,使得該金屬填充間隙並且以金屬覆蓋層之厚度來覆蓋該堆疊之頂部 及側面。重複地氧化金屬之表面以形成金屬氧化物及從該堆疊蝕刻該金屬氧化物,直到金屬覆蓋層被移除,將該金屬留在間隙中作為字元線。
本揭示案之進一步實施例針對處理基板之方法。提供基板,該基板具有間隔的氧化物層之堆疊,且該等氧化物層之間具有間隙。該堆疊具有頂部及側面,每個間隙可形成字元線。任選地在間隔的氧化物層上形成阻障層。阻障層包括TiN,TiN之厚度在約20Å至約50Å的範圍中。在該堆疊上沉積鎢,使得鎢填充間隙並且以鎢覆蓋層之厚度來覆蓋該堆疊之頂部及側面。重複地氧化鎢之表面以形成氧化鎢及蝕刻之以移除鎢覆蓋層。將鎢留在間隙中而與該堆疊之側面實質上齊平。氧化該表面的步驟包括暴露於O2,蝕刻氧化鎢的步驟包括暴露於WCl5或WCl6中之一或更多者。鎢沉積、鎢氧化及氧化鎢蝕刻在小於或等於約400℃的溫度下發生。
10:基板
11:記憶體串
12:堆疊
13:頂部
14:氧化物層
15:側面
16:間隙
19:字元線
20:金屬
22:覆蓋層
25:金屬氧化物
為了可得到詳細地瞭解本揭示案之上述特徵的方式,可藉由參照實施例來得到以上簡要總結的本揭示案之更特定敘述,該等實施例中之一些實施例繪示於附圖中。附圖僅繪示本揭示案之典型實施例,且因此不應被視為限制,因為本揭示案可容許其他等效實施例。
第1圖繪示根據本揭示案之一或更多個實施例的其中將形成字元線的氧化物層之堆疊; 第2圖繪示在第1圖之氧化物層之堆疊上形成的金屬膜;第3A圖及第3B圖繪示根據本揭示案之一或更多個實施例的高溫氧化及蝕刻製程;及第4A圖至第4D圖繪示根據本揭示案之一或更多個實施例的低溫氧化及蝕刻製程。
在描述本揭示案之若干示例性實施例之前,應理解,本揭示案不限於以下描述中記載的構造或製程步驟之細節。本揭示案能夠具有其他實施例並且能夠以各種方式來實踐或執行。
本文使用的「基板」指任何基板或在基板上形成的材料表面,在製造過程期間在該基板或材料表面上實行膜處理。例如,取決於應用,可在其上實行處理的基板表面包含如矽、氧化矽、應變矽、絕緣體上矽(SOI)、摻雜碳的矽氧化物、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石的材料,以及任何其他材料,如金屬、金屬氮化物、金屬合金及其他導電材料。基板包含但不限於半導體晶圓。可將基板暴露於預處理製程以拋光、蝕刻、還原、氧化、羥基化(hydroxylate)、退火、UV固化、電子束固化及/或烘烤基板表面。除了直接在基板本身之表面上進行膜處理之外,在本揭示案中,所揭示的膜處理步驟中之任一者亦可在基板上形成的底層(underlayer)上實行,如以下更詳細地揭示,並且用語「基板表面」欲包含 上下文指出的上述底層。因此,例如,在已將膜/層或部分膜/層沉積至基板表面上的情況下,新沉積的膜/層之暴露表面變成基板表面。
本揭示案之一或更多個實施例有利地提供在三維結構之間隙中沉積鎢膜之方法。本揭示案之一些實施例有利地提供沉積保形氧化鎢膜及選擇性氧化鎢移除之方法。一些實施例有利地提供由高品質鎢膜從氧化物堆疊之頂部至底部具有均勻的厚度來填充V-NAND之側向特徵的方法。
本揭示案之一或更多個實施例針對基於高度保形金屬(例如,鎢)氧化及高選擇性金屬氧化物(例如,氧化鎢)移除的字元線分離之方法。該等方法可使用高溫或低溫製程。
參照第1圖,基板10上具有數層之堆疊12。基板10可為任何適合的基板材料,並且不限於與個別層中之任一者相同的材料。例如,在一些實施例中,基板為氧化物、氮化物或金屬層。堆疊12具有複數個氧化物層14,氧化物層14彼此間隔開以在氧化物層14之間形成間隙16,使得每個間隙形成字元線或用於待形成的字元線的殼。堆疊12具有頂部13及側面15。
堆疊12可具有任何適合數量的氧化物層14或間隙16。在一些實施例中,堆疊12中形成有大於或等於約10、20、30、40、50、60、70、80、90或100個間隙16,該等間隙16可用以形成相同數量的字元線。在 連接所有個別氧化物層14的記憶體串11之任一側上量測間隙16之數量。在一些實施例中,間隙16之數量為2的倍數。在一些實施例中,間隙之數量等於2n,其中n為任何正整數。在一些實施例中,間隙16之數量約為96。
如第2圖所繪示,金屬20沉積在堆疊12上。金屬20填充間隙16以形成字元線19。金屬20形成在堆疊12的整個周圍,使得金屬20以金屬覆蓋層22之厚度來覆蓋堆疊12之頂部13及側面15。覆蓋層22為沉積在間隙16外側的材料。取決於用於沉積金屬20的製程,覆蓋層可具有任何適合的厚度。在一些實施例中,覆蓋層22之厚度在約1Å至約1000Å的範圍中。在一些實施例中,覆蓋層22之厚度大於或等於約5Å、10Å、15Å、20Å、25Å、30Å、35Å、40Å、45Å或50Å。
金屬20可為用於字元線應用中的任何適合的金屬。在一些具體實施例中,金屬膜包括鎢。在一些具體實施例中,金屬膜不包含鎢。在一些具體實施例中,金屬膜本質上由鎢組成。如在這方面使用的用語「本質上由鎢組成」意指塊材金屬膜之組成按原子計(atomic basis)為大於或等於約95%、98%或99%的鎢。塊材金屬膜不包含可能接觸另一個表面(例如,氧化物表面)或者開放用於進一步處理的金屬20之表面部分,因為這些區域可能具有與相鄰材料的一些少量的原子擴散或具有一些像氫化物終止(hydride termination)的表面部分(moiety)。
可藉由任何適合的技術來沉積金屬20,包含但不限於,化學氣相沉積(CVD)或原子層沉積(ALD)。金屬20沉積在間隙空間內及記憶體堆疊之頂部/側壁處。
參照第3A圖及第3B圖,繪示具有低溫蝕刻製程的高溫氧化。在第3A圖中,金屬20被氧化成金屬氧化物25達約為覆蓋層22之厚度的深度。實質上所有的覆蓋層22可在一個步驟氧化製程中被氧化。覆蓋層之氧化可受到例如氧化氣體流動、氧化氣體分壓、晶圓溫度及製程時間的影響,以形成金屬覆蓋層22之高度保形氧化。
氧化氣體可為任何適合的氧化氣體,其可與已沉積的金屬20反應。適合的氧化氣體包含但不限於O2、O3、H2O、H2O2、NO、NO2或其組合。在一些實施例中,氧化氣體包括O2或O3中之一或更多者。在一些實施例中,氧化氣體本質上由O2或O3中之一或更多者組成。如以此方式使用的用語「本質上由......組成」意指氧化氣體之氧化成分大於或等於所述物種的約95%、98%或99%。氧化氣體可包含惰性氣體、稀釋氣體或載氣。例如,氧化氣體可與Ar、He或N2中之一或更多者共流或以Ar、He或N2中之一或更多者來稀釋。
一些實施例之金屬氧化物25包括氧化鎢(WOx)。在一些實施例中,金屬氧化物25為金屬20之衍生物,其可包含或不包含氧。適合的金屬膜之衍生物包含但不限於氮化物(nitride)、硼化物(boride)、碳化物(carbide)、氮氧化物(oxynitride)、硼氧化物 (oxyboride)、碳氧化物(oxycarbide)、碳氮化物(carbonitride)、碳化硼(borocarbide)、氮化硼(boronitride)、碳氮化硼(borocarbonitride)、硼氧碳氮化物(borooxycarbonitride)、氧碳氮化物(oxycarbonitride)、硼氧碳化物(borooxycarbide)及氮氧化硼(borooxynitride)。本領域熟知技術者將理解,沉積的金屬膜可具有由金屬膜的非化學計量的原子數量。例如,指明為WO的膜可具有不同量的鎢及氧。WO膜可例如為90原子%的鎢。WO用於描述氧化鎢膜意指該膜包括鎢原子及氧原子,並且不應視為將膜限制為特定組成。在一些實施例中,膜本質上由指明的原子組成。例如,本質上由WO組成的膜意指膜之組成大於或等於約95%、98%或99%的鎢原子及氧原子。
在第3A圖及第3B圖繪示的製程中,氧化製程在高溫下發生。如在這方面使用的用語「高溫」意指溫度大於或等於約400℃、450℃、500℃、550℃、600℃、650℃、700℃、750℃、800℃或850℃。在一些實施例中,氧化製程之溫度在約400℃至約950℃的範圍中,或在約450℃至約900℃的範圍中,或在約500℃至約850℃的範圍中。
氧化製程期間的壓力可在約0.1托至約760托的範圍中。製程時間(暴露時間)可在約0.1秒至12小時的範圍中。壓力及製程時間可能受氧化製程期間的溫度影響。
在一些實施例中,覆蓋層22之金屬20被氧化以在堆疊12之頂部13及側面15上形成金屬氧化物25,同時將金屬20留在間隙16中以形成字元線19。在一些實施例中,實質上間隙16中的所有金屬20在氧化之後保留。如以此方式使用的用語「實質上所有」意指金屬20被氧化至堆疊12之側面15的±1Å內。
參照第3B圖,從堆疊12之頂部13及側面15蝕刻由覆蓋層22形成的金屬氧化物25,以在間隙16中留下金屬20作為字元線19。一些實施例之蝕刻製程為選擇性蝕刻製程,其將在實質上不影響金屬20的情況下移除金屬氧化物25。
在一些實施例中,蝕刻劑包括金屬鹵化物蝕刻劑。一些實施例之蝕刻劑本質上由金屬鹵化物蝕刻劑組成。如在這方面使用的用語「本質上由金屬鹵化物蝕刻劑組成」意指特定的金屬鹵化物蝕刻劑物種構成總金屬鹵化物蝕刻劑物種的95%、98%或99%(不包含惰性氣體、稀釋氣體或載氣)。金屬鹵化物蝕刻劑可具有與金屬氧化物25相同的金屬物種或不同的金屬物種。在一些實施例中,金屬鹵化物蝕刻劑包括與金屬氧化物25相同的金屬物種。
在一些實施例中,金屬鹵化物蝕刻劑包括本質上由氯組成的鹵素原子。如在這方面使用的用語「本質上由氯組成」意指氯按原子計構成金屬鹵化物蝕刻劑中鹵素原子的大於或等於約95%、98%或99%。
在一些實施例中,金屬鹵化物蝕刻劑包括WCl5或WCl6中之一或更多者。在一些實施例中,金屬鹵化物蝕刻劑本質上由WCl5或WCl6中之一或更多者組成。如在這方面使用的用語「本質上由......組成」意指所述物種以莫耳計(molar basis)構成金屬鹵化物的大於或等於約95%、98%或99%。
一些實施例之蝕刻溫度低於氧化期間的溫度。在一些實施例中,蝕刻溫度在約300℃至約600℃的範圍中,或在約400℃至約500℃的範圍中。在一些實施例中,蝕刻溫度小於或等於約600℃、550℃、500℃、450℃、400℃或350℃。在一些實施例中,蝕刻期間的溫度比氧化期間的溫度低了大於或等於約50℃、75℃、100℃、125℃或150℃。在一些實施例中,氧化及蝕刻兩者皆在大於或等於約400℃的溫度下發生。
在蝕刻金屬氧化物25之後,移除金屬覆蓋層22,並且保留在間隙16中作為字元線19的金屬20與堆疊12之側面15實質上齊平。如以此方式使用的用語「實質上齊平」意指間隙16內的字元線19在堆疊12之側面15的±1Å內。
第3A圖及第3B圖中繪示的實施例示出高溫氧化一低溫蝕刻製程。第4A圖至第4D圖中繪示的實施例示出低溫氧化及蝕刻製程。這些製程之間的一些差異包含但不限於較低溫度氧化及較慢地移除覆蓋層。
在堆疊12使金屬20形成有覆蓋層22之後(如第2圖所示),可藉由原子層蝕刻類型製程來實行覆蓋層之移除。原子層蝕刻製程可包含多個重複製程,其修改待蝕刻的表面,然後揮發或移除修改的表面,從而暴露下方的新表面。
參照第4A圖,覆蓋層22被氧化以在覆蓋層22之表面上形成金屬氧化物25。氧化製程可使用與第3A圖中繪示的實施例相同的試劑及參數,而具有一些改變以允許發生原子層蝕刻(ALE)製程。一些實施例之氧化製程發生在約300℃至約500℃的範圍中的溫度下。在一些實施例中,氧化發生在小於或等於約500℃、450℃、400℃或350℃的溫度下。低溫氧化製程期間的壓力可在約0.1托至約760托的範圍中。製程或暴露時間可在約0.001秒至約60秒的範圍中。在原子層蝕刻製程中,每個氧化及蝕刻製程皆為自限制的,因為一旦已與反應性表面位置(active surface site)反應,該製程即停止。例如,一旦金屬20之所有反應性表面位置暴露於氧化劑並且與氧化劑反應形成金屬氧化物25膜,即不容易發生進一步氧化。類似地,一旦蝕刻劑已移除氧化物膜以暴露下方的新鮮金屬20,蝕刻劑即不具有待移除的進一步氧化物。
參照第4B圖,在金屬20上形成金屬氧化物25之後,將堆疊12暴露於蝕刻劑。蝕刻劑及蝕刻條件可與關於第3B圖所述的蝕刻劑及蝕刻條件相同。金屬20上的 金屬氧化物25層比第3A圖及第3B圖中繪示的實施例薄,使得蝕刻製程將花費較少時間。在一些實施例中,蝕刻劑製程時間在約0.1秒至約60秒的範圍中。
在一些實施例中,氧化及蝕刻製程期間的溫度在小於或等於約400℃的溫度下發生。第4B圖中示出的蝕刻製程之溫度可與第4A圖之氧化製程相同,使得含有堆疊12的基板可快速地從處理腔室之一個處理區域移動至處理腔室之另一個處理區域,以依序地將基板暴露於氧化及蝕刻條件。
此類型的ALE製程可稱作空間(spatial)ALE,其中各種反應性氣體(例如,氧化劑及蝕刻劑)流入處理腔室之分離區域,並且基板在區域之間移動。藉由包括一或更多個淨化氣流及/或真空流的氣幕(gas curtain)來分離不同的處理區域,以防止氧化劑與蝕刻劑在氣相中混合。ALE製程亦可藉由時域處理來實行,其中處理腔室充滿氧化劑,進行淨化以移除過量的氧化劑及反應產物或副產物,充滿蝕刻劑,然後進行淨化以移除過量的蝕刻劑及反應產物或副產物。在時域處理中,基板可維持靜止。
第4C圖及第4D圖分別示出重複暴露於氧化劑以形成金屬氧化物25與暴露於蝕刻劑以移除金屬氧化物。儘管製程繪示為使用兩個循環,但本領域熟知技術者將理解,這僅為代表,並且可使用多於兩個的循環來移除覆蓋層22並且將金屬20留在間隙16中作為字元線19。
在一些實施例中,在沉積金屬20之前,在氧化物層14上形成阻障層。阻障層可為任何適合的阻障材料。在一些實施例中,阻障層包括氮化鈦。在一些實施例中,阻障層本質上由氮化鈦組成。如以此方式使用的用語「本質上由氮化鈦組成」意指阻障層之組成按原子計為大於或等於約95%、98%或99%的鈦原子及氮原子。阻障層之厚度可為任何適合的厚度。在一些實施例中,阻障層之厚度在約20Å至約50Å的範圍中。
貫穿本說明書對「一個實施例」、「某些實施例」、「一或更多個實施例」或「實施例」的參照意指結合實施例所述的特定特徵、結構、材料或特性包含於本揭示案之至少一個實施例中。因此,在貫穿本說明書中各處出現的短語如「在一或更多個實施例中」、「在某些實施例中」、「在一個實施例中」或「在實施例中」未必指本揭示案之相同的實施例。此外,特定特徵、結構、材料或特性可在一或更多個實施例中以任何適合的方式來組合。
儘管已參照特定實施例描述了本揭示案,但應理解,這些實施例僅為說明本揭示案之原理及應用。對於本領域熟知技術者顯而易見的是,在不脫離本揭示案之精神及範疇下,可對本揭示案之方法及設備作各種修改及變化。因此,預期本揭示案包含在所附申請專利範圍及其均等物之範疇內的修改及變化。
10‧‧‧基板
12‧‧‧堆疊
13‧‧‧頂部
14‧‧‧氧化物層
15‧‧‧側面
16‧‧‧間隙
19‧‧‧字元線
22‧‧‧覆蓋層
25‧‧‧金屬氧化物

Claims (20)

  1. 一種處理一基板之方法,該方法包括以下步驟: 提供一基板,該基板具有間隔的氧化物層之一堆疊,且該等氧化物層之間具有間隙,該堆疊具有一頂部及側面,每個間隙可形成一字元線;在該堆疊上沉積一金屬,使得該金屬填充該等間隙並且以一金屬覆蓋層之厚度來覆蓋該堆疊之該頂部及該等側面;將該金屬進行氧化達約該覆蓋層之厚度的一深度,以在該堆疊之該頂部及該等側面上形成一金屬氧化物,並且將該金屬留在該等間隙中作為字元線;及從該堆疊之該頂部及該等側面蝕刻該金屬氧化物,將該金屬留在該等字元線中。
  2. 如請求項1所述之方法,其中該金屬包括鎢,並且該金屬氧化物包括氧化鎢。
  3. 如請求項1所述之方法,其中該金屬本質上由鎢組成。
  4. 如請求項1所述之方法,進一步包括在該等氧化物層上形成一阻障層的步驟,並且該金屬沉積在該阻障層上。
  5. 如請求項4所述之方法,其中該阻障層包括TiN,TiN之厚度在約20Å至約50Å的範圍中。
  6. 如請求項1所述之方法,其中存在多於50個的字元線。
  7. 如請求項1所述之方法,其中在蝕刻該金屬氧化物之後,移除該金屬覆蓋層,並且在該等間隙中形成字元線的該金屬與該堆疊之該等側面實質上齊平。
  8. 如請求項1所述之方法,其中該氧化及蝕刻在大於或等於約400ºC的一溫度下發生。
  9. 如請求項1所述之方法,其中蝕刻該金屬氧化物的步驟包括以下步驟:將該金屬氧化物暴露於一金屬鹵化物蝕刻劑。
  10. 一種處理一基板之方法,該方法包括以下步驟: 提供一基板,該基板具有間隔的氧化物層之一堆疊,且該等氧化物層之間具有間隙,該堆疊具有一頂部及側面,每個間隙可形成一字元線;在該堆疊上沉積一金屬,使得該金屬填充該等間隙並且以一金屬覆蓋層之厚度來覆蓋該堆疊之該頂部及該等側面;及重複氧化該金屬之一表面以形成一金屬氧化物的步驟與從該堆疊蝕刻該金屬氧化物的步驟,直到該金屬覆蓋層被移除,將該金屬留在該等間隙中作為字元線。
  11. 如請求項10所述之方法,其中該金屬包括鎢,並且該金屬氧化物包括氧化鎢。
  12. 如請求項10所述之方法,其中該金屬本質上由鎢組成。
  13. 如請求項10所述之方法,進一步包括在該等間隔的氧化物層上形成一阻障層的步驟,並且該金屬沉積在該阻障層上。
  14. 如請求項13所述之方法,其中該阻障層包括TiN,TiN之厚度在約20Å至約50Å的範圍中。
  15. 如請求項10所述之方法,其中存在多於50個的字元線。
  16. 如請求項10所述之方法,其中在蝕刻之後,移除該金屬覆蓋層,並且在該等字元線中的該金屬與該堆疊之該等側面實質上齊平。
  17. 如請求項10所述之方法,其中該氧化及蝕刻在小於或等於約400ºC的一溫度下發生。
  18. 如請求項10所述之方法,其中蝕刻該金屬氧化物的步驟包括以下步驟:將該金屬氧化物暴露於一金屬鹵化物蝕刻劑。
  19. 如請求項10所述之方法,其中氧化該金屬之該表面的步驟包括以下步驟:將該金屬暴露於O2
  20. 一種處理一基板之方法,該方法包括以下步驟: 提供一基板,該基板具有間隔的氧化物層之一堆疊,且該等氧化物層之間具有間隙,該堆疊具有一頂部及側面,每個間隙可形成一字元線;任選地在該等間隔的氧化物層上形成一阻障層,該阻障層包括TiN,TiN之厚度在約20Å至約50Å的範圍中;在該堆疊上沉積鎢,使得該鎢填充該等間隙並且以一鎢覆蓋層之厚度來覆蓋該堆疊之該頂部及該等側面;及重複氧化該鎢之一表面以形成氧化鎢的步驟與從該堆疊蝕刻該氧化鎢的步驟,直到該鎢覆蓋層被移除,將該鎢留在該等間隙中而與該堆疊之該等側面實質上齊平,氧化該表面的步驟包括暴露於O2 ,並且蝕刻該氧化鎢的步驟包括暴露於WCl5 或WCl6 中之一或更多者,其中,沉積該鎢的步驟、氧化該鎢的步驟及蝕刻該氧化鎢的步驟在小於或等於約400ºC的一溫度下發生。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10950498B2 (en) 2017-05-31 2021-03-16 Applied Materials, Inc. Selective and self-limiting tungsten etch process
JP2020522130A (ja) 2017-05-31 2020-07-27 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 3d−nandデバイスでのワードライン分離のための方法
US10622221B2 (en) 2017-12-14 2020-04-14 Applied Materials, Inc. Methods of etching metal oxides with less etch residue
CN110896671B (zh) 2019-03-29 2021-07-30 长江存储科技有限责任公司 三维存储器件及其制造方法
JP2022519752A (ja) 2019-03-29 2022-03-24 長江存儲科技有限責任公司 3次元メモリデバイス
CN110914986B (zh) 2019-03-29 2021-05-14 长江存储科技有限责任公司 三维存储器件及其制造方法
CN110896672B (zh) 2019-03-29 2021-05-25 长江存储科技有限责任公司 三维存储器件及其制造方法
CN110896670B (zh) 2019-03-29 2021-06-08 长江存储科技有限责任公司 三维存储器件及其制造方法
US11189635B2 (en) 2019-04-01 2021-11-30 Applied Materials, Inc. 3D-NAND mold
US11638377B2 (en) 2019-09-13 2023-04-25 Applied Materials, Inc. Self-aligned select gate cut for 3D NAND
TW202115827A (zh) * 2019-09-26 2021-04-16 美商應用材料股份有限公司 選擇性和自我限制性之鎢蝕刻製程
US11587796B2 (en) 2020-01-23 2023-02-21 Applied Materials, Inc. 3D-NAND memory cell structure
US11930637B2 (en) 2020-06-19 2024-03-12 Applied Materials, Inc. Confined charge trap layer
US20230232624A1 (en) * 2022-01-18 2023-07-20 Sandisk Technologies Llc Three-dimensional memory device containing self-aligned isolation strips and methods for forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235632B1 (en) * 1998-01-13 2001-05-22 Advanced Micro Devices, Inc. Tungsten plug formation
US20100276743A1 (en) * 2007-12-27 2010-11-04 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US8865594B2 (en) * 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US20160343718A1 (en) * 2015-05-20 2016-11-24 Sandisk Technologies Inc. Memory Hole Last Boxim

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3649512A (en) 1970-06-25 1972-03-14 Varian Associates Large area sputtering target electrode structure
DE3613018A1 (de) 1986-04-17 1987-10-22 Santos Pereira Ribeiro Car Dos Magnetron-zerstaeubungskathode
KR100291330B1 (ko) 1998-07-02 2001-07-12 윤종용 반도체장치제조용스퍼터링설비및이를이용한스퍼터링방법
WO2002022300A1 (en) 2000-09-11 2002-03-21 Tosoh Smd, Inc. Method of manufacturing sputter targets with internal cooling channels
JP2002220661A (ja) 2001-01-29 2002-08-09 Sharp Corp スパッタリング装置に用いられるバッキングプレートおよびスパッタリング方法
US7691240B2 (en) 2005-05-02 2010-04-06 Honeywell International Inc. Target assemblies, targets, backing plates, and methods of target cooling
US20070045108A1 (en) 2005-08-26 2007-03-01 Demaray Richard E Monolithic sputter target backing plate with integrated cooling passages
KR20090020210A (ko) * 2007-08-23 2009-02-26 삼성전자주식회사 반도체 소자의 게이트 구조물 형성 방법
JP2009158775A (ja) * 2007-12-27 2009-07-16 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
FR2933802B1 (fr) * 2008-07-10 2010-10-15 Commissariat Energie Atomique Structure et procede de realisation d'un dispositif microelectronique de memoire 3d de type flash nand.
KR101604054B1 (ko) * 2009-09-03 2016-03-16 삼성전자주식회사 반도체 소자 및 그 형성방법
KR101669470B1 (ko) * 2009-10-14 2016-10-26 삼성전자주식회사 금속 실리사이드층을 포함하는 반도체 소자
KR20120003351A (ko) * 2010-07-02 2012-01-10 삼성전자주식회사 3차원 비휘발성 메모리 장치 및 그 동작방법
US8659944B2 (en) * 2010-09-01 2014-02-25 Macronix International Co., Ltd. Memory architecture of 3D array with diode in memory string
TWI427744B (zh) * 2010-09-01 2014-02-21 Macronix Int Co Ltd 具有二極體於記憶串列中的三維陣列記憶體架構
CN102569203A (zh) * 2010-12-20 2012-07-11 中国科学院微电子研究所 一种三维多值非挥发存储器的制备方法
KR20130024303A (ko) * 2011-08-31 2013-03-08 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8946082B2 (en) * 2011-09-16 2015-02-03 GlobalFoundries, Inc. Methods for forming semiconductor devices
JP2013065777A (ja) 2011-09-20 2013-04-11 Toshiba Corp 半導体装置および半導体装置の製造方法
KR20130066950A (ko) 2011-12-13 2013-06-21 에스케이하이닉스 주식회사 3차원 불휘발성 메모리 소자와, 이를 포함하는 메모리 시스템과, 그 제조방법
US20140061039A1 (en) 2012-09-05 2014-03-06 Applied Materials, Inc. Target cooling for physical vapor deposition (pvd) processing systems
US9076879B2 (en) * 2012-09-11 2015-07-07 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device and method for fabricating the same
KR102031179B1 (ko) * 2012-09-11 2019-11-08 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US9252151B2 (en) * 2013-07-08 2016-02-02 Sandisk Technologies Inc. Three dimensional NAND device with birds beak containing floating gates and method of making thereof
KR102161814B1 (ko) * 2013-11-19 2020-10-06 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
JP6478813B2 (ja) * 2015-05-28 2019-03-06 東京エレクトロン株式会社 金属膜の成膜方法
US9449843B1 (en) * 2015-06-09 2016-09-20 Applied Materials, Inc. Selectively etching metals and metal nitrides conformally
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
EP3375008B1 (en) * 2015-11-10 2020-05-20 L'Air Liquide Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Plasma-free etching process
EP3375007A4 (en) 2015-11-12 2019-07-31 Honeywell International Inc. CARRIER PLATE ASSEMBLY WITH COOLING STRUCTURE FOR SPUTTER TARGETS
TWI651787B (zh) 2016-04-07 2019-02-21 旺宏電子股份有限公司 半導體結構與其製造方法
US10325763B2 (en) 2017-01-20 2019-06-18 Applied Materials, Inc. Physical vapor deposition processing systems target cooling
JP2020522130A (ja) 2017-05-31 2020-07-27 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 3d−nandデバイスでのワードライン分離のための方法
KR20190104902A (ko) 2018-03-02 2019-09-11 마이크로머티어리얼즈 엘엘씨 금속 산화물들을 제거하기 위한 방법들

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235632B1 (en) * 1998-01-13 2001-05-22 Advanced Micro Devices, Inc. Tungsten plug formation
US20100276743A1 (en) * 2007-12-27 2010-11-04 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US8865594B2 (en) * 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US20160343718A1 (en) * 2015-05-20 2016-11-24 Sandisk Technologies Inc. Memory Hole Last Boxim

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