JP2021517734A5 - - Google Patents

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Publication number
JP2021517734A5
JP2021517734A5 JP2020544399A JP2020544399A JP2021517734A5 JP 2021517734 A5 JP2021517734 A5 JP 2021517734A5 JP 2020544399 A JP2020544399 A JP 2020544399A JP 2020544399 A JP2020544399 A JP 2020544399A JP 2021517734 A5 JP2021517734 A5 JP 2021517734A5
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JP
Japan
Prior art keywords
shallow trench
trench
dielectric layer
forming
oxide
Prior art date
Application number
JP2020544399A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021517734A (ja
JP7755114B2 (ja
JPWO2019165107A5 (https=
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Priority claimed from US15/901,449 external-priority patent/US10879106B2/en
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Publication of JP2021517734A publication Critical patent/JP2021517734A/ja
Publication of JP2021517734A5 publication Critical patent/JP2021517734A5/ja
Publication of JPWO2019165107A5 publication Critical patent/JPWO2019165107A5/ja
Priority to JP2024033763A priority Critical patent/JP2024063193A/ja
Application granted granted Critical
Publication of JP7755114B2 publication Critical patent/JP7755114B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2020544399A 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 Active JP7755114B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024033763A JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/901,449 US10879106B2 (en) 2018-02-21 2018-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US15/901,449 2018-02-21
PCT/US2019/019005 WO2019165107A1 (en) 2018-02-21 2019-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024033763A Division JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Publications (4)

Publication Number Publication Date
JP2021517734A JP2021517734A (ja) 2021-07-26
JP2021517734A5 true JP2021517734A5 (https=) 2022-02-24
JPWO2019165107A5 JPWO2019165107A5 (https=) 2022-02-24
JP7755114B2 JP7755114B2 (ja) 2025-10-16

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ID=67616963

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2020544399A Active JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Family Applications After (1)

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JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Country Status (5)

Country Link
US (2) US10879106B2 (https=)
EP (1) EP3756213B1 (https=)
JP (2) JP7755114B2 (https=)
CN (1) CN112204705A (https=)
WO (1) WO2019165107A1 (https=)

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US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US11443976B2 (en) 2020-10-20 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Trench isolation process
US11264457B1 (en) * 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US11410873B2 (en) * 2020-11-20 2022-08-09 Applied Materials, Inc. Deep trench integration processes and devices
CN112750752B (zh) * 2021-01-22 2023-06-02 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US12354904B2 (en) * 2021-10-27 2025-07-08 Texas Instruments Incorporated Method of reducing integrated deep trench optically sensitive defectivity
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242649B (zh) * 2021-12-16 2026-02-03 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607B (zh) * 2024-03-27 2024-06-21 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件
CN121194505A (zh) * 2025-11-20 2025-12-23 杭州富芯半导体有限公司 一种双极元件-cmos-dmos半导体器件的制备方法及半导体器件

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