JP7755114B2 - 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 - Google Patents

低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

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Publication number
JP7755114B2
JP7755114B2 JP2020544399A JP2020544399A JP7755114B2 JP 7755114 B2 JP7755114 B2 JP 7755114B2 JP 2020544399 A JP2020544399 A JP 2020544399A JP 2020544399 A JP2020544399 A JP 2020544399A JP 7755114 B2 JP7755114 B2 JP 7755114B2
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shallow trench
trench
forming
layer
dielectric layer
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JP2021517734A5 (https=
JP2021517734A (ja
JPWO2019165107A5 (https=
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エドワード リリブリッジ トーマス
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テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2021517734A5 publication Critical patent/JP2021517734A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6332—Deposition from the gas or vapour phase using thermal evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020544399A 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 Active JP7755114B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024033763A JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/901,449 US10879106B2 (en) 2018-02-21 2018-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US15/901,449 2018-02-21
PCT/US2019/019005 WO2019165107A1 (en) 2018-02-21 2019-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024033763A Division JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Publications (4)

Publication Number Publication Date
JP2021517734A JP2021517734A (ja) 2021-07-26
JP2021517734A5 JP2021517734A5 (https=) 2022-02-24
JPWO2019165107A5 JPWO2019165107A5 (https=) 2022-02-24
JP7755114B2 true JP7755114B2 (ja) 2025-10-16

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Family Applications (2)

Application Number Title Priority Date Filing Date
JP2020544399A Active JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Country Status (5)

Country Link
US (2) US10879106B2 (https=)
EP (1) EP3756213B1 (https=)
JP (2) JP7755114B2 (https=)
CN (1) CN112204705A (https=)
WO (1) WO2019165107A1 (https=)

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US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US11443976B2 (en) 2020-10-20 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Trench isolation process
US11264457B1 (en) * 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US11410873B2 (en) * 2020-11-20 2022-08-09 Applied Materials, Inc. Deep trench integration processes and devices
CN112750752B (zh) * 2021-01-22 2023-06-02 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US12354904B2 (en) * 2021-10-27 2025-07-08 Texas Instruments Incorporated Method of reducing integrated deep trench optically sensitive defectivity
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242649B (zh) * 2021-12-16 2026-02-03 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607B (zh) * 2024-03-27 2024-06-21 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件
CN121194505A (zh) * 2025-11-20 2025-12-23 杭州富芯半导体有限公司 一种双极元件-cmos-dmos半导体器件的制备方法及半导体器件

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JP2004260151A (ja) 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
JP2006108646A (ja) 2004-09-08 2006-04-20 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2008541446A (ja) 2005-05-11 2008-11-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｓｏｉデバイスの製造方法
JP2011243638A (ja) 2010-05-14 2011-12-01 Sharp Corp 半導体装置の製造方法
JP2017517154A (ja) 2014-05-27 2017-06-22 日本テキサス・インスツルメンツ株式会社 ウェルレジスタ及びポリシリコンレジスタ

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US4579812A (en) * 1984-02-03 1986-04-01 Advanced Micro Devices, Inc. Process for forming slots of different types in self-aligned relationship using a latent image mask
JPH02248063A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd 半導体装置及びその製造方法
US5972777A (en) * 1997-07-23 1999-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming isolation by nitrogen implant to reduce bird's beak
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
US7205630B2 (en) * 2004-07-12 2007-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device having low and high voltage transistors
US8053823B2 (en) * 2005-03-08 2011-11-08 International Business Machines Corporation Simplified buried plate structure and process for semiconductor-on-insulator chip
DE102005010944B4 (de) * 2005-03-10 2009-09-10 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung eines Trägerscheibenkontaktes in integrierten Schaltungen mit Hochspannungsbauelementen auf der Basis der SOI-Technologie und integrierte Schaltungen mit entsprechenden Grabenstrukturen
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JP5977002B2 (ja) * 2011-08-25 2016-08-24 東京エレクトロン株式会社 トレンチの埋め込み方法および半導体集積回路装置の製造方法
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US10163679B1 (en) * 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization
US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

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JP2004260151A (ja) 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
JP2006108646A (ja) 2004-09-08 2006-04-20 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2008541446A (ja) 2005-05-11 2008-11-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｓｏｉデバイスの製造方法
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Also Published As

Publication number Publication date
JP2024063193A (ja) 2024-05-10
EP3756213B1 (en) 2025-05-21
EP3756213A1 (en) 2020-12-30
JP2021517734A (ja) 2021-07-26
US20210090941A1 (en) 2021-03-25
CN112204705A (zh) 2021-01-08
WO2019165107A1 (en) 2019-08-29
WO2019165107A8 (en) 2020-12-03
US20190259651A1 (en) 2019-08-22
EP3756213A4 (en) 2021-04-28
US10879106B2 (en) 2020-12-29

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