CN112204705A - 具有重叠深沟槽和浅沟槽的装置及制造具有低缺陷密度的类似装置的方法 - Google Patents

具有重叠深沟槽和浅沟槽的装置及制造具有低缺陷密度的类似装置的方法 Download PDF

Info

Publication number
CN112204705A
CN112204705A CN201980012220.7A CN201980012220A CN112204705A CN 112204705 A CN112204705 A CN 112204705A CN 201980012220 A CN201980012220 A CN 201980012220A CN 112204705 A CN112204705 A CN 112204705A
Authority
CN
China
Prior art keywords
shallow trench
trench
shallow
deep
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980012220.7A
Other languages
English (en)
Chinese (zh)
Inventor
T·E·利利布里奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN112204705A publication Critical patent/CN112204705A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6332—Deposition from the gas or vapour phase using thermal evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201980012220.7A 2018-02-21 2019-02-21 具有重叠深沟槽和浅沟槽的装置及制造具有低缺陷密度的类似装置的方法 Pending CN112204705A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/901,449 US10879106B2 (en) 2018-02-21 2018-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US15/901,449 2018-02-21
PCT/US2019/019005 WO2019165107A1 (en) 2018-02-21 2019-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Publications (1)

Publication Number Publication Date
CN112204705A true CN112204705A (zh) 2021-01-08

Family

ID=67616963

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980012220.7A Pending CN112204705A (zh) 2018-02-21 2019-02-21 具有重叠深沟槽和浅沟槽的装置及制造具有低缺陷密度的类似装置的方法

Country Status (5)

Country Link
US (2) US10879106B2 (https=)
EP (1) EP3756213B1 (https=)
JP (2) JP7755114B2 (https=)
CN (1) CN112204705A (https=)
WO (1) WO2019165107A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242649A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607A (zh) * 2024-03-27 2024-05-03 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US11443976B2 (en) 2020-10-20 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Trench isolation process
US11264457B1 (en) * 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US11410873B2 (en) * 2020-11-20 2022-08-09 Applied Materials, Inc. Deep trench integration processes and devices
CN112750752B (zh) * 2021-01-22 2023-06-02 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US12354904B2 (en) * 2021-10-27 2025-07-08 Texas Instruments Incorporated Method of reducing integrated deep trench optically sensitive defectivity
CN121194505A (zh) * 2025-11-20 2025-12-23 杭州富芯半导体有限公司 一种双极元件-cmos-dmos半导体器件的制备方法及半导体器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004260151A (ja) * 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) * 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
CN102244004A (zh) * 2010-05-14 2011-11-16 夏普株式会社 半导体器件的制造方法
US8703577B1 (en) * 2012-12-17 2014-04-22 United Microelectronics Corp. Method for fabrication deep trench isolation structure

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124840A (ja) * 1983-12-09 1985-07-03 Fujitsu Ltd 半導体装置の製造方法
US4579812A (en) * 1984-02-03 1986-04-01 Advanced Micro Devices, Inc. Process for forming slots of different types in self-aligned relationship using a latent image mask
JPH02248063A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd 半導体装置及びその製造方法
US5972777A (en) * 1997-07-23 1999-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming isolation by nitrogen implant to reduce bird's beak
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
US7205630B2 (en) * 2004-07-12 2007-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device having low and high voltage transistors
JP4646743B2 (ja) * 2004-09-08 2011-03-09 三洋電機株式会社 半導体装置の製造方法
US8053823B2 (en) * 2005-03-08 2011-11-08 International Business Machines Corporation Simplified buried plate structure and process for semiconductor-on-insulator chip
DE102005010944B4 (de) * 2005-03-10 2009-09-10 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung eines Trägerscheibenkontaktes in integrierten Schaltungen mit Hochspannungsbauelementen auf der Basis der SOI-Technologie und integrierte Schaltungen mit entsprechenden Grabenstrukturen
US7361534B2 (en) * 2005-05-11 2008-04-22 Advanced Micro Devices, Inc. Method for fabricating SOI device
US7709345B2 (en) * 2006-03-07 2010-05-04 Micron Technology, Inc. Trench isolation implantation
US20090314963A1 (en) * 2008-06-24 2009-12-24 Tel Epion Inc. Method for forming trench isolation
JP2010161241A (ja) * 2009-01-08 2010-07-22 Toyota Motor Corp 半導体装置および半導体装置の製造方法
US20110217832A1 (en) * 2009-09-30 2011-09-08 Digvijay Raorane Method of filling a deep trench in a substrate
KR101201903B1 (ko) * 2010-07-20 2012-11-16 매그나칩 반도체 유한회사 반도체소자의 소자분리 구조 및 그 형성방법
JP5977002B2 (ja) * 2011-08-25 2016-08-24 東京エレクトロン株式会社 トレンチの埋め込み方法および半導体集積回路装置の製造方法
US20130292791A1 (en) * 2012-05-01 2013-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same
US9202859B1 (en) * 2014-05-27 2015-12-01 Texas Instruments Incorporated Well resistors and polysilicon resistors
US9887123B2 (en) * 2014-10-24 2018-02-06 Newport Fab, Llc Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method
US9812354B2 (en) 2015-05-15 2017-11-07 Semiconductor Components Industries, Llc Process of forming an electronic device including a material defining a void
KR102449901B1 (ko) 2015-06-23 2022-09-30 삼성전자주식회사 집적회로 소자 및 그 제조 방법
KR102532202B1 (ko) 2016-01-22 2023-05-12 삼성전자 주식회사 반도체 소자
US10163679B1 (en) * 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization
US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004260151A (ja) * 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) * 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
CN102244004A (zh) * 2010-05-14 2011-11-16 夏普株式会社 半导体器件的制造方法
US8703577B1 (en) * 2012-12-17 2014-04-22 United Microelectronics Corp. Method for fabrication deep trench isolation structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242649A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607A (zh) * 2024-03-27 2024-05-03 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件

Also Published As

Publication number Publication date
JP2024063193A (ja) 2024-05-10
EP3756213B1 (en) 2025-05-21
EP3756213A1 (en) 2020-12-30
JP2021517734A (ja) 2021-07-26
US20210090941A1 (en) 2021-03-25
JP7755114B2 (ja) 2025-10-16
WO2019165107A1 (en) 2019-08-29
WO2019165107A8 (en) 2020-12-03
US20190259651A1 (en) 2019-08-22
EP3756213A4 (en) 2021-04-28
US10879106B2 (en) 2020-12-29

Similar Documents

Publication Publication Date Title
CN112204705A (zh) 具有重叠深沟槽和浅沟槽的装置及制造具有低缺陷密度的类似装置的方法
TWI646629B (zh) 用於積體電路裝置之間隔物啟用之主動隔離
JP5237285B2 (ja) 電子デバイス及びその製造方法
US9520435B2 (en) Image sensor illuminated and connected on its back side
CN107658309A (zh) 一种三维存储器阵列的多级接触及其制造方法
US9889472B2 (en) CMUT device and manufacturing method
US10784152B2 (en) Method of making an interconnection between wafers after wafer level stacking, based on 3D-IC technology
TW201342586A (zh) 在半導體裝置中形成不同深度溝渠之方法
CN111370368B (zh) 一种半导体芯片密封环及其制造方法
EP2933829B1 (en) Method for reducing defects in shallow trench isolation
CN115000113B (zh) 背照式图像传感器及其制作方法
TWI713783B (zh) 製作半導體裝置的方法
CN109994493B (zh) 电子器件图像传感器
JP6308067B2 (ja) 半導体装置の製造方法
US20150295030A1 (en) Insulating trench forming method
CN105845735A (zh) 一种mosfet及其制备方法
CN111384001B (zh) 一种半导体器件
CN111354630B (zh) 半导体结构及其制造方法
JP2005116907A (ja) 半導体装置の製造方法
US20240304688A1 (en) Semiconductor device having contact plug connected to diffusion region
CN103021923A (zh) 半导体的制造方法
US20160240576A1 (en) Method of manufacturing semiconductor device
JPH0497516A (ja) 半導体装置の素子分離用酸化膜形成方法
CN108122822A (zh) 半导体器件的制备方法
JPH01128470A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination