CN113223949B - 屏蔽栅功率器件制造方法及其功率器件 - Google Patents

屏蔽栅功率器件制造方法及其功率器件 Download PDF

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CN113223949B
CN113223949B CN202110467590.9A CN202110467590A CN113223949B CN 113223949 B CN113223949 B CN 113223949B CN 202110467590 A CN202110467590 A CN 202110467590A CN 113223949 B CN113223949 B CN 113223949B
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张蕾
谭艳琼
陈正嵘
丁佳
钱佳成
李志国
吴长明
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Hua Hong Semiconductor Wuxi Co Ltd
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Abstract

本发明公开了一种屏蔽栅功率器件制造方法及其功率器件,包括如下步骤:步骤S1,提供一半导体衬底,在所述半导体衬底上刻蚀形成多个深沟槽,步骤S2、刻蚀所述源多晶硅层,定义原胞区和保护环区刻蚀所述原胞区处的所述源多晶硅层,步骤S3、刻蚀所述氧化层,步骤S4、沉积薄膜层,在所述原胞区和所述保护环区同时沉积二氧化硅薄膜层;步骤S5、沉积栅多晶硅层,步骤S6、涂布光刻胶层,在所述栅多晶硅层上涂布光刻胶,形成所述光刻胶层;步骤S7、栅多晶硅回刻,对所述光刻胶层和所述栅多晶硅层进行回刻;使所述原胞区的所述栅多晶硅层与所述半导体衬底上的所述薄膜层齐平,并使所述保护环区无所述栅多晶硅层残留。

Description

屏蔽栅功率器件制造方法及其功率器件
技术领域
本发明涉及一种半导体集成电路的制造方法,特别是涉及屏蔽栅功率器件制造方法及其功率器件。
背景技术
随着半导体集成电路技术的发展,屏蔽栅功率器件(Shield Gate Trench,SGT),广泛地用作中压功率器件(60v-250v)。然而在制造过程中,尤其是Half UDSGT平台在制造过程中,原胞区的源多晶硅层和氧化层(FOX)经过刻蚀工艺后,由于其特殊的形貌结构和较大的沟槽关键尺寸,导致多晶硅填充后形成较大的凹陷,后续回刻形成的栅多晶硅层继续存在凹陷,如图6,进一步影响后续作业。
发明内容
本发明所要解决的技术问题是,提供一种屏蔽栅功率器件制造方法,避免原胞区的栅多晶硅层产生凹陷,不影响后续作业。
本发明提供一种屏蔽栅功率器件制造方法,包括:
步骤S1,提供一半导体衬底,
在所述半导体衬底上刻蚀形成多个深沟槽,
在所述深沟槽沉积形成氧化层,所述氧化层覆盖所述深沟槽的底壁和侧壁并延伸覆盖所述半导体衬底的顶面,
用多晶硅材料填充所述深沟槽以形成源多晶硅层;
步骤S2、刻蚀所述源多晶硅层,
定义原胞区和保护环区
刻蚀所述原胞区处的所述源多晶硅层,直至所述源多晶硅层的上表面低于所述半导体衬底的顶面至预设阈值a,
刻蚀所述保护环区处的所述源多晶硅层,直至所述源多晶硅层的上表面低于所述半导体衬底的顶面至预设阈值b,其中所述阈值a大于所述阈值b;
步骤S3、刻蚀所述氧化层,
刻蚀所述原胞区处的所述氧化层,形成栅沟槽,
刻蚀所述保护环区的所述氧化层,使所述氧化层的上表面与所述半导体衬底的顶面齐平,并使所述保护环区处的所述源多晶硅层裸露出来;
步骤S4、沉积薄膜层,
在所述原胞区和所述保护环区同时沉积二氧化硅薄膜层;
步骤S5、沉积栅多晶硅层,
利用多晶硅材料沉积填充所述栅沟槽以形成所述栅多晶硅层;
步骤S6、涂布光刻胶层,
在所述栅多晶硅层上涂布光刻胶,形成所述光刻胶层;
步骤S7、栅多晶硅回刻,
对所述光刻胶层和所述栅多晶硅层进行回刻;
使所述原胞区的所述栅多晶硅层与所述半导体衬底上的所述薄膜层齐平,并使所述保护环区无所述栅多晶硅层残留。
优选地,所述步骤S2中,刻蚀所述源多晶硅层的方法为干法刻蚀。
优选地,所述步骤S3中,刻蚀所述氧化层2的方法为湿法刻蚀。
优选地,所述步骤S3中,在所述原胞区处,所述栅沟槽暴露出部分所述半导体衬底的侧壁和部分所述源多晶硅层的侧壁。
优选地,所述步骤S4中,采用TEOS源PECVD生长二氧化硅薄膜。
优先地,所述步骤S5中,所述栅多晶硅层的上表面延伸覆盖所述半导体衬底上的所述薄膜层。
优选地,所述步骤S7中,所述栅多晶硅回刻工艺的选择比为1比1。
本发明还提供一种屏蔽栅功率器件,所述屏蔽栅功率器件由前述任一所述的屏蔽栅功率器件制造方法制备而成。
与现有技术相比,本发明避免回刻形成的栅多晶硅层形成凹陷,使栅多晶硅层平坦化,使后续工艺步骤可以正常进行。
附图说明
图1为具体实施方式的屏蔽栅功率器件制造方法步骤示意图。
图2为具体实施方式中步骤S2、S3的器件结构示意图。
图3为具体实施方式中步骤S4、S5的器件结构示意图。
图4为具体实施方式中步骤S6的器件结构示意图。
图5为具体实施方式中步骤S7的器件结构示意图。
图6为现有技术导致的栅多晶硅层凹陷示意图
具体实施方式
本发明的屏蔽栅功率器件制造方法的具体实施方式包括如下步骤
S1、提供一半导体衬底1,在该半导体衬底1上已形成多个深沟槽,在深沟槽中形成氧化层2,氧化层2覆盖深沟槽的底壁和侧壁并延伸覆盖半导体衬底1的顶面,并利用多晶硅材料填充所述深沟槽以形成源多晶硅层3。该步骤可采用现有技术的方法获得,例如公开文献CN111785641A所公开的方法,因此不再详述。
S2、刻蚀多晶硅层
定义原胞区和保护环区,如图2。
刻蚀原胞区处的源多晶硅层3,直至源多晶硅层3的上表面低于半导体衬底1的顶面至预设阈值a。刻蚀保护环区处的源多晶硅层3,直至源多晶硅层3的上表面低于半导体衬底1的顶面至预设阈值b。其中阈值a大于阈值b。刻蚀源多晶硅层3的方法为干法刻蚀。
S3、刻蚀氧化层
如图2,刻蚀原胞区处的氧化层2,以在原胞区处的半导体衬底1和所述源多晶硅层3之间形成栅沟槽。栅沟槽暴露出部分半导体衬底1的侧壁和部分源多晶硅层3的侧壁。刻蚀氧化层2的方法为湿法刻蚀。
刻蚀保护环区的氧化层2,使氧化层2的上表面与半导体的顶面齐平,并使刻蚀保护环区处的多晶硅层裸露出来。
S4、沉积薄膜层
如图3,在原胞区和保护环区同时沉积二氧化硅薄膜层4。
采用TEOS源PECVD生长二氧化硅薄膜。
PECVD(Plasma Enhanced Chemical Vapor Deposition)是指等离子体增强化学的气相沉积法。TEOS是指四乙氧基硅烷。
S5、沉积栅多晶硅层
如图3,利用多晶硅材料沉积填充栅沟槽以形成栅多晶硅层5,栅多晶硅层5的上表面延伸覆盖半导体衬底1上的薄膜层4。
S6、涂布光刻胶层
如图4,在栅多晶硅层5上涂布光刻胶,形成光刻胶层6。光刻胶具有较佳流动性,可以填充栅多晶硅层5的凹陷,并形成平坦的光刻胶层6。光刻胶层6的厚度与栅多晶硅层5的厚度相当。
涂布光刻胶后可切片确认原胞区与保护环区衔接处无异常。
S7、栅多晶硅回刻
如图5,对光刻胶层6和栅多晶硅层5进行回刻。
调整回刻工艺选择比,光刻胶层刻蚀:栅多晶硅层刻蚀=1:1,使原胞区的栅多晶硅层5与半导体衬底1上的薄膜层4齐平,并使保护环区无栅多晶硅层残留。
此外,本发明还提供一种屏蔽栅功率器件,该屏蔽栅功率器件由前述的屏蔽栅功率器件制造方法制备而成的。
以上通过具体实施方式和实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。

Claims (7)

1.一种屏蔽栅功率器件制造方法,其特征在于,包括:步骤S1,提供一半导体衬底,
在所述半导体衬底上刻蚀形成多个深沟槽,
在所述深沟槽沉积形成氧化层,所述氧化层覆盖所述深沟槽的底壁和侧壁并延伸覆盖所述半导体衬底的顶面,
用多晶硅材料填充所述深沟槽以形成源多晶硅层;步骤S2、刻蚀所述源多晶硅层,定义原胞区和保护环区,
刻蚀所述原胞区处的所述源多晶硅层,直至所述源多晶硅层的上表面低于所述半导体衬底的顶面至预设阈值a,
刻蚀所述保护环区处的所述源多晶硅层,直至所述源多晶硅层的上表面低于所述半导体衬底的顶面至预设阈值b,其中所述阈值a大于所述阈值b;
步骤S3、刻蚀所述氧化层,
刻蚀所述原胞区处的所述氧化层,形成栅沟槽,
刻蚀所述保护环区的所述氧化层,使所述氧化层的上表面与所述半导体衬底的顶面齐平,并使所述保护环区处的所述源多晶硅层裸露出来;
步骤S4、沉积薄膜层,
在所述原胞区和所述保护环区同时沉积二氧化硅薄膜层;步骤S5、沉积栅多晶硅层,
利用多晶硅材料沉积填充所述栅沟槽以形成所述栅多晶硅层;步骤S6、涂布光刻胶层,
在所述栅多晶硅层上涂布光刻胶,形成所述光刻胶层;步骤S7、栅多晶硅回刻,
对所述光刻胶层和所述栅多晶硅层进行回刻;
使所述原胞区的所述栅多晶硅层与所述半导体衬底上的所述薄膜层齐平,并使所述保护环区无所述栅多晶硅层残留;所述栅多晶硅回刻工艺的选择比为1比1。
2.如权利要求1所述的屏蔽栅功率器件制造方法,其特征在于:所述步骤S2中,刻蚀所述源多晶硅层的方法为干法刻蚀。
3.如权利要求1所述的屏蔽栅功率器件制造方法,其特征在于:所述步骤S3中,刻蚀所述氧化层2的方法为湿法刻蚀。
4.如权利要求1所述的屏蔽栅功率器件制造方法,其特征在于:
所述步骤S3中,在所述原胞区处,所述栅沟槽暴露出部分所述半导体衬底的侧壁和部分所述源多晶硅层的侧壁。
5.如权利要求1所述的屏蔽栅功率器件制造方法,其特征在于:所述步骤S4中,采用TEOS源PECVD生长二氧化硅薄膜。
6.如权利要求1所述的屏蔽栅功率器件制造方法,其特征在于:
所述步骤S5中,所述栅多晶硅层的上表面延伸覆盖所述半导体衬底上的所述薄膜层。
7.一种屏蔽栅功率器件,其特征在于:
所述屏蔽栅功率器件由前述任一权利要求所述的屏蔽栅功率器件制造方法制备而成。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108039369A (zh) * 2017-11-30 2018-05-15 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽mosfet及其制造方法
CN112133637A (zh) * 2020-11-30 2020-12-25 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽的半导体器件的制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108039369A (zh) * 2017-11-30 2018-05-15 上海华虹宏力半导体制造有限公司 屏蔽栅沟槽mosfet及其制造方法
CN112133637A (zh) * 2020-11-30 2020-12-25 中芯集成电路制造(绍兴)有限公司 具有屏蔽栅沟槽的半导体器件的制造方法

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