JP2021515986A - マルチパスレーザスクライビングプロセスとプラズマエッチングプロセスを使用したハイブリッドウエハダイシングアプローチ - Google Patents
マルチパスレーザスクライビングプロセスとプラズマエッチングプロセスを使用したハイブリッドウエハダイシングアプローチ Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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Abstract
Description
本出願は、2018年3月12日出願の米国特許出願第15/918,673号の優先権を主張するものであり、この出願の全内容が、本明細書で参照することにより本書に組み込まれる。
Claims (15)
- 複数の集積回路を備える半導体ウエハをダイシングする方法であって、
前記半導体ウエハの上に、前記集積回路を覆い保護する層を備えるマスクを形成することと、
前記集積回路間の前記半導体ウエハの領域を露出させる空隙を有するパターニングされたマスクを提供するために、マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることであって、前記マルチパスレーザスクライビングプロセスは、第1のエッジスクライブパスに沿った第1のパスと、中心スクライブパスに沿った第2のパスと、第2のエッジスクライブパスに沿った第3のパスと、前記第2のエッジスクライブパスに沿った第4のパスと、前記中心スクライブパスに沿った第5のパスと、前記第1のエッジスクライブパスに沿った第6のパスとを含む、マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることと、
前記集積回路を個片化するために、前記パターニングされたマスクの空隙を通して前記半導体ウエハをプラズマエッチングすることと
を含む方法。 - 前記マルチパスレーザスクライビングプロセスは、約10ミクロンのスポットサイズを有するレーザビームを使用することを含む、請求項1に記載の方法。
- 前記第1のエッジスクライブパスの中心と前記中心スクライブパスの中心との間の間隔が約5ミクロンであり、前記中心スクライブパスの中心と前記第2のエッジスクライブパスの中心との間の間隔が約5ミクロンである、請求項2に記載の方法。
- 前記マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることは、前記集積回路間の前記半導体ウエハの前記領域にトレンチを形成することを含み、前記半導体ウエハをプラズマエッチングすることは、対応するトレンチ延長部を形成するために前記トレンチを延長することを含み、前記トレンチは、約20ミクロンの幅、及び5〜6ミクロンの範囲の深さを有する、請求項3に記載の方法。
- 前記第1のエッジスクライブパスの中心と前記中心スクライブパスの中心との間の間隔が約8ミクロンであり、前記中心スクライブパスの中心と前記第2のエッジスクライブパスの中心との間の間隔が約8ミクロンである、請求項2に記載の方法。
- 前記マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることは、前記集積回路間の前記半導体ウエハの前記領域にトレンチを形成することを含み、前記半導体ウエハをプラズマエッチングすることは、対応するトレンチ延長部を形成するために前記トレンチを延長することを含み、前記トレンチは25〜30ミクロンの範囲の幅、及び5ミクロン以下の深さを有する、請求項5に記載の方法。
- 前記マルチパスレーザスクライビングプロセスは、ガウス型レーザビームに基づく、請求項1に記載の方法。
- 前記マルチパスレーザスクライビングプロセスは、平坦な上部を有するライン状レーザビームに基づく、請求項1に記載の方法。
- 複数の集積回路を備える半導体ウエハをダイシングする方法であって、
前記半導体ウエハの上に、前記集積回路を覆い保護する層を備えるマスクを形成することと、
前記集積回路間の前記半導体ウエハの領域を露出させる空隙を有するパターニングされたマスクを提供するために、マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることであって、前記マルチパスレーザスクライビングプロセスは、中心スクライブパスに沿った第1のパスと、第1のエッジスクライブパスに沿った第2のパスと、第2のエッジスクライブパスに沿った第3のパスと、前記第2のエッジスクライブパスに沿った第4のパスと、前記第1のエッジスクライブパスに沿った第5のパスと、前記中心スクライブパスに沿った第6のパスとを含む、マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることと、
前記集積回路を個片化するために、前記パターニングされたマスクの空隙を通して前記半導体ウエハをプラズマエッチングすることと
を含む方法。 - 前記マルチパスレーザスクライビングプロセスは、約10ミクロンのスポットサイズを有するレーザビームを使用することを含む、請求項9に記載の方法。
- 前記第1のエッジスクライブパスの中心と前記中心スクライブパスの中心との間の間隔が約5ミクロンであり、前記中心スクライブパスの中心と前記第2のエッジスクライブパスの中心との間の間隔が約5ミクロンである、請求項10に記載の方法。
- 前記マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることは、前記集積回路間の前記半導体ウエハの前記領域にトレンチを形成することを含み、前記半導体ウエハをプラズマエッチングすることは、対応するトレンチ延長部を形成するために前記トレンチを延長することを含み、前記トレンチは約20ミクロンの幅、及び5〜6ミクロンの範囲の深さを有する、請求項11に記載の方法。
- 前記第1のエッジスクライブパスの中心と前記中心スクライブパスの中心との間の間隔は約8ミクロンであり、前記中心スクライブパスの中心と前記第2のエッジスクライブパスの中心との間の間隔は約8ミクロンである、請求項10に記載の方法。
- 前記マルチパスレーザスクライビングプロセスで前記マスクをパターニングすることは、前記集積回路間の前記半導体ウエハの前記領域にトレンチを形成することを含み、前記半導体ウエハをプラズマエッチングすることは、対応するトレンチ延長部を形成するために前記トレンチを延長することを含み、前記トレンチは25から30ミクロンの範囲の幅、及び5ミクロン以下の深さを有する、請求項13に記載の方法。
- 前記マルチパスレーザスクライビングプロセスは、ガウス型レーザビームに基づく、請求項9に記載の方法。
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US15/918,673 US10535561B2 (en) | 2018-03-12 | 2018-03-12 | Hybrid wafer dicing approach using a multiple pass laser scribing process and plasma etch process |
PCT/US2019/017893 WO2019177737A1 (en) | 2018-03-12 | 2019-02-13 | Hybrid wafer dicing approach using a multiple pass laser scribing process and plasma etch process |
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