JP2021512504A - マルチプルパターンニング処理での原子層堆積を使用するスペーサプロファイル制御 - Google Patents
マルチプルパターンニング処理での原子層堆積を使用するスペーサプロファイル制御 Download PDFInfo
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- JP2021512504A JP2021512504A JP2020561576A JP2020561576A JP2021512504A JP 2021512504 A JP2021512504 A JP 2021512504A JP 2020561576 A JP2020561576 A JP 2020561576A JP 2020561576 A JP2020561576 A JP 2020561576A JP 2021512504 A JP2021512504 A JP 2021512504A
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- oxidation
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- silicon oxide
- plasma
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45536—Use of plasma, radiation or electromagnetic fields
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32422—Arrangement for selecting ions or species in the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
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Abstract
Description
本出願は、事実上全体が参照により本明細書に組み入れられる、2018年1月26日に提出された、「SPACER PROFILE CONTROL USING ATOMIC LAYER DEPOSITION IN A MULTIPLE PATTERNING PROCESS(マルチプルパターンニング処理での原子層堆積を使用するスペーサプロファイル制御)」と題する米国特許出願公開第15/881,506号明細書の優先権の利益を主張する。
以下の記述では、提示する実施形態を十分に理解することができるようにするために、数多くの具体的な詳細について示す。開示する実施形態は、これらの具体的な詳細の一部またはすべてなしに実施されてよい。他の実例では、開示する実施形態を不必要に不明瞭にしないために、周知の処理動作について詳細に記述しなかった。開示する実施形態について具体的実施形態と関連づけて記述するが、その一方で、開示する実施形態に限定することを意図するものではないことを理解されよう。
特徴サイズが縮小し、ピッチがより小さくなり、相補型金属酸化膜半導体(complementary metal−oxide −semiconductor、CMOS)技術がより小さなノードにスケール変更するにつれて、薄く等角な堆積技術は、重要性を増し続ける。原子層堆積(ALD)が等角な薄膜を堆積させるのに最適な膜形成技法であるのは、ALDが、膜形成化学反応自体の前に基板表面の上に吸収されてよい(すなわち、吸収制限層を形成する)1つまたは複数の前駆物質反応物の量により厚さが制限される、材料の単一薄層を堆積させるという事実に起因する。ALDにより形成される各層は薄く、等角であり、得られる膜は、下にある素子構造物および特徴の形状に事実上一致する。
技術の進歩は、半導体素子で、縮小する素子特徴およびより小さなピッチの需要を増大させてきた。さまざまなパターン形成技法および方法を採用して、より小さな素子特徴およびより小さなピッチを達成してきたが、一定の限界に達することが多い。たとえば、高分解能のフォトリソグラフィを使用して、より小さな特徴を印刷して、より小さな限界寸法(critical dimension、CD)を得てよいが、高分解能のフォトリソグラフィは、一定の限界(たとえば、40nm以下)を超える特徴を印刷することができないことがあるので、ピッチはその限界を超えないことがある。
本明細書では、酸化ケイ素スペーサプロファイルを制御するための方法、システム、および装置を提供する。ALDまたはPEALDは、マルチプルパターンニング方式で酸化ケイ素スペーサ堆積のために使用される。ALDは、順次の自己制御的反応を使用して材料の薄層を堆積させる技法である。典型的には、ALDサイクルは、基板に少なくとも1つの反応物を配送し、吸収させ、次いで吸収された反応物を1つまたは複数の反応物と反応させて、部分的な膜の層を形成する動作を含む。CVD技法と異なり、ALD処理は、表面の自己制御的堆積反応を使用して、膜を層ごとに堆積させる。典型的なALDサイクルは、(i)基板表面の上に前駆物質材料を堆積させて、吸収させる照射ステップと、(ii)チャンバから過剰な前駆物質材料をパージして、基板表面上に自己制御的単層を残すステップと、(iii)反応物質を配送して、吸収された前駆物質材料と反応させるステップと、(iv)反応しなかった反応物材料または反応副産物をチャンバからパージするステップとを含んでよい。照射ステップは、活性部位が前駆物質材料により占有されると、追加の前駆物質材料が基板表面上にほとんど、またはまったく吸収されないように、自己制御的手法で前駆物質を吸収してよい。前駆物質材料は、同様に自己制御的手法で、または吸収を制限する手法で、前駆物質材料と反応してよい。パージステップは、チャンバから過剰な前駆物質材料、反応副産物、および/または未反応の反応物材料を除去するために任意選択で遂行されてよく、ALDサイクルを完了させる。ALDを使用して、高アスペクト比の特徴でさえ比較的高い段差被覆を伴う高度に等角な膜を提供してよい。
本明細書では、酸化ケイ素スペーサプロファイルを制御するための方法、システム、および装置を提供する。酸化ケイ素スペーサの堆積中、スペーサの中に固有応力が発生することがある。酸化ケイ素スペーサ内の応力分布は、エッチングおよびコア材料除去の後にプロファイルが正の、負の、または垂直の傾きであるかどうかに対応することがある。ALDサイクルの間、または複数のALDサイクルの間にわたって、1つまたは複数の堆積パラメータを制御することにより応力分布を制御してよい。それに応じてALDサイクルで、該当する堆積パラメータを設定または修正することにより、所望の手法で酸化ケイ素スペーサの最終プロファイルを制御してよい。該当する堆積パラメータを設定または修正するステップは、ALDサイクルで酸化条件を設定または修正するステップを含んでよい。
前述の実施形態について、理解を明確にするためにいくらか詳細に記述してきたが、添付の特許請求の範囲内で一定の変更および修正を実施してよいことは明らかであろう。本実施形態の処理、システム、および装置を実装する代替方法が多くあることに留意されたい。したがって、本実施形態は、例示的であり、制限するものではないと考えるべきであり、実施形態は、本明細書で示す詳細に限定されるべきではない。
Claims (22)
- 方法であって、
プラズマチャンバ内で、パターン形成されたコア材料および前記パターン形成されたコア材料の下にあるターゲット層を含む基板上に原子層堆積(ALD)により第1の厚さの酸化ケイ素スペーサ層を堆積させるステップであって、第1の照射量のケイ素含有前駆物質に前記基板を暴露するステップ、および第1の酸化条件の下で酸化剤のプラズマに前記基板を暴露するステップを含むステップと、
前記プラズマチャンバ内で、前記基板上に前記ALDにより第2の厚さの前記酸化ケイ素スペーサ層を堆積させるステップであって、第2の照射量の前記ケイ素含有前駆物質に前記基板を暴露するステップ、および第2の酸化条件の下で前記酸化物の前記プラズマに前記基板を暴露するステップを含み、前記第1の酸化条件は、前記第2の酸化条件と異なるステップと、
前記プラズマチャンバ内で、前記パターン形成されたコア材料をエッチングして、前記酸化ケイ素スペーサ層から前記ターゲット層用のマスクの役割を果たす複数のスペーサを形成するステップと
を備える方法。 - 請求項1に記載の方法であって、
前記第2の酸化条件は、(1)酸化時間、(2)無線周波数(RF)電力、および(3)基板温度のうちの1つまたは複数だけ前記第1の酸化条件と異なる方法。 - 請求項2に記載の方法であって、
前記酸化時間は、前記第1の酸化条件および前記第2の酸化条件ごとに約0.25秒〜約5秒の間である方法。 - 請求項2に記載の方法であって、
前記RF電力は、前記第1の酸化条件および前記第2の酸化条件ごとに約100ワット〜約10,000ワットの間である方法。 - 請求項2に記載の方法であって、
前記基板温度は、前記第1の酸化条件および前記第2の酸化条件ごとに約0℃〜約100℃の間である方法。 - 請求項1に記載の方法であって、
前記第2の酸化条件は、第2の酸化時間および第2のRF電力を含み、前記第1の酸化条件は、第1の酸化時間および第1のRF電力を含み、前記第2の酸化時間は、前記第1の酸化時間よりも長く、前記第2のRF電力は、前記第1のRF電力よりも大きい方法。 - 請求項1に記載の方法であって、
前記第2の酸化条件は、第2の酸化時間および第2のRF電力を含み、前記第1の酸化条件は、第1の酸化時間および第1のRF電力を含み、前記第2の酸化時間は、前記第1の酸化時間よりも短く、前記第2のRF電力は、前記第1のRF電力よりも小さい方法。 - 請求項1に記載の方法であって、
前記第2の酸化条件は、第2の基板温度を含み、前記第1の酸化条件は、第1の基板温度を含み、第前記2の基板温度は、前記第1の基板温度と異なる方法。 - 請求項8に記載の方法であって、
基板支持物の温度を前記第1の基板温度から前記第2の基板温度へ傾斜させるステップ
をさらに備える方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記第1の厚さの前記酸化ケイ素スペーサ層を堆積させる前記ステップの動作、前記第2の厚さの前記酸化ケイ素スペーサ層を堆積させる前記ステップの動作、および前記パターン形成されたコア材料をエッチングする前記ステップの動作は、前記動作の間に真空破壊を導入することなく前記プラズマチャンバ内で行われる方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記プラズマチャンバ内の圧力は、約1mTorr(133.322mPa)〜約100mTorr(13332.2mPa)の間である方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記パターン形成されたコア材料をエッチングする前記ステップの前に前記酸化ケイ素スペーサ層の一部分をエッチングするステップ
をさらに備える方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記第1の厚さの前記酸化ケイ素スペーサ層を堆積させる前記ステップは、(i)前記第1の照射量の前記ケイ素含有前駆物質に前記基板を暴露する前記ステップ、および(ii)前記第1の酸化条件の下で前記酸化剤の前記プラズマに前記基板を暴露する前記ステップからなるX回のサイクルを適用するステップを含み、前記第2の厚さの前記酸化ケイ素スペーサ層を堆積させる前記ステップは、(iii)前記第2の照射量の前記ケイ素含有前駆物質に前記基板を暴露する前記ステップ、および(iv)前記第2の酸化条件の下で前記酸化剤の前記プラズマに前記基板を暴露する前記ステップからなるY回のサイクルを適用するステップを含み、前記Xおよび前記Yは、互いに異なる整数値である方法。 - 請求項13に記載の方法であって、
前記第1の酸化条件は、第1の酸化時間を含み、前記第2の酸化条件は、第2の酸化時間を含み、前記第1の酸化時間は、前記X回のサイクルにわたり徐々に変化し、前記第2の酸化時間は、前記Y回のサイクルにわたり徐々に変化する方法。 - 請求項13に記載の方法であって、
前記第1の酸化条件は、第1のRF電力を含み、前記第2の酸化条件は、第2のRF電力を含み、前記第1のRF電力は、前記X回のサイクルにわたり徐々に変化し、前記第2のRF電力は、前記Y回のサイクルにわたり徐々に変化する方法。 - 請求項13に記載の方法であって、
前記第1の酸化条件の下で前記酸化物の前記プラズマに前記基板を暴露する前記ステップは、前記第1の照射量の前記ケイ素含有前駆物質を変換して、前記第1の厚さの前記酸化ケイ素スペーサ層を形成するステップを含み、前記第2の酸化条件の下で前記酸化物の前記プラズマに前記基板を暴露する前記ステップは、前記第2の照射量の前記ケイ素含有前駆物質を変換して、前記第2の厚さの前記酸化ケイ素スペーサ層を形成するステップを含む方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記酸化物は酸素ガスを含む方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記パターン形成されたコア材料は、スピンオン炭素、ダイヤモンド状炭素、およびギャップ充填灰化可能バードマスクからなるグループから選択される材料を含む方法。 - 請求項1〜9のいずれか一項に記載の方法であって、
前記複数のスペーサの各々の上側部分は、前記第1の酸化条件および前記第2の酸化条件に少なくとも一部は依存する傾きを有する方法。 - 複数の酸化ケイ素スペーサの傾きを制御するための装置であって、
プラズマチャンバと、
前記プラズマチャンバにRF電力を配送するように構成された、前記プラズマチャンバに連結されたRF電源と、
前記プラズマチャンバ内で、パターン形成されたコア材料および前記パターン形成されたコア材料の下にあるターゲット層を含む基板を支持するための基板支持物と、
コントローラであって、
(i)前記プラズマチャンバ内で、前記基板上に原子層堆積(ALD)により第1の厚さの酸化ケイ素スペーサ層を堆積させる命令であって、前記ALDにより前記第1の厚さの前記酸化ケイ素スペーサ層を堆積させるステップは、第1の照射量のケイ素含有前駆物質に前記基板を暴露するステップ、および第1の酸化条件の下で酸化物のプラズマに前記基板を暴露するステップを含む命令、
(ii)前記プラズマチャンバ内で、前記第1の厚さの前記酸化ケイ素スペーサ層上に前記ALDにより第2の厚さの前記酸化ケイ素スペーサ層を堆積させる命令であって、前記ALDにより前記第2の厚さの前記酸化ケイ素スペーサ層を堆積させるステップは、第2の照射量の前記ケイ素含有前駆物質に前記基板を暴露するステップ、および第2の酸化条件の下で前記酸化物の前記プラズマに前記基板を暴露するステップを含み、前記第2の酸化条件は、前記第1の酸化条件と異なる命令、ならびに
(iii)前記プラズマチャンバ内で、前記パターン形成されたコア材料をエッチングして、前記酸化ケイ素スペーサ層から前記ターゲット層用のマスクの役割を果たす複数のスペーサを形成する命令
を遂行するように構成されたコントローラと
を備える装置。 - 請求項20に記載の装置であって、
前記第2の酸化条件は、(1)酸化時間、(2)無線周波数(RF)電力、および(3)基板温度のうちの1つまたは複数だけ前記第1の酸化条件と異なる装置。 - 請求項20に記載の装置であって、
前記複数のスペーサの各々の上側部分は、前記第1の酸化条件および前記第2の酸化条件に少なくとも一部は依存する傾きを有する装置。
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