JP2021506132A - メモリデバイス、半導体デバイスを製造する方法及びデバイス構造 - Google Patents
メモリデバイス、半導体デバイスを製造する方法及びデバイス構造 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 81
- 238000003860 storage Methods 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000010884 ion-beam technique Methods 0.000 claims description 32
- 239000012212 insulator Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 12
- 238000000605 extraction Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 description 10
- 238000012545 processing Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 241000894007 species Species 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (15)
- 第1のレベルに少なくとも部分的に配置されたアクティブデバイス領域と、
前記第1のレベルより上の第2のレベルに少なくとも部分的に配置された蓄積キャパシタと、
コンタクトビアと、
を備え、
前記第1のレベルおよび前記第2のレベルは基板平面に平行であり、
前記コンタクトビアは、前記蓄積キャパシタと前記アクティブデバイス領域との間に延在し、前記基板平面に対する垂直線に対して非ゼロの傾斜角を成す、
メモリデバイス。 - 前記蓄積キャパシタは、平面図の観点から、前記基板平面内で前記アクティブデバイス領域と不完全なオーバーラップを形成する、請求項1に記載のメモリデバイス。
- 前記蓄積キャパシタは、平面図の観点から見て、前記基板平面内で前記アクティブデバイス領域とオーバーラップを形成しない、請求項1に記載のメモリデバイス。
- 前記コンタクトビアの底部全体が前記アクティブデバイス領域とオーバーラップを形成する、請求項1に記載のメモリデバイス。
- 前記コンタクトビアの上部全体が前記蓄積キャパシタとオーバーラップする、請求項1に記載のメモリデバイス。
- 前記非ゼロの傾斜角は15度未満である、請求項1に記載のメモリデバイス。
- 前記アクティブデバイス領域および前記蓄積キャパシタはダイナミックランダムアクセス(DRAM)セルの一部を形成し、該DRAMセルはDRAMデバイスの一部を形成し、該DRAMデバイスは6F2構造を含む、請求項1に記載のメモリデバイス。
- 前記コンタクトビアは第3のレベルに少なくとも部分的に配置され、前記第3のレベルは前記第1のレベルと前記第2のレベルの間に延在している、請求項1に記載のメモリデバイス。
- 前記アクティブデバイス領域および前記蓄積キャパシタはダイナミックランダムアクセス(DRAM)セルの一部を形成し、前記コンタクトビアは前記DRAMセルのディジットラインを含むディジットラインレベルを通過して延在する、請求項1に記載のメモリデバイス。
- 半導体デバイスを製造する方法であって、
前記半導体デバイスの第1のレベルにアクティブデバイス領域を形成するステップと、
前記アクティブデバイス領域に接触するコンタクトビアであって、基板平面に対する垂直線に対して非ゼロの傾斜角を成す、コンタクトビアを形成するステップと、
前記半導体デバイスの前記第1のレベルより上の第2のレベルに蓄積キャパシタを少なくとも部分的に形成するステップで、該蓄積キャパシタがコンタクトビアに接触する、ステップと、
を含む、方法。 - 前記蓄積キャパシタは、平面図の観点から、前記基板平面内で前記アクティブデバイス領域とのオーバーラップを形成しない、請求項10に記載の方法。
- 前記アクティブデバイス領域および前記蓄積キャパシタは、ダイナミックランダムアクセスメモリ(DRAM)セルの一部を形成し、前記コンタクトビアは、ディジット線を含む前記DRAMセルのディジット線レベルを、前記ディジット線に接触しないで、通過して延在する、請求項10に記載の方法。
- 前記コンタクトビアを形成するステップは、
前記アクティブデバイス領域を含む基板をプラズマチャンバに隣接するプロセスチャンバ内に提供するステップと、
イオンビームを前記プラズマチャンバから抽出アパーチャを介してプロセスチャンバに抽出するステップで、前記イオンビームは、前記基板平面に対して非ゼロの入射角を成す軌道を形成するステップと、
前記基板がイオンビームに曝されるときに前記基板が前記抽出開口に対して走査される少なくとも1回の走査を実行するステップと、
を含む、請求項10に記載の方法。 - 前記コンタクトビアを形成する前に、前記アクティブデバイス領域上に絶縁体を形成するステップと、
前記絶縁体上にマスクを形成し、該マスクは複数の開口部を画定し、該複数の開口部は第1の開口部を規定し、前記イオンビームは、反応性イオンビームエッチングプロセスを使用して前記第1の開口部を通して前記絶縁体をエッチングすることにより前記コンタクトビアを形成するステップと、
を含む、請求項13に記載の方法。 - 第1のデバイスレベルに配置された第1のデバイスと、
前記第1のデバイスレベルより上の第2のデバイスレベルに配置された第2のデバイスと、
前記第1のデバイスと前記第2のデバイスとの間に延在し、前記基板平面に対する垂直線に対して非ゼロの傾斜角を成すコンタクトビアと、
を備える、デバイス構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US15/839,260 | 2017-12-12 | ||
US15/839,260 US10692872B2 (en) | 2017-12-12 | 2017-12-12 | Device structure for forming semiconductor device having angled contacts |
PCT/US2018/062555 WO2019118166A1 (en) | 2017-12-12 | 2018-11-27 | Device structure for forming semiconductor device having angled contacts |
Publications (2)
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JP2021506132A true JP2021506132A (ja) | 2021-02-18 |
JP7214732B2 JP7214732B2 (ja) | 2023-01-30 |
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US (2) | US10692872B2 (ja) |
JP (1) | JP7214732B2 (ja) |
KR (1) | KR102388129B1 (ja) |
CN (1) | CN111788684B (ja) |
TW (1) | TWI761635B (ja) |
WO (1) | WO2019118166A1 (ja) |
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US11956978B2 (en) * | 2020-09-03 | 2024-04-09 | Applied Materials, Inc. | Techniques and device structure based upon directional seeding and selective deposition |
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US20190181144A1 (en) | 2019-06-13 |
KR102388129B1 (ko) | 2022-04-19 |
US10886279B2 (en) | 2021-01-05 |
CN111788684A (zh) | 2020-10-16 |
JP7214732B2 (ja) | 2023-01-30 |
US10692872B2 (en) | 2020-06-23 |
TW201928962A (zh) | 2019-07-16 |
CN111788684B (zh) | 2023-10-27 |
US20200279852A1 (en) | 2020-09-03 |
WO2019118166A1 (en) | 2019-06-20 |
TWI761635B (zh) | 2022-04-21 |
KR20200088913A (ko) | 2020-07-23 |
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