JP2020528215A - 自己整合コンタクトを形成する方法およびデバイス構造体 - Google Patents
自己整合コンタクトを形成する方法およびデバイス構造体 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 125000006850 spacer group Chemical group 0.000 claims abstract description 154
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 239000002131 composite material Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 239000002253 acid Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- -1 SiN) Chemical class 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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Abstract
Description
Claims (21)
- 自己整合コンタクトを形成する方法であって、
基板の上に多数のゲート側壁スペーサを形成するステップと、
誘電体の中に前記ゲート側壁スペーサを埋め込むステップと、
ゲートが形成される前記ゲート側壁スペーサ同士の間の領域から前記誘電体を選択的に除去することによりゲート・トレンチを形成するステップと、
前記ゲート・トレンチ内に前記ゲートを形成するステップと、
前記自己整合コンタクトが形成される前記ゲート側壁スペーサ同士の間の領域から前記誘電体を選択的に除去することによりコンタクト・トレンチを形成するステップと、
前記コンタクト・トレンチ内に前記自己整合コンタクトを形成するステップと
を含む、方法。 - 前記基板の上にスペーサ材料層を形成するステップと、
前記基板の上に前記ゲート側壁スペーサを形成するために前記スペーサ材料層をパターニングするステップと
をさらに含む、請求項1に記載の方法。 - 側壁イメージ転写(SIT)が、前記基板の上に前記ゲート側壁スペーサを形成するため前記スペーサ材料層をパターニングするのに使用される、請求項2に記載の方法。
- 前記スペーサ材料層の上にマンドレルを形成するステップと、
前記マンドレルの対向する側面の上に複合スペーサを形成するステップであって、前記複合スペーサがi)前記マンドレルの対向する側面上の第1のスペーサとii)前記マンドレルとは反対の前記第1のスペーサの側面上の第2のスペーサとを含む、複合スペーサを形成するステップと
をさらに含む、請求項3に記載の方法。 - 前記複合スペーサに対して選択的に前記マンドレルを除去するステップと、
前記スペーサ材料層をパターニングするのに前記複合スペーサを使用するステップと、
前記第2のスペーサを選択的に除去するステップと、
前記スペーサ材料層をパターニングするのに前記第1のスペーサを使用するステップと
をさらに含む、請求項4に記載の方法。 - ゲートが形成される前記ゲート側壁スペーサ同士の間の前記領域から前記誘電体を選択的に除去する前に、前記自己整合コンタクトが形成される前記ゲート側壁スペーサ同士の間の前記領域を覆うマスクを形成するステップ
をさらに含む、請求項1に記載の方法。 - 前記ゲートが、置換金属ゲートを含み、前記ゲート・トレンチ内に前記ゲートを形成する前記ステップが、前記ゲート・トレンチの中へとゲート誘電体を堆積するステップと、
前記ゲート誘電体の上に仕事関数設定金属を堆積するステップと、
前記仕事関数設定金属の上に充填金属を堆積するステップと
を含む、請求項1に記載の方法。 - 前記ゲート誘電体が、酸化ハフニウムおよび酸化ランタンからなる群から選択されるhigh−k材料を含む、請求項7に記載の方法。
- 前記仕事関数設定金属が、窒化チタン、窒化タンタル、およびタングステンからなる群から選択される、請求項7に記載の方法。
- 前記充填金属がアルミニウムを含む、請求項7に記載の方法。
- 前記自己整合コンタクトがトレンチ・シリサイドを含む、請求項1に記載の方法。
- 前記トレンチ・シリサイドがニッケル・シリサイドを含む、請求項11に記載の方法。
- 前記ゲートのうちの少なくとも1つを選択的に除去するステップ
をさらに含む、請求項1に記載の方法。 - 前記ゲートのうちで1つおきに選択的に除去するステップ
をさらに含む、請求項13に記載の方法。 - 選択的に除去される前記ゲートを除いてすべてをマスキングするステップ
をさらに含む、請求項13に記載の方法。 - 前記ゲートのうちの少なくとも1つが選択的に除去されている前記ゲート・トレンチを絶縁体で埋めるステップ
をさらに含む、請求項13に記載の方法。 - 前記絶縁体が窒化物材料を含む、請求項16に記載の方法。
- 基板上の多数のゲート側壁スペーサと、
ゲートおよび前記ゲート側壁スペーサ同士の間の領域内の前記ゲートに自己整合したコンタクトであって、前記ゲートの各々が金属ゲートを含み、前記コンタクトの各々がトレンチ・シリサイドを含む、ゲートおよびコンタクトと
を備える、デバイス構造体。 - 前記ゲート側壁スペーサ同士の間の前記領域のうちの少なくとも1つが、絶縁体を含む、請求項18に記載のデバイス構造体。
- 前記金属ゲートが、
ゲート誘電体と、
前記ゲート誘電体上の仕事関数設定金属と、
前記仕事関数設定金属上の充填金属と
を含む、請求項18に記載のデバイス構造体。 - 前記ゲート側壁スペーサが、窒化ケイ素、炭窒化ケイ素、ホウ炭窒化ケイ素、酸炭窒化ケイ素、およびこれらの組み合わせからなる群から選択される材料を含む、請求項18に記載のデバイス構造体。
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US15/655,547 | 2017-07-20 | ||
PCT/IB2018/055243 WO2019016672A1 (en) | 2017-07-20 | 2018-07-16 | FORMATION OF SELF-ALIGNED CONTACTS |
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WO2019016672A1 (en) | 2019-01-24 |
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DE112018002948T5 (de) | 2020-04-02 |
GB2579487A (en) | 2020-06-24 |
US10186599B1 (en) | 2019-01-22 |
CN110892523B (zh) | 2024-01-05 |
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