JP2020513693A5 - - Google Patents

Download PDF

Info

Publication number
JP2020513693A5
JP2020513693A5 JP2019529602A JP2019529602A JP2020513693A5 JP 2020513693 A5 JP2020513693 A5 JP 2020513693A5 JP 2019529602 A JP2019529602 A JP 2019529602A JP 2019529602 A JP2019529602 A JP 2019529602A JP 2020513693 A5 JP2020513693 A5 JP 2020513693A5
Authority
JP
Japan
Prior art keywords
single crystal
layer
handle substrate
crystal semiconductor
semiconductor handle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019529602A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020513693A (ja
JP6801105B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2017/064248 external-priority patent/WO2018106535A1/en
Publication of JP2020513693A publication Critical patent/JP2020513693A/ja
Publication of JP2020513693A5 publication Critical patent/JP2020513693A5/ja
Priority to JP2020194948A priority Critical patent/JP6972282B2/ja
Application granted granted Critical
Publication of JP6801105B2 publication Critical patent/JP6801105B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2019529602A 2016-12-05 2017-12-01 高抵抗シリコンオンインシュレータ構造及びその製造方法 Active JP6801105B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020194948A JP6972282B2 (ja) 2016-12-05 2020-11-25 高抵抗シリコンオンインシュレータ構造及びその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662429922P 2016-12-05 2016-12-05
US62/429,922 2016-12-05
PCT/US2017/064248 WO2018106535A1 (en) 2016-12-05 2017-12-01 High resistivity silicon-on-insulator structure and method of manufacture thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2020194948A Division JP6972282B2 (ja) 2016-12-05 2020-11-25 高抵抗シリコンオンインシュレータ構造及びその製造方法

Publications (3)

Publication Number Publication Date
JP2020513693A JP2020513693A (ja) 2020-05-14
JP2020513693A5 true JP2020513693A5 (https=) 2020-11-19
JP6801105B2 JP6801105B2 (ja) 2020-12-16

Family

ID=60997530

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2019529602A Active JP6801105B2 (ja) 2016-12-05 2017-12-01 高抵抗シリコンオンインシュレータ構造及びその製造方法
JP2020194948A Active JP6972282B2 (ja) 2016-12-05 2020-11-25 高抵抗シリコンオンインシュレータ構造及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2020194948A Active JP6972282B2 (ja) 2016-12-05 2020-11-25 高抵抗シリコンオンインシュレータ構造及びその製造方法

Country Status (8)

Country Link
US (2) US10468295B2 (https=)
EP (2) EP4009361B1 (https=)
JP (2) JP6801105B2 (https=)
KR (2) KR102587815B1 (https=)
CN (2) CN110352484B (https=)
SG (1) SG10201913059PA (https=)
TW (2) TWI758133B (https=)
WO (1) WO2018106535A1 (https=)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6344271B2 (ja) * 2015-03-06 2018-06-20 信越半導体株式会社 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
US10622247B2 (en) * 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
FR3066858B1 (fr) * 2017-05-23 2019-06-21 Soitec Procede pour minimiser une distorsion d'un signal dans un circuit radiofrequence
CN107611144B (zh) * 2017-09-19 2019-10-11 武汉华星光电技术有限公司 一种层间绝缘层的制备方法、层间绝缘层及液晶显示面板
US10943813B2 (en) 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
FR3098642B1 (fr) * 2019-07-12 2021-06-11 Soitec Silicon On Insulator procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges
US11171015B2 (en) * 2019-09-11 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer
FR3104322B1 (fr) * 2019-12-05 2023-02-24 Soitec Silicon On Insulator Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf
US12176202B2 (en) * 2020-10-08 2024-12-24 Okmetic Oy Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure
FR3116151A1 (fr) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile
TWM633935U (zh) * 2021-04-07 2022-11-11 日商信越化學工業股份有限公司 積層體的製造系統、積層體以及半導體裝置
JP7692638B2 (ja) * 2021-04-16 2025-06-16 テクタス コーポレイション 窒化ガリウム発光ダイオード用のシリコン二重ウェーハ基板
US11869869B2 (en) * 2021-04-22 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Heterogeneous dielectric bonding scheme
US12533766B2 (en) 2021-06-11 2026-01-27 Taiwan Semiconductor Manufacturing Co., Ltd. Simplified carrier removable by reduced number of CMP processes
CN113437016A (zh) 2021-06-25 2021-09-24 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
EP4287239A1 (en) * 2022-06-02 2023-12-06 Imec VZW A low loss semiconductor substrate
FR3137493B1 (fr) * 2022-06-29 2024-10-04 Soitec Silicon On Insulator Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
FR3137490B1 (fr) * 2022-07-04 2024-05-31 Soitec Silicon On Insulator Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
WO2024115410A1 (fr) 2022-11-29 2024-06-06 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes.
JP2026511208A (ja) 2022-11-29 2026-04-10 ソイテック 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法
EP4627621A1 (fr) 2022-11-29 2025-10-08 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
FR3146020B1 (fr) 2023-02-20 2025-07-18 Soitec Silicon On Insulator Support comprenant une couche de piégeage de charges, substrat composite comprenant un tel support et procédé de fabrication associés
FR3163488A1 (fr) * 2024-06-12 2025-12-19 Soitec Substrat photonique et utilisation d’un tel substrat dans un dispositif de modulation optique
WO2025257265A1 (fr) * 2024-06-12 2025-12-18 Soitec Procédé de fabrication d'un substrat photonique
CN121240528A (zh) * 2025-12-01 2025-12-30 上海超硅半导体股份有限公司 绝缘体上半导体及其制备方法

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501060A (en) 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
US4755865A (en) 1986-01-21 1988-07-05 Motorola Inc. Means for stabilizing polycrystalline semiconductor layers
JPH06105691B2 (ja) 1988-09-29 1994-12-21 株式会社富士電機総合研究所 炭素添加非晶質シリコン薄膜の製造方法
JP2617798B2 (ja) 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
US6043138A (en) 1996-09-16 2000-03-28 Advanced Micro Devices, Inc. Multi-step polysilicon deposition process for boron penetration inhibition
US5783469A (en) 1996-12-10 1998-07-21 Advanced Micro Devices, Inc. Method for making nitrogenated gate structure for improved transistor performance
US6068928A (en) 1998-02-25 2000-05-30 Siemens Aktiengesellschaft Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
JP4313874B2 (ja) 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
US6346459B1 (en) 1999-02-05 2002-02-12 Silicon Wafer Technologies, Inc. Process for lift off and transfer of semiconductor devices onto an alien substrate
US20020090758A1 (en) 2000-09-19 2002-07-11 Silicon Genesis Corporation Method and resulting device for manufacturing for double gated transistors
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7057234B2 (en) 2002-12-06 2006-06-06 Cornell Research Foundation, Inc. Scalable nano-transistor and memory using back-side trapping
US20070032040A1 (en) 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
US6992025B2 (en) 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
US7279400B2 (en) 2004-08-05 2007-10-09 Sharp Laboratories Of America, Inc. Method of fabricating single-layer and multi-layer single crystalline silicon and silicon devices on plastic using sacrificial glass
US7312487B2 (en) 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7476594B2 (en) 2005-03-30 2009-01-13 Cree, Inc. Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
FR2890489B1 (fr) 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
JP4445524B2 (ja) 2007-06-26 2010-04-07 株式会社東芝 半導体記憶装置の製造方法
JP2009016692A (ja) 2007-07-06 2009-01-22 Toshiba Corp 半導体記憶装置の製造方法と半導体記憶装置
US7915706B1 (en) 2007-07-09 2011-03-29 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate using passivation
US7879699B2 (en) 2007-09-28 2011-02-01 Infineon Technologies Ag Wafer and a method for manufacturing a wafer
US8128749B2 (en) 2007-10-04 2012-03-06 International Business Machines Corporation Fabrication of SOI with gettering layer
US7868419B1 (en) 2007-10-18 2011-01-11 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate based radio frequency devices
US20090236689A1 (en) 2008-03-24 2009-09-24 Freescale Semiconductor, Inc. Integrated passive device and method with low cost substrate
FR2933234B1 (fr) 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2010258083A (ja) 2009-04-22 2010-11-11 Panasonic Corp Soiウェーハ、その製造方法および半導体装置の製造方法
US8766413B2 (en) 2009-11-02 2014-07-01 Fuji Electric Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP5644096B2 (ja) 2009-11-30 2014-12-24 ソニー株式会社 接合基板の製造方法及び固体撮像装置の製造方法
WO2011087878A2 (en) 2010-01-18 2011-07-21 Applied Materials, Inc. Manufacture of thin film solar cells with high conversion efficiency
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8859393B2 (en) 2010-06-30 2014-10-14 Sunedison Semiconductor Limited Methods for in-situ passivation of silicon-on-insulator wafers
US9433753B2 (en) 2010-07-16 2016-09-06 Barbara R. Holliday Medical tubing stabilizer
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
JP5627649B2 (ja) 2010-09-07 2014-11-19 株式会社東芝 窒化物半導体結晶層の製造方法
JP5117588B2 (ja) 2010-09-07 2013-01-16 株式会社東芝 窒化物半導体結晶層の製造方法
FR2967812B1 (fr) 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech Dispositif electronique pour applications radiofrequence ou de puissance et procede de fabrication d'un tel dispositif
US9287353B2 (en) 2010-11-30 2016-03-15 Kyocera Corporation Composite substrate and method of manufacturing the same
US8481405B2 (en) 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
US8536021B2 (en) 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
EP3734645B1 (en) 2010-12-24 2025-09-10 Qualcomm Incorporated Trap rich layer for semiconductor devices
US8796116B2 (en) 2011-01-31 2014-08-05 Sunedison Semiconductor Limited Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
KR101870476B1 (ko) 2011-03-16 2018-06-22 썬에디슨, 인크. 핸들 웨이퍼에 고 비저항 영역을 갖는 실리콘-온-인슐레이터 구조체 및 그러한 구조체를 제조하는 방법
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
US9496255B2 (en) 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8741739B2 (en) 2012-01-03 2014-06-03 International Business Machines Corporation High resistivity silicon-on-insulator substrate and method of forming
US20130193445A1 (en) 2012-01-26 2013-08-01 International Business Machines Corporation Soi structures including a buried boron nitride dielectric
TWI604595B (zh) * 2012-07-01 2017-11-01 賽普拉斯半導體公司 非揮發性電荷捕獲記憶體元件以及其製造方法
US8921209B2 (en) * 2012-09-12 2014-12-30 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
US9202711B2 (en) 2013-03-14 2015-12-01 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness
JP6232124B2 (ja) * 2013-03-15 2017-11-15 バタフライ ネットワーク,インコーポレイテッド 相補型金属酸化膜半導体(cmos)超音波振動子およびその形成方法
US8951896B2 (en) 2013-06-28 2015-02-10 International Business Machines Corporation High linearity SOI wafer for low-distortion circuit applications
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
WO2015112308A1 (en) * 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
JP6100200B2 (ja) * 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP2015228432A (ja) * 2014-06-02 2015-12-17 信越半導体株式会社 Soiウェーハの製造方法及び貼り合わせsoiウェーハ
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
US9853133B2 (en) 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
EP3221884B1 (en) * 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
WO2016081363A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A system-on-chip on a semiconductor-on-insulator wafer and a method of manufacturing
EP3221885B1 (en) * 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
CN104498895B (zh) * 2014-12-23 2017-02-22 国家纳米科学中心 一种超薄氮氧化硅膜材料及其制备方法和用途
JP2016143820A (ja) * 2015-02-04 2016-08-08 信越半導体株式会社 貼り合わせ半導体ウェーハ及びその製造方法
US10283402B2 (en) * 2015-03-03 2019-05-07 Globalwafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
JP6443394B2 (ja) * 2016-06-06 2018-12-26 信越半導体株式会社 貼り合わせsoiウェーハの製造方法

Similar Documents

Publication Publication Date Title
JP2020513693A5 (https=)
JP2017526190A5 (https=)
JP2017538288A5 (https=)
EP4170705A3 (en) High resistivity semiconductor-on-insulator wafer and a method of manufacturing
JP2017005282A5 (https=)
JP2014072533A5 (https=)
JP2014131025A5 (https=)
Fukui et al. Surface relaxation of topological insulators: Influence on the electronic structure
JP2018002544A5 (https=)
JP2011139054A5 (ja) 半導体装置
JP2013110393A5 (https=)
JP2014143339A5 (https=)
JP2015135962A5 (https=)
JP2014220488A5 (https=)
JP2014179596A5 (https=)
JP2013080918A5 (https=)
JP2009158936A5 (https=)
FR2987618B1 (fr) Vitrage anticondensation
JP2012049513A5 (ja) 半導体装置
JP2013021312A5 (ja) 半導体装置
JP2016197708A5 (ja) 半導体装置
EP4660349A3 (en) Perovskite material layer processing
JP2010533371A5 (https=)
RU2015138108A (ru) Слои для минимизации влияния дефектов в электрохромных устройствах
JP2012151453A5 (ja) 半導体装置