JP2020512689A - 薄膜トランジスタ及びその製造方法、表示パネル - Google Patents
薄膜トランジスタ及びその製造方法、表示パネル Download PDFInfo
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- JP2020512689A JP2020512689A JP2019549372A JP2019549372A JP2020512689A JP 2020512689 A JP2020512689 A JP 2020512689A JP 2019549372 A JP2019549372 A JP 2019549372A JP 2019549372 A JP2019549372 A JP 2019549372A JP 2020512689 A JP2020512689 A JP 2020512689A
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- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000003963 antioxidant agent Substances 0.000 claims abstract description 54
- 230000003078 antioxidant effect Effects 0.000 claims abstract description 54
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 52
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- -1 oxygen ions Chemical class 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 77
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 18
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 claims description 5
- 230000008025 crystallization Effects 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 3
- 230000000149 penetrating effect Effects 0.000 claims 3
- 239000001301 oxygen Substances 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 169
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
- G02F1/13685—Top gates
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
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- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L29/0843—Source or drain regions of field-effect devices
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Abstract
Description
基板基材に所定パターンのアルミニウム層及び酸化防止層を順次形成し、前記基板基材には、基板基材に平行な方向に沿って順次隣接して配置されている第1領域、第2領域及び第3領域が区画されており、アルミニウム層が第1領域、第2領域及び第3領域に形成され、前記酸化防止層が第2領域に形成される工程と、
酸化防止層上にアルミニウム層を被覆する非晶質酸化物半導体層を形成する工程と、
非晶質酸化物半導体層をアニール処理し、アニール処理中に、第1領域及び第3領域においてアルミニウム層が酸化反応してAl2O3を生成し、非晶質酸化物半導体層が第1領域及び第3領域において結晶化反応してソースコンタクト領域及びドレインコンタクト領域を形成し、第2領域において酸化防止層に遮蔽されてチャネル領域を形成する工程と、
アニール処理された非晶質酸化物半導体層上にゲート絶縁層を形成する工程と、
ゲート絶縁層上に、ソースコンタクト領域とドレインコンタクト領域との間に位置しかつチャネル領域の上方に対応して位置するゲートパターンを形成する工程と、
ゲートパターン上に誘電体分離層を形成する工程と、
誘電体分離層上に、ソースコンタクト領域に接続されたソースパターンと、ドレインコンタクト領域に接続されたドレインパターンとを形成する工程とを備える。
基板基材に位置し且つ所定パターンを有するAl2O3層及びアルミニウム層であって、前記基板基材には、前記基板基材に平行な方向に沿って順次隣接して配置されている第1領域、第2領域及び第3領域が区画されており、前記Al2O3層が第1領域及び第3領域に形成され、前記アルミニウム層が第2領域に形成されるAl2O3層及びアルミニウム層と、
アルミニウム層上に位置し、基板基材における正射影が第2領域と重なる酸化防止層と、
酸化防止層上に位置し、基板基材における正射影が第1領域と重なるソースコンタクト領域と、基板基材における正射影が第3領域と重なるドレインコンタクト領域と、基板基材における正射影が第2領域と重なるチャネル領域と、を備える半導体層と、
半導体層上に位置するゲート絶縁層と、
ゲート絶縁層上に位置し、ソースコンタクト領域とドレインコンタクト領域との間に位置しかつチャネル領域の上方に対応して位置するゲートパターンと、
ゲートパターン上に位置する誘電体分離層と、
誘電体分離層上に位置するソースパターン及びドレインパターンであって、前記ソースパターンがソースコンタクト領域に接続され、前記ドレインパターンがドレインコンタクト領域に接続されたソースパターン及びドレインパターンと、を備える。
基板基材20上に、基板基材20を被覆するアルミニウム層21及び酸化防止層22を順次形成する。該基板基材20は、ガラス基板基材、プラスチック基板基材、フレキシブル基板基材等の透光性基板基材を含むが、これに限定されない。本実施例では、PVD(Physical Vapor Deposition,物理蒸着法)法を用いて、基板基材20上に、全面アルミニウム層21と、全面酸化防止層22とを順に形成することができ、該酸化防止層22は、Mo(モリブデン)層であってもよい。
図2及び図3に示すように、本実施例では、PVD法により、基板基材20の全面を被覆する非晶質酸化物半導体層24を形成することができる。該非晶質酸化物半導体層の材質はIGZOを含むが、これに限定されない。そして、本実施例では、フォトレジストの塗布、露光、エッチングにより、第1領域201、第2領域202及び第3領域203に位置する非晶質酸化物半導体層24のみを保留することができる。
本実施例では、半導体層25上に、基板基材20の全面を被覆する構造であるゲート絶縁層(Gate Insulation Layer,GI)26をCVD(Chemical Vapor Deposition,化学蒸着)法により形成することができる。前記ゲート絶縁層26の材質はケイ素酸化物(SiOx)であってもよく、もちろん、ゲート絶縁層26は半導体層25上に順次形成された酸化ケイ素化合物層及び窒化ケイ素化合物層、例えば、SiO2(二酸化ケイ素)とSi3N4(窒化ケイ素)を含んでもよく、これによりゲート絶縁層26の耐摩耗性と絶縁性能をさらに向上させることができる。
本実施例では、フォトレジストの塗布、露光、現像、エッチング等のパターニング工程を用いて、所定パターンを有するゲートパターン271を形成することができる。本実施例のTFTは、ゲートパターン271が半導体層25の上方に位置することを考慮してトップゲート設計を有すると考えられ、露光工程において、背面照射のイエロープロセスを用いてゲート絶縁層26上にゲートパターン271を形成することができ、前記イエロープロセスがアニーリング処理されたアルミニウム層(即ち、第2領域202のアルミニウム層21)を遮光層とし、前記遮光層の酸化防止層22とは反対側から光を照射し、従来のフォトマスクを遮光層として用いることを省略して、製造工程をより簡略化することができる。
本実施例は、CVD法を用いてゲートパターン271上に誘電体分離層28を形成することができる。該誘電体分離層(Interlayer Dielectric Layer,IDL、誘電体層又は層間絶縁層とも呼ばれる)28は、ゲート絶縁層26の全面の構造を被覆する。
本発明の実施例は表示パネルをさらに提供し、図4に示すように、該液晶表示パネル40が第1基板41及び第2基板42を含み、前記薄膜トランジスタが第1基板41又は第2基板42上に形成されてもよい。したがって、該表示パネル40も上記の有益な効果を有する。なお、該表示パネル40は、液晶表示パネルであってもよいし、AMOLED(Active−matrix organic light emitting diode、アクティブマトリックス有機発光ダイオード)等のタイプの表示パネルであってもよい。
Claims (16)
- 薄膜トランジスタの製造方法であって、
基板基材に所定パターンのアルミニウム層及び酸化防止層を順次形成する工程であって、前記基板基材には、基板基材に平行な方向に沿って順次隣接して配置されている第1領域、第2領域及び第3領域が区画されており、前記アルミニウム層が前記第1領域、第2領域及び第3領域に形成され、前記酸化防止層が前記第2領域に形成される工程と、
前記酸化防止層上に前記アルミニウム層を被覆する非晶質酸化物半導体層を形成する工程と、
前記非晶質酸化物半導体層をアニール処理し、前記アニール処理中に、前記第1領域及び第3領域においてアルミニウム層が酸化反応してAl2O3(酸化アルミニウム)を生成し、非晶質酸化物半導体層が前記第1領域及び第3領域において結晶化反応してソースコンタクト領域及びドレインコンタクト領域を形成し、前記第2領域において酸化防止層に遮蔽されてチャネル領域を形成する工程と、
アニール処理された非晶質酸化物半導体層上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層上に、前記ソースコンタクト領域と前記ドレインコンタクト領域との間に位置しかつ前記チャネル領域の上方に対応して位置するゲートパターンを形成する工程と、
前記ゲートパターン上に誘電体分離層を形成する工程と、
前記誘電体分離層上に、前記ソースコンタクト領域に接続されたソースパターンと、前記ドレインコンタクト領域に接続されたドレインパターンとを形成する工程と、を含む、薄膜トランジスタの製造方法。 - 基板基材上に所定パターンのアルミニウム層及び酸化防止層を順次形成する工程は、
基板基材上に、前記基板基材を被覆するアルミニウム層及び酸化防止層を順次形成することと、
前記酸化防止層上にフォトレジスト層を形成することと、
露光後のフォトレジスト層が前記第1領域、第2領域及び第3領域に形成され、第2領域における前記フォトレジストの厚みが、前記第1領域及び第3領域のいずれかにおける前記フォトレジストの厚みよりも大きくなるように、Half−tone(ハーフトーン)マスクを用いて前記フォトレジストを露光することと、
前記露光されたフォトレジスト層で覆われていないアルミニウム層及び酸化防止層を除去するように、1回目のエッチング工程を行うことと、
前記第1領域及び前記第3領域に位置するフォトレジスト層を除去して、第2領域のフォトレジスト層を保留するように、前記露光されたフォトレジスト層をアッシング処理することと、
第2領域のフォトレジスト層で遮蔽されずに、前記第1領域及び第3領域に位置する酸化防止層を除去するように、2回目のエッチング工程を行うことと、
前記第2領域に位置するフォトレジストを除去することと、を含む、請求項1に記載の方法。 - 前記1回目のエッチング工程がウェットエッチングを用い、前記2回目のエッチング工程がドライエッチングを用いる、請求項2に記載の方法。
- 基板基材上に所定パターンのアルミニウム層及び酸化防止層を順次形成する工程は、
基板基材上に、前記基板基材を被覆するアルミニウム層及び酸化防止層を順次形成することと、
前記酸化防止層上に、前記基板基材における正射影が前記第2領域と重なるフォトレジスト層を形成することと、
前記フォトレジスト層で遮蔽されていない酸化防止層を除去するように、前記フォトレジスト層で遮蔽されていない酸化防止層をエッチングすることと、
前記フォトレジスト層を除去することと、を含む、請求項1に記載の方法。 - ドライエッチングを用いて前記フォトレジスト層で遮蔽されていない酸化防止層をエッチングする、請求項4に記載の方法。
- 前記酸化防止層がモリブデン層を含む、請求項1に記載の方法。
- 背面照射のイエロープロセスを用いて、ゲート絶縁層上にゲートパターンを形成し、前記イエロープロセスが前記第2領域のアルミニウム層を遮光層とし、前記遮光層の酸化防止層とは反対側から光を照射する、請求項1に記載の方法。
- 前記誘電体分離層上に、ソースパターン及びドレインパターンを形成する工程は、
前記ゲート絶縁層及び誘電体分離層を貫通して、前記ソースコンタクト領域及びドレインコンタクト領域をそれぞれ露出する2つのコンタクトホールを形成することと、
前記2つのコンタクトホールにそれぞれ形成されたソースパターン及びドレインパターンを前記誘電体分離層上に形成することと、を含む、請求項1に記載の方法。 - 薄膜トランジスタであって、
基板基材に形成され且つ所定パターンを有するAl2O3層(酸化アルミニウム)及びアルミニウム層であって、前記基板基材には、前記基板基材に平行な方向に沿って順次隣接して配置されている第1領域、第2領域及び第3領域が区画されており、前記Al2O3層が第1領域及び第3領域に形成され、前記アルミニウム層が第2領域に形成されるAl2O3層及びアルミニウム層と、
前記アルミニウム層上に位置し、前記基板基材における正射影が前記第2領域と重なる酸化防止層と、
前記酸化防止層上に位置し、基板基材における正射影が前記第1領域と重なるソースコンタクト領域と、基板基材における正射影が前記第3領域と重なるドレインコンタクト領域と、基板基材における正射影が前記第2領域と重なるチャネル領域と、を含む半導体層と、
前記半導体層上に位置するゲート絶縁層と、
前記ゲート絶縁層上に位置し、前記ソースコンタクト領域と前記ドレインコンタクト領域との間に位置しかつ前記チャネル領域の上方に対応して位置するゲートパターンと、
前記ゲートパターン上に位置する誘電体分離層と、
前記誘電体分離層上に位置するソースパターン及びドレインパターンであって、前記ソースパターンが前記ソースコンタクト領域に接続され、前記ドレインパターンが前記ドレインコンタクト領域に接続されたソースパターン及びドレインパターンと、を含む、薄膜トランジスタ。 - 前記酸化防止層がモリブデン層を含む、請求項9に記載の薄膜トランジスタ。
- 前記ゲート絶縁層は、前記半導体層上に順次形成された酸化ケイ素化合物層及び窒化ケイ素化合物層を含む、請求項9に記載の薄膜トランジスタ。
- 前記薄膜トランジスタは、前記ゲート絶縁層及び誘電体分離層を貫通して、前記ソースコンタクト領域及びドレインコンタクト領域をそれぞれ露出する2つのコンタクトホールをさらに含み、前記ソースパターン及びドレインパターンが2つのコンタクトホールにそれぞれ形成される、請求項9に記載の薄膜トランジスタ。
- 薄膜トランジスタを含む表示パネルであって、前記薄膜トランジスタは、
基板基材に形成され且つ所定パターンを有するAl2O3層(酸化アルミニウム)及びアルミニウム層であって、前記基板基材には、前記基板基材に平行な方向に沿って順次隣接して配置されている第1領域、第2領域及び第3領域が区画されており、前記Al2O3層が第1領域及び第3領域に形成され、前記アルミニウム層が第2領域に形成されるAl2O3層及びアルミニウム層と、
前記アルミニウム層上に位置し、前記基板基材における正射影が前記第2領域と重なる酸化防止層と、
前記酸化防止層上に位置し、基板基材における正射影が前記第1領域と重なるソースコンタクト領域と、基板基材における正射影が前記第3領域と重なるドレインコンタクト領域と、基板基材における正射影が前記第2領域と重なるチャネル領域と、を含む半導体層と、
前記半導体層上に位置するゲート絶縁層と、
前記ゲート絶縁層上に位置し、前記ソースコンタクト領域と前記ドレインコンタクト領域との間に位置しかつ前記チャネル領域の上方に対応して位置するゲートパターンと、
前記ゲートパターン上に位置する誘電体分離層と、
前記誘電体分離層上に位置するソースパターン及びドレインパターンであって、前記ソースパターンが前記ソースコンタクト領域に接続され、前記ドレインパターンが前記ドレインコンタクト領域に接続されたソースパターン及びドレインパターンと、を含む、表示パネル。 - 前記酸化防止層がモリブデン層を含む、請求項13に記載の表示パネル。
- 前記ゲート絶縁層は、前記半導体層上に順次形成された酸化ケイ素化合物層及び窒化ケイ素化合物層を含む、請求項13に記載の表示パネル。
- 前記薄膜トランジスタは、前記ゲート絶縁層及び誘電体分離層を貫通して、前記ソースコンタクト領域及びドレインコンタクト領域をそれぞれ露出する2つのコンタクトホールをさらに含み、前記ソースパターン及びドレインパターンが2つのコンタクトホールにそれぞれ形成される、請求項13に記載の表示パネル。
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CN201710156787.4A CN106952827A (zh) | 2017-03-16 | 2017-03-16 | 薄膜晶体管及其制造方法、显示面板 |
PCT/CN2017/079907 WO2018166018A1 (zh) | 2017-03-16 | 2017-04-10 | 薄膜晶体管及其制造方法、显示面板 |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011139045A (ja) * | 2009-12-04 | 2011-07-14 | Semiconductor Energy Lab Co Ltd | 紫外線センサを有する半導体装置及びその作製方法 |
US20120001167A1 (en) * | 2010-07-05 | 2012-01-05 | Sony Corporation | Thin film transistor and display device |
JP2012049513A (ja) * | 2010-07-26 | 2012-03-08 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
US20130134415A1 (en) * | 2011-11-30 | 2013-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2013175710A (ja) * | 2012-01-23 | 2013-09-05 | Semiconductor Energy Lab Co Ltd | 半導体装置、及び半導体装置の作製方法 |
JP2016028449A (ja) * | 2010-06-16 | 2016-02-25 | 株式会社半導体エネルギー研究所 | 電界効果トランジスタ |
WO2016181256A1 (ja) * | 2015-05-12 | 2016-11-17 | 株式会社半導体エネルギー研究所 | 半導体装置、電子部品および電子機器 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3067949B2 (ja) * | 1994-06-15 | 2000-07-24 | シャープ株式会社 | 電子装置および液晶表示装置 |
KR101496148B1 (ko) * | 2008-05-15 | 2015-02-27 | 삼성전자주식회사 | 반도체소자 및 그 제조방법 |
KR101476817B1 (ko) * | 2009-07-03 | 2014-12-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 트랜지스터를 갖는 표시 장치 및 그 제작 방법 |
JP5708910B2 (ja) * | 2010-03-30 | 2015-04-30 | ソニー株式会社 | 薄膜トランジスタおよびその製造方法、並びに表示装置 |
KR20110125105A (ko) * | 2010-05-12 | 2011-11-18 | 엘지디스플레이 주식회사 | 산화물 박막 트랜지스터 및 그 제조방법 |
CN103219391B (zh) * | 2013-04-07 | 2016-03-02 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法、阵列基板和显示装置 |
CN103715094B (zh) * | 2013-12-27 | 2017-02-01 | 京东方科技集团股份有限公司 | 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 |
KR102188690B1 (ko) * | 2014-01-20 | 2020-12-09 | 삼성디스플레이 주식회사 | 박막트랜지스터, 그의 제조방법 및 박막트랜지스터를 구비하는 평판 표시장치 |
CN103972110B (zh) * | 2014-04-22 | 2016-02-24 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制备方法、阵列基板、显示装置 |
TWI555150B (zh) * | 2014-05-27 | 2016-10-21 | 財團法人工業技術研究院 | 電子元件及其製法 |
CN106206743B (zh) * | 2015-05-04 | 2020-04-28 | 清华大学 | 薄膜晶体管及其制备方法、薄膜晶体管面板以及显示装置 |
CN105938800A (zh) * | 2016-07-01 | 2016-09-14 | 深圳市华星光电技术有限公司 | 薄膜晶体管的制造方法及阵列基板的制造方法 |
-
2017
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- 2017-04-10 WO PCT/CN2017/079907 patent/WO2018166018A1/zh active Application Filing
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- 2017-04-10 EP EP17900358.7A patent/EP3598479A4/en not_active Withdrawn
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Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011139045A (ja) * | 2009-12-04 | 2011-07-14 | Semiconductor Energy Lab Co Ltd | 紫外線センサを有する半導体装置及びその作製方法 |
JP2016028449A (ja) * | 2010-06-16 | 2016-02-25 | 株式会社半導体エネルギー研究所 | 電界効果トランジスタ |
US20120001167A1 (en) * | 2010-07-05 | 2012-01-05 | Sony Corporation | Thin film transistor and display device |
CN102315277A (zh) * | 2010-07-05 | 2012-01-11 | 索尼公司 | 薄膜晶体管和显示装置 |
JP2012015436A (ja) * | 2010-07-05 | 2012-01-19 | Sony Corp | 薄膜トランジスタおよび表示装置 |
US20130309822A1 (en) * | 2010-07-26 | 2013-11-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2012049513A (ja) * | 2010-07-26 | 2012-03-08 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
KR20120082800A (ko) * | 2010-07-26 | 2012-07-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제작 방법 |
US20130134415A1 (en) * | 2011-11-30 | 2013-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2013138195A (ja) * | 2011-11-30 | 2013-07-11 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法 |
KR20130061070A (ko) * | 2011-11-30 | 2013-06-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
JP2013175710A (ja) * | 2012-01-23 | 2013-09-05 | Semiconductor Energy Lab Co Ltd | 半導体装置、及び半導体装置の作製方法 |
WO2016181256A1 (ja) * | 2015-05-12 | 2016-11-17 | 株式会社半導体エネルギー研究所 | 半導体装置、電子部品および電子機器 |
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CN106952827A (zh) | 2017-07-14 |
JP6829775B2 (ja) | 2021-02-10 |
EP3598479A1 (en) | 2020-01-22 |
WO2018166018A1 (zh) | 2018-09-20 |
KR102205307B1 (ko) | 2021-01-21 |
EP3598479A4 (en) | 2020-11-25 |
KR20190124788A (ko) | 2019-11-05 |
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