JP2019101062A - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- JP2019101062A JP2019101062A JP2017228227A JP2017228227A JP2019101062A JP 2019101062 A JP2019101062 A JP 2019101062A JP 2017228227 A JP2017228227 A JP 2017228227A JP 2017228227 A JP2017228227 A JP 2017228227A JP 2019101062 A JP2019101062 A JP 2019101062A
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Abstract
Description
本実施形態に係る表示装置について、図1乃至図6を参照して説明する。
図1は、本実施形態に係る表示装置100の構成を示す平面図である。表示装置100は、基材101、表示領域102、周辺領域110を含む。基材101は可撓性を有する。表示領域102は基材101上に設けられる。また、表示領域102は、複数の画素103を含む。複数の画素103は、マトリクス状に配置されている。
本実施形態では、図6に示す領域140の構成とは一部異なる領域140Aの構成について図7を参照して説明する。
本実施形態では、図6に示す領域140の構成とは一部異なる領域140Bの構成について図8を参照して説明する。
本実施形態では、第1実施形態に示す表示装置100とは一部異なる構成を有する表示装置100Aについて、図9及び図10を参照して説明する。なお、図1に示す表示装置100と同じ構成については説明を省略する。
本実施形態では、第1実施形態に示す表示装置100とは一部異なる構成を有する表示装置100Bについて、図11乃至図15を参照して説明する。なお、図1に示す表示装置100と同じ構成については説明を省略する。
本実施形態では、第5実施形態に示す画素とは一部異なる画素について、図16及び図17を参照して説明する。
期間T0では、あるフレーム期間での処理が開始されるまでの間、発光素子OLEDは前フレームの発光状態を継続している。
期間T1では、ゲート発光制御走査線BGの電位がLowレベル(以下、Lレベル)、リセット制御走査線RGの電位がHighレベル(以下、Hレベル)、補正制御走査線CGの電位がHレベルとなる。これにより、発光制御トランジスタBCTがオフとなり、補正トランジスタCCTがオンとなり、リセットトランジスタRSTがオンとなる。当該行の各画素において、高電位側電源PVDDからの電流が発光制御トランジスタBCTによって遮断される。また、発光素子OLEDの発光が停止する共に、画素103内に残留していた電荷がリセットトランジスタRSTを通じて引き抜かれる。これにより、駆動トランジスタDRTのソースがリセット電位Vrstに固定される。リセット電位Vrstは、低電位側電源PVSSに対して、発光素子OLEDの発行開始電圧よりも低い電位に設定されている。
期間T2では、初期化制御走査線IGの電位がHレベルとなり、初期化トランジスタISTがオンする。当該行の各画素において、初期化トランジスタISTを介してDRTのゲートが初期化電位Viniに固定される。初期化電位Viniは、リセット電位Vrstに対して駆動トランジスタDRTのしきい値よりも大きい電位に設定されている。つまり、この操作によって、駆動トランジスタDRTはオンとなる。ただし、発光制御トランジスタBCTがオフしているので、駆動トランジスタDRTにはまだ電流は流れない。
期間T3では、ゲート発光制御走査線BGの電位がHレベル、リセット制御走査線RGの電位がLレベルとなる。これにより、発光制御トランジスタBCTがオンし、リセットトランジスタRSTがオフする。駆動トランジスタDRTは前動作によってオン状態であるから、発光制御トランジスタBCT、高電位側電源PVDDから補正トランジスタCCTを通じて駆動トランジスタDRTに電流が供給される。この段階では、発光素子OLEDの陽極・陰極間の電圧は発光開始電圧を上回っていないので、電流が流れない。従って、高電位側電源PVDDから供給された電流によって、駆動トランジスタDRTのソースが充電され、その電位が上昇する。このとき、駆動トランジスタDRTのゲート電位は初期化電位Viniとなっている。よって、駆動トランジスタDRTのソースの電位が(Vini−Vth)となった段階で駆動トランジスタDRTがオフし、電位の上昇が停止する。駆動トランジスタDRTのしきい値電圧Vthは、画素によってばらつきがあるため、電位の上昇が停止したときの駆動トランジスタDRTのソースの電位は画素によって異なる。つまり、この動作によって、各画素で駆動トランジスタDRTのしきい値電圧Vthに相当する電圧が取得される。このとき、発光素子OLEDの陽極・陰極間には、{(Vini−Vth)−PVSS}の電圧が印加されているが、この電圧は依然発光開始電圧を上回っていないので、発光素子OLEDには電流が流れない。
期間T3及び期間T4では、補正制御走査線CGの電位がLレベル、初期化制御走査線IGの電位がLレベル、書込制御走査線SGの電位がHレベルとなる。これにより、補正トランジスタCCTがオフし、初期化トランジスタISTがオフし、書込トランジスタSSTがオンする。当該行の各画素において、映像信号線Vsigの電位が駆動トランジスタDRTのゲートに入力される。駆動トランジスタDRTのゲート電位は初期化電位Viniから映像信号Vsigの電位に変化する。一方、駆動トランジスタDRTのソース電位は依然(Vini−Vth)であり、結果、駆動トランジスタDRTのゲート、ソース間電圧は、{Vsig−(Vini−Vth)}となり、画素間のしきい値のばらつきが反映されたものとなる。
期間T6では、補正制御走査線CGの電位がHレベル、書込制御走査線SGの電位がLレベルとなる。これにより、補正トランジスタCCTがオンし、書込トランジスタSSTがオフする。高電位側電源PVDDから発光制御トランジスタBCT及び補正トランジスタCCTを通じて駆動トランジスタDRTに電流が供給される。駆動トランジスタDRTは前段階までに設定されたゲート・ソース間電圧に応じた電流を発光素子OLEDに流し、発光素子OLEDがその電流に応じた輝度で発光する。このときの発光素子OLEDの陽極・陰極間電圧は、その電流に応じた電圧となるため、陽極側の電位が上昇するが、容量Csによって駆動トランジスタDRTのゲート・ソース間電圧が保持される。そのため、陽極側の電位上昇に伴って、容量Csのカップリングによって駆動トランジスタDRTのゲート電位も上昇する。実際には、駆動トランジスタDRTのゲートに対しては、容量Csのみならず付加容量Cadや、その他の寄生容量が付いている。よって、陽極側の電位の上昇よりも、駆動トランジスタDRTのゲート電位の上昇はわずかに小さくなるが、この値は既知であるから、最終的な駆動トランジスタDRTのゲート・ソース間電圧において所望の電流値となるように、映像信号線Vsigの電位を決定すれば良い。
Claims (12)
- 可撓性を有する基材と、
前記基材上の複数の画素を含む表示領域と、
前記基材上で前記表示領域の外側の周辺領域と、
前記周辺領域に配置された第1方向に延びる第1配線と、
前記第1配線上の第1絶縁層と、
前記第1絶縁層上の前記第1方向と交差する第2方向に延びる第2配線と、を有し、
前記第1配線は、第1屈曲部を有し、
前記第2配線は、第2屈曲部を有し、
前記第1配線と前記第2配線とが交差する領域において、前記第1屈曲部は前記第2配線と重畳し、前記第2屈曲部は前記第1配線と重畳する、表示装置。 - 前記第1屈曲部は少なくとも一つの第1屈曲角部を含み、
前記第2屈曲部は少なくとも一つの第2屈曲角部を含み、
前記第1配線は、前記第2屈曲角部と重畳し、
前記第2配線は、前記第1屈曲角部と重畳する、請求項1に記載の表示装置。 - 前記第1屈曲部の角部及び前記第2屈曲部の角部は、それぞれ丸みを帯びている、請求項2に記載の表示装置。
- 前記第1屈曲部の角部及び前記第2屈曲部の角部は、それぞれ面取りされている、請求項2に記載の表示装置。
- 前記周辺領域は、ドライバICをさらに有し、
前記ドライバICは、前記複数の画素と、前記第2配線を介して電気的に接続される、請求項1に記載の表示装置。 - 前記基材は前記表示領域と前記ドライバICとの間に折り曲げ領域を含み、
前記第1配線及び前記第2配線は前記折り曲げ領域と交差する、請求項5に記載の表示装置。 - 前記第1配線の幅は、前記第2配線の幅よりも大きい、請求項1に記載の表示装置。
- 可撓性を有する基材と、
前記基材上の複数の画素を含む表示領域と、
前記基材上で前記表示領域の外側の周辺領域と、
前記表示領域で第1方向に延びる第1配線と、
前記第1配線上の第1絶縁層と、
前記第1絶縁層上で、前記第1方向と交差する第2方向に延びる第2配線と、を有し、
前記第1配線は、第1屈曲部を有し、
前記第2配線は、第2屈曲部を有し、
前記第1配線と前記第2配線とが交差する領域において、前記第1屈曲部は前記第2配線と重畳し、前記第2屈曲部は前記第1配線と重畳する、表示装置。 - 前記第1屈曲部は少なくとも一つの第1屈曲角部 を含み、
前記第2屈曲部は少なくとも一つの第2屈曲角部を含み、
前記第1配線は、前記第2屈曲角部と重畳し、
前記第2配線は、前記第1屈曲角部と重畳する、請求項8に記載の表示装置。 - 前記第1屈曲角部及び前記第2屈曲角部は、それぞれ丸みを帯びている、請求項9に記載の表示装置。
- 前記第1屈曲角部及び前記第2屈曲角部は、それぞれ面取りされている、請求項9に記載の表示装置。
- 前記周辺領域は、ドライバICをさらに有し、
前記ドライバICは、前記複数の画素と、前記第2配線を介して電気的に接続される、請求項8に記載の表示装置。
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US11592873B2 (en) * | 2020-02-14 | 2023-02-28 | Apple Inc. | Display stack topologies for under-display optical transceivers |
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