JP2018503250A - パワー電界効果トランジスタ(fet)、プリドライバ、コントローラ、及び感知レジスタの統合 - Google Patents
パワー電界効果トランジスタ(fet)、プリドライバ、コントローラ、及び感知レジスタの統合 Download PDFInfo
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Abstract
Description
Claims (20)
- マルチチップパッケージであって、
少なくとも2つのローサイド(LS)電界効果トランジスタ(FET)、
少なくとも2つのハイサイド(HS)FET、及び、
前記少なくとも2つのHS FET又は前記少なくとも2つのLS FETを含むダイ、
を含む、マルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージであって、
前記ダイが、前記少なくとも2つのHS FETを含む第1のダイであり、
前記マルチチップパッケージがさらに、
前記少なくとも2つのLS FETのうちの第1のLS FETを含む第2のダイ、及び、
前記少なくとも2つのLS FETのうちの第2のLS FETを含む第3のダイ、
を含む、マルチチップパッケージ。 - 請求項2に記載のマルチチップパッケージであって、さらに、
コントローラ回路又はドライバ回路の少なくとも一方を含む第4のダイ、
を含む、マルチチップパッケージ。 - 請求項3に記載のマルチチップパッケージであって、さらに、
前記第1のLS FETのソース電極に結合される第1のレジスタ、及び、
前記第2のLS FETのソース電極に結合される第2のレジスタ、
を含む、マルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージであって、
前記ダイが、前記少なくとも2つのHS FETを含む第1のダイであり、
前記マルチチップパッケージが、さらに、
前記2つのLS FETの少なくとも1つを含む第2のダイ、
を含む、マルチチップパッケージ。 - 請求項5に記載のマルチチップパッケージであって、さらに、
熱パッドと、
コントローラ回路又はドライバ回路の少なくとも一方を含む第3のダイと、
を含み、
前記第2のダイ及び前記第3のダイが、前記熱パッド上に配置される、
マルチチップパッケージ。 - 請求項6に記載のマルチチップパッケージであって、前記第2のダイが前記LS FETのうちの少なくとも2つを含む、マルチチップパッケージ。
- 請求項6に記載のマルチチップパッケージであって、前記少なくとも2つのHS FETがドレイン基板HS FETであり、前記少なくとも2つのLS FETがソース基板LS FETである、マルチチップパッケージ。
- 請求項1に記載のマルチチップパッケージであって、前記ダイが前記少なくとも2つのHS FETを含む第1のダイであり、前記少なくとも2つのHS FETがドレイン基板HS FETである、マルチチップパッケージ。
- 請求項1に記載のマルチチップパッケージであって、
前記ダイが、前記少なくとも2つのLS FETを含む第1のダイであり、
前記マルチチップパッケージが、さらに、
前記少なくとも2つのHS FETのうちの第1のHS FETを含む第2のダイ、及び、
前記少なくとも2つのHS FETのうちの第2のHS FETを含む第3のダイ、
を含み、
前記第2及び第3のダイが、前記第1のダイの頂部上に垂直にスタックされる、
マルチチップパッケージ。 - 請求項10に記載のマルチチップパッケージであって、さらに、
前記第1のダイと前記第2のダイとの間に位置決めされる第1のクリップであって、前記少なくとも2つのLS FETのうちの前記第1のLS FETのドレイン電極と、前記第1のHS FETのソース電極とに結合される、前記第1のクリップ、及び、
前記第1のダイと前記第3のダイとの間に位置決めされる第2のクリップであって、前記少なくとも2つのLS FETのうちの前記第2のLS FETのドレイン電極と、前記第2のHS FETのソース電極とに結合される、前記第2のクリップ、
を含む、マルチチップパッケージ。 - 請求項10に記載のマルチチップパッケージであって、さらに、
コントローラ回路又はドライバ回路の少なくとも一方を含む第4のダイ、
を含む、マルチチップパッケージ。 - 請求項10に記載のマルチチップパッケージであって、さらに、
前記第1のHS FETのドレイン電極に結合される第1のレジスタ、及び、
前記第2のHS FETのドレイン電極に結合される第2のレジスタ、
を含む、マルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージであって、
前記ダイが、前記少なくとも2つのLS FETを含む第1のダイであり、
前記マルチチップパッケージが、さらに、前記少なくとも2つのHS FETを含む第2のダイを含み、前記第2のダイが、前記第1のダイの頂部上に垂直にスタックされる、
マルチチップパッケージ。 - 請求項14に記載のマルチチップパッケージであって、さらに、
コントローラ回路又はドライバ回路の少なくとも一方を含む第3のダイ、
を含む、マルチチップパッケージ。 - 請求項14に記載のマルチチップパッケージであって、さらに、
前記第1及び第2のHS FETのドレイン電極に結合されるレジスタ、
を含む、マルチチップパッケージ。 - 請求項1に記載のマルチチップパッケージであって、
前記ダイが、前記少なくとも2つのLS FETを含む第1のダイであり、
前記マルチチップパッケージが、さらに、
熱パッド、
前記少なくとも2つのHS FETの少なくとも1つを含む第2のダイであって、前記第1のダイの頂部上に垂直にスタックされる、前記第2のダイ、及び、
コントローラ回路又はドライバ回路の少なくとも一方を含む第3のダイ、
を含み、
前記第1のダイ及び前記第3のダイが、前記熱パッド上に配置される、
マルチチップパッケージ。 - 請求項17に記載のマルチチップパッケージであって、前記第2のダイが前記少なくとも2つのHS FETを含む、マルチチップパッケージ。
- マルチチップパッケージであって、
少なくとも2つのローサイド(LS)電界効果トランジスタ(FET)、
少なくとも2つのハイサイド(HS)FET、
前記少なくとも2つのHS FET又は前記少なくとも2つのLS FETを含む第1のダイ、及び、
コントローラ回路又はドライバ回路の少なくとも一方を含む第2のダイ、
を含む、マルチチップパッケージ。 - マルチチップパッケージであって、
少なくとも2つのローサイド(LS)電界効果トランジスタ(FET)、
少なくとも2つのハイサイド(HS)FET、
前記少なくとも2つのHS FET又は前記少なくとも2つのLS FETを含む第1のダイ、
コントローラ回路又はドライバ回路の少なくとも一方を含む第2のダイ、
前記少なくとも2つのHS FET又は前記少なくとも2つのLS FETの第1の1つに結合される第1のレジスタ、及び
前記少なくとも2つのHS FET又は前記少なくとも2つのLS FETの第2の1つに結合される第2のレジスタ、
を含む、マルチチップパッケージ。
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US201462090197P | 2014-12-10 | 2014-12-10 | |
US62/090,197 | 2014-12-10 | ||
PCT/US2015/065091 WO2016094718A1 (en) | 2014-12-10 | 2015-12-10 | Power field-effect transistor (fet), pre-driver, controller, and sense resistor integration |
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JP2018503250A5 JP2018503250A5 (ja) | 2019-01-24 |
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EP (1) | EP3257336A4 (ja) |
JP (1) | JP2018503250A (ja) |
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- 2015-12-10 CN CN201580066697.5A patent/CN107006123A/zh active Pending
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US9870984B2 (en) | 2018-01-16 |
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