JP2018067143A - 電流源 - Google Patents
電流源 Download PDFInfo
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- JP2018067143A JP2018067143A JP2016205209A JP2016205209A JP2018067143A JP 2018067143 A JP2018067143 A JP 2018067143A JP 2016205209 A JP2016205209 A JP 2016205209A JP 2016205209 A JP2016205209 A JP 2016205209A JP 2018067143 A JP2018067143 A JP 2018067143A
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- 230000005669 field effect Effects 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 238000010586 diagram Methods 0.000 description 23
- 239000012212 insulator Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 6
- 238000012790 confirmation Methods 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
図1に示すように、本実施形態による電流源に備えられる不揮発性記憶素子Mは、半導体基板に形成されたPウェル領域10と、Pウェル領域10上に形成されたフローティングゲート領域FGと、フローティングゲート領域FG上に形成されたコントロールゲート領域CGとを備えている。また、不揮発性記憶素子Mは、フローティングゲート領域FGの下方の両側の一方に形成されたドレイン領域Dと、フローティングゲート領域FGの下方の両側の他方に形成されたソース領域Sとを備えている。ドレイン領域Dおよびソース領域Sは、Pウェル領域10に形成されている。不揮発性記憶素子Mは、素子分離領域41,42によって、同一の半導体基板に形成された他の素子と素子分離されている。
スイッチSW2:接続状態(ショート状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図13では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:低電圧供給端子Vss側
スイッチSW2:開放状態(オープン状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図15では低電圧Vss側)
本発明の第2実施形態による電流源回路について図16から図20を用いて説明する。本実施形態における不揮発性記憶素子は、図1に示す不揮発性記憶素子Mと同一の構造を有する不揮発性記憶素子Mwと、図16に示す不揮発性記憶素子Mrとを一組とし、不揮発性記憶素子Mwおよび不揮発性記憶素子Mrのそれぞれのフローティングゲート領域同士が接続され、不揮発性記憶素子Mwおよび不揮発性記憶素子Mrのそれぞれのコントロールゲート領域同士が接続された構成を有している。
スイッチSW2:接続状態(ショート状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図18では低電圧Vss側)
スイッチSW2:開放状態(オープン状態)
スイッチSW3:開放状態(オープン状態)
スイッチSW4:接続状態(ショート状態)
スイッチSW5:低電圧供給端子Vss側
スイッチSW2:開放状態(オープン状態)
スイッチSW3:接続状態(ショート状態)
スイッチSW4:開放状態(オープン状態)
スイッチSW5:任意(図20では低電圧Vss側)
2 負荷
4 電流計
10 ウェル領域
11,13 N型領域
12,14 N+領域
20,70 絶縁体
21,71 電荷保持領域
22,72 ゲート絶縁膜
23、73 側壁酸化膜
24、74 上部絶縁膜
25,32 サイドウォール
41,42 素子分離領域
51,52,53 コンタクトプラグ
61 保護膜
211 電荷注入口
221 トンネル絶縁膜
A1 第一領域
A2 第二領域
B バックゲート
CG コントロールゲート領域
D ドレイン領域
FG フローティングゲート領域
G ゲート領域
M,Mr,Mw 不揮発性記憶素子
S ソース領域
Claims (8)
- コントロールゲート領域およびソース領域を有し電界効果型トランジスタとして動作する不揮発性記憶素子を備え、
前記コントロールゲート領域と前記ソース領域との間にバイアスを印加した状態で電流を出力する
電流源。 - 前記バイアスは、0Vである
請求項1に記載の電流源。 - 前記バイアスは、前記電流の電流値の−40℃から125℃における温度変化率が±0.2%/℃未満となるように設定されている
請求項1または2に記載の電流源。 - 前記バイアスは、前記電流の電流値の−40℃から125℃における温度変化率が±0.1%/℃未満となるように設定されている
請求項1から3までのいずれか一項に記載の電流源。 - 前記バイアスは、前記電流の電流値の−40℃〜125℃における温度変化率が±0.05%/℃未満となるように設定されている
請求項1から4までのいずれか一項に記載の電流源。 - 前記バイアスは、前記電流の電流値の−40℃〜125℃における温度変化率が0%/℃未満となるように設定されている
請求項1から5までのいずれか一項に記載の電流源。 - 前記電流の電流値は、100nA未満である
請求項1から6までのいずれか一項に記載の電流源。 - 前記不揮発性記憶素子は、電荷注入口を有し、
前記電荷注入口は、前記電流の経路とは接していない領域に形成されている
請求項1から7までのいずれか一項に記載の電流源。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016205209A JP6751002B2 (ja) | 2016-10-19 | 2016-10-19 | 電流源 |
EP17861693.4A EP3514655A4 (en) | 2016-10-19 | 2017-10-03 | POWER SOURCE |
US16/342,997 US11249503B2 (en) | 2016-10-19 | 2017-10-03 | Current source with nonvolatile storage element |
PCT/JP2017/036025 WO2018074225A1 (ja) | 2016-10-19 | 2017-10-03 | 電流源 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016205209A JP6751002B2 (ja) | 2016-10-19 | 2016-10-19 | 電流源 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018067143A true JP2018067143A (ja) | 2018-04-26 |
JP6751002B2 JP6751002B2 (ja) | 2020-09-02 |
Family
ID=62018476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016205209A Active JP6751002B2 (ja) | 2016-10-19 | 2016-10-19 | 電流源 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11249503B2 (ja) |
EP (1) | EP3514655A4 (ja) |
JP (1) | JP6751002B2 (ja) |
WO (1) | WO2018074225A1 (ja) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05119859A (ja) * | 1991-10-24 | 1993-05-18 | Sony Corp | 基準電圧発生回路 |
JP2002006968A (ja) * | 2000-06-23 | 2002-01-11 | Ricoh Co Ltd | 基準電圧発生回路及び電源装置 |
JP2002368107A (ja) * | 2001-06-07 | 2002-12-20 | Ricoh Co Ltd | 基準電圧発生回路とそれを用いた電源装置 |
JP2010170533A (ja) * | 2008-12-22 | 2010-08-05 | Seiko Instruments Inc | 基準電圧回路及び半導体装置 |
JP2014071515A (ja) * | 2012-09-27 | 2014-04-21 | Seiko Instruments Inc | 基準電圧発生装置 |
US20150008496A1 (en) * | 2011-12-02 | 2015-01-08 | Board Of Trustees Of Michigan State University | Temperature compensation method for high-density floating-gate memory |
JP2015011454A (ja) * | 2013-06-27 | 2015-01-19 | 旭化成エレクトロニクス株式会社 | 基準電圧発生回路及び基準電圧発生方法 |
JP2016129293A (ja) * | 2015-01-09 | 2016-07-14 | 旭化成エレクトロニクス株式会社 | 電圧検出器 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930171A (en) * | 1995-05-22 | 1999-07-27 | Siemens Aktiengesellschaft | Constant-current source with an EEPROM cell |
KR100413652B1 (ko) | 1995-09-11 | 2004-05-27 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체기억장치및그구동방법 |
US6552603B2 (en) | 2000-06-23 | 2003-04-22 | Ricoh Company Ltd. | Voltage reference generation circuit and power source incorporating such circuit |
US6747896B2 (en) * | 2002-05-06 | 2004-06-08 | Multi Level Memory Technology | Bi-directional floating gate nonvolatile memory |
JP4473627B2 (ja) | 2004-04-07 | 2010-06-02 | 株式会社リコー | 定電流源、その定電流源を使用した増幅回路及び定電圧回路 |
JP4632422B2 (ja) * | 2004-12-22 | 2011-02-16 | ルネサスエレクトロニクス株式会社 | 読み出し回路、及び不揮発性半導体記憶装置 |
JP2007294846A (ja) * | 2006-03-31 | 2007-11-08 | Ricoh Co Ltd | 基準電圧発生回路及びそれを用いた電源装置 |
EP3000006B1 (en) * | 2013-05-19 | 2018-02-28 | Julius Georgiou | All-cmos, low-voltage, wide-temperature range, voltage reference circuit |
CN105845688A (zh) * | 2015-02-03 | 2016-08-10 | 精工半导体有限公司 | 半导体非易失性存储元件及其制造方法 |
-
2016
- 2016-10-19 JP JP2016205209A patent/JP6751002B2/ja active Active
-
2017
- 2017-10-03 WO PCT/JP2017/036025 patent/WO2018074225A1/ja unknown
- 2017-10-03 EP EP17861693.4A patent/EP3514655A4/en active Pending
- 2017-10-03 US US16/342,997 patent/US11249503B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05119859A (ja) * | 1991-10-24 | 1993-05-18 | Sony Corp | 基準電圧発生回路 |
JP2002006968A (ja) * | 2000-06-23 | 2002-01-11 | Ricoh Co Ltd | 基準電圧発生回路及び電源装置 |
JP2002368107A (ja) * | 2001-06-07 | 2002-12-20 | Ricoh Co Ltd | 基準電圧発生回路とそれを用いた電源装置 |
JP2010170533A (ja) * | 2008-12-22 | 2010-08-05 | Seiko Instruments Inc | 基準電圧回路及び半導体装置 |
US20150008496A1 (en) * | 2011-12-02 | 2015-01-08 | Board Of Trustees Of Michigan State University | Temperature compensation method for high-density floating-gate memory |
JP2014071515A (ja) * | 2012-09-27 | 2014-04-21 | Seiko Instruments Inc | 基準電圧発生装置 |
JP2015011454A (ja) * | 2013-06-27 | 2015-01-19 | 旭化成エレクトロニクス株式会社 | 基準電圧発生回路及び基準電圧発生方法 |
JP2016129293A (ja) * | 2015-01-09 | 2016-07-14 | 旭化成エレクトロニクス株式会社 | 電圧検出器 |
Also Published As
Publication number | Publication date |
---|---|
US20190243405A1 (en) | 2019-08-08 |
JP6751002B2 (ja) | 2020-09-02 |
EP3514655A1 (en) | 2019-07-24 |
WO2018074225A1 (ja) | 2018-04-26 |
EP3514655A4 (en) | 2019-11-20 |
US11249503B2 (en) | 2022-02-15 |
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