JP2018037631A - メモリデバイスの製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 71
- 238000002955 isolation Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- 238000000926 separation method Methods 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 150000003254 radicals Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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Abstract
【解決手段】メモリデバイスを製造する方法が提供される。本方法では、第1ゲート誘電体層が第1領域内の基板上に形成される。第2ゲート誘電体層が第2及び第3領域内の基板上に形成される。第1導電層が基板上に形成される。第1誘電体層が直接第1導電層上に形成される。第2領域内の第1誘電体層の一部分、第1導電層の一部分、及び第2ゲート誘電体層の一部分が除去される。第3導電層及び第2ゲート誘電体層が第2領域内の基板上に順次に形成される。第3導電層及び第2誘電体層が基板上に順次に形成される。絶縁分離構造が基板内に形成される。ここで、絶縁分離構造は第2の誘電体層を貫通し、基板内にまで延在する。
【選択図】図1K
Description
400 基板
410 深いウェル
420 第1ウェル
430 第1高電圧ウェル
440,442,444 第2高電圧ウェル
450 第1低電圧ウェル
460 第2低電圧ウェル
470,480 マスク層
485,485a,485b 階段状開口
490 分離構造
500 セル領域
510 高電圧ゲート誘電体層
520 トンネル誘電体層
530 第1導電層
550 第1誘電体層
560 低電圧ゲート誘電体層
570 第2導電層
580 第3導電層
590 第2誘電体層
600 周辺領域
610 高電圧デバイス領域
620 低電圧デバイス領域
D1,D2 距離
R1,R3 凹部
R2,R4 溝
S101−S107,S201−S207 ステップ
Claims (10)
- メモリデバイスを製造する方法であって、前記方法は、
第1領域と第2領域と第3領域に分割された基板を準備するステップと、
前記第1領域内の前記基板上に第1ゲート誘電体層を形成するステップと、
前記第2領域及び前記第3領域内の前記基板上に第2ゲート誘電体層を形成するステップと、
前記基板上に第1導電層を形成するステップと、
前記第1導電層上に直接第1誘電体層を形成するステップと、
前記第2領域内の前記基板の表面を部分的に露出させるために、前記第2領域内の前記第1誘電体層の一部分、前記第1導電層の一部分及び前記第2ゲート誘電体層の一部分を除去するステップと、
前記第2領域内の前記基板上に第3ゲート誘電体層及び第2導電層を順次に形成するステップと、
前記基板上に第3導電層及び第2誘電体層を順次に形成するステップと、
前記基板内に、前記第2誘電体層を貫通して基板にまで達する複数の分離構造を形成するステップと、
を備える方法。 - 前記第1導電層は前記第1誘電体層に直接接触している、請求項1記載の方法。
- 前記第3ゲート誘電体層及び前記第2導電層を形成するステップにおいて、溝が前記第2領域内の前記基板に同時に形成され、前記分離構造の一つを形成する方法は、トレンチを形成するために前記溝の上部の前記第2誘電体層及び前記第3導電層のみならず前記溝の周囲の前記基板及び前記第1導電層も除去するステップと前記トレンチを分離材料層で満たすステップとを含む、請求項1又は2記載の方法。
- 前記第3領域内の前記第2ゲート誘電体層はトンネル誘電体層である、請求項1−3の何れかに記載の方法。
- 前記第2領域内の前記第1誘電体層の一部分、前記第1導電層の一部分及び前記第2ゲート誘電体層の一部分を除去するステップは、
前記第3領域内の前記基板の表面を部分的に露出させるために、前記第3領域内の前記第1誘電体層の一部分、前記第1導電層の一部分及び前記第2ゲート誘電体層の一部分を除去するステップを更に含む、
請求項1又は2記載の方法。 - 前記第2領域内の前記基板上に前記第3ゲート誘電体層及び前記第2導電層を順次に形成するステップは、
前記第3領域内の前記基板上に前記第3ゲート誘電体層及び前記第2導電層を順次に形成するステップを更に含み、前記第3領域内の前記第3ゲート誘電体層はトンネル誘電体層である、
請求項5記載の方法。 - 前記第2領域及び前記第3領域内の前記基板上に前記第3ゲート誘電体層及び前記第2導電層を順次に形成するステップにおいて、一つの溝が前記第2領域内の前記基板に同時に形成されるとともに、別の溝が前記第3領域内の前記基板に同時に形成され、前記分離構造の一つを形成する方法は、2つのトレンチを形成するために前記溝の上部の前記第2誘電体層及び前記第3導電層のみならず前記溝の周囲の前記基板及び前記第1導電層も除去するステップと前記トレンチを分離材料層で満たすステップとを含む、請求項6記載の方法。
- 前記第1ゲート誘電体層を形成する前に、
第1導電型の深いウェルを前記第3領域内の前記基板内に形成するステップと、
第2導電型の第1ウェルを前記深いウェル上に形成するステップと、
前記第1導電型の2つの高電圧ウェルを前記深いウェルの両側にそれぞれ形成するステップと、
を更に備える、請求項1−7のいずれかに記載の方法。 - 前記第1ゲート誘電体層の厚さ、前記第2ゲート誘電体層の厚さ及び前記第3ゲート誘電体層の厚さは互いに異なる、請求項1−8のいずれかに記載の方法。
- 前記第1ゲート誘電体層の厚さは10nm〜40nmである、請求項1−9のいずれかに記載の方法。
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JP6302107B2 (ja) | 2018-03-28 |
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