JP2018019045A - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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- JP2018019045A JP2018019045A JP2016150848A JP2016150848A JP2018019045A JP 2018019045 A JP2018019045 A JP 2018019045A JP 2016150848 A JP2016150848 A JP 2016150848A JP 2016150848 A JP2016150848 A JP 2016150848A JP 2018019045 A JP2018019045 A JP 2018019045A
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Abstract
Description
実施の形態1にかかる炭化珪素半導体装置の構造について説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構造を示す断面図である。図1には、活性領域41に配置された複数のセルのうちの隣接する2つのセル(素子の構成単位)を示すが、すべてのセルは同じセル構造(単位構造)を有する(図3〜7においても同様)。図1に示す実施の形態1にかかる炭化珪素半導体装置は、炭化珪素からなる半導体基体(炭化珪素基体:半導体チップ)10のおもて面(p型ベース領域4側の面)側にトレンチゲート構造のMOSゲートを備えたトレンチゲート型SiC−MOSFETである。
次に、実施の形態2において、実施の形態1にかかる炭化珪素半導体装置(図1参照)の平面レイアウトについて説明する。図9は、実施の形態2にかかる炭化珪素半導体装置の平面レイアウトを示す平面図である。平面レイアウトとは、炭化珪素基体10のおもて面側から見た各部の平面形状および配置構成である。図9には、活性領域41におけるトレンチ7およびp++型コンタクト領域6の平面レイアウトを示し、ゲート絶縁膜8および基体おもて面の表面層に設けられた各領域は図示省略する(図10〜12においても同様)。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図13は、実施の形態3にかかる炭化珪素半導体装置の構造を示す断面図である。図13は、図14の切断線B−B’における断面構造である。図14は、実施の形態3にかかる炭化珪素半導体装置の平面レイアウトを示す平面図である。図14には、トレンチ7を塗りつぶして示す(図16〜18においても同様)。実施の形態3にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、ソース電極16が第2メサ部32のn+型ソース領域5と接する点である。
次に、実施の形態4にかかる炭化珪素半導体装置の構造について説明する。図15は、実施の形態4にかかる炭化珪素半導体装置の構造を示す断面図である。図15は、図16の切断線C−C’における断面構造である。図16は、実施の形態4にかかる炭化珪素半導体装置の平面レイアウトを示す平面図である。実施の形態4にかかる炭化珪素半導体装置は、実施の形態1において、第2p+型領域12の間引き数を3個にした場合のトレンチゲート型SiC−MOSFETである。
次に、実施の形態5にかかる炭化珪素半導体装置の構造について説明する。図17は、実施の形態5にかかる炭化珪素半導体装置の平面レイアウトを示す平面図である。図18は、実施の形態5にかかる炭化珪素半導体装置の別の一例の平面レイアウトを示す平面図である。図17の切断線D−D’における断面構造は、実施の形態3の図13に相当する。図18の切断線E−E’における断面構造は、実施の形態4の図15に相当する。図17,18には、第1,2p+型領域11,12(ハッチング部分)およびJFET領域13a,13b(白抜き部分)の平面レイアウトを示す。
次に、実施の形態6にかかる炭化珪素半導体装置の構造について説明する。図19は、実施の形態6にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態6にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、n型CSL領域3の内部において、第2p+型領域12直下(ドレイン側)に、第2p+型領域12に接して、n型CSL領域(以下、部分n型CSL領域とする)61を選択的に設けた点である。部分n型CSL領域61は、n型CSL領域3よりも不純物濃度が高い。部分n型CSL領域61の幅は、例えば第2p+型領域12の幅w2と同じであってもよい。
2 n-型ドリフト領域
3 n型CSL領域
3a,3b n型部分領域
4 p型ベース領域
5 n+型ソース領域
6 p++型コンタクト領域
6' 最外p++型コンタクト領域
6a p+型コンタクト領域の終端部
6b p+型コンタクト領域の連結部
6c 部分p+型コンタクト領域
7 トレンチ
7a トレンチの終端部
7b トレンチの連結部
7c トレンチの終端部
8 ゲート絶縁膜
9 ゲート電極
10 炭化珪素基体
11 トレンチ底面のp+型領域(第1p+型領域)
12 トレンチ間のp+型領域(第2p+型領域)
12' 最外第2p+型領域
12a,12b p+型部分領域
13a,13b JFET領域
14 層間絶縁膜
14a, 14b コンタクトホール
15 バリアメタル
16 ソース電極
17 ソースパッド
18 ドレイン電極
19 ゲートランナー
19a ゲートランナーの直線部
19b ゲートランナーの連結部
21,21a,21b n-型炭化珪素層
22 p型炭化珪素層
30,31,32 メサ部
41 活性領域
42 エッジ終端領域
43 活性領域とエッジ終端領域との間に形成される段差
43a 段差のステア
44 JTE構造のp+型領域
45 JTE構造のp型領域
46 n型チャネルストッパ領域
51 酸化膜
52 フィールド酸化膜
53 HTO膜
54 ドープトポリシリコン層
55 レジストマスク
61 部分n型CSL領域
X トレンチがストライプ状に延びる方向(第1方向)
Y トレンチがストライプ状に延びる方向と直交する方向(第2方向)
w1 第1p+型領域の幅
w2 第2p+型領域の幅
w3,w4 JFET領域の幅
w5,w5' セルピッチ
w6 トレンチの幅
Claims (10)
- 第1導電型の炭化珪素基板のおもて面から所定の深さで設けられた複数のトレンチと、
隣り合う前記トレンチ間に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられた第1導電型の第2半導体領域と、
前記炭化珪素基板の内部に選択的に設けられ、前記トレンチの底面を覆う第2導電型の第3半導体領域と、
前記炭化珪素基板の内部に選択的に設けられ、隣り合う前記トレンチ間において前記第1半導体領域に接する第2導電型の第4半導体領域と、
前記トレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極と、
1つの前記トレンチの内部の前記ゲート電極で構成された絶縁ゲート構造を有し、所定ピッチで複数配置された単位構造と、
前記第1半導体領域および前記第2半導体領域に接続された第1電極と、
前記炭化珪素基板の裏面に接続された第2電極と、
を備え、
隣り合う前記第4半導体領域の間には、2つ以上の前記トレンチが配置されていることを特徴とする炭化珪素半導体装置。 - 前記第4半導体領域は、前記第3半導体領域と離して設けられていることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記第4半導体領域は、隣り合う前記第3半導体領域と部分的に連結されていることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 隣り合う前記第4半導体領域の間には、3つ以上の前記トレンチが配置され、
隣り合う前記第3半導体領域同士は、部分的に連結されていることを特徴とする請求項3に記載の炭化珪素半導体装置。 - 前記トレンチは、前記炭化珪素基板のおもて面に平行な方向に延びるストライプ状のレイアウトに配置されていることを特徴とする請求項1〜4のいずれか一つに記載の炭化珪素半導体装置。
- 前記第1半導体領域の内部に選択的に設けられた第2導電型の第5半導体領域と、
前記第1半導体領域の内部に選択的に設けられた第2導電型の第6半導体領域と、
をさらに備え、
前記第5半導体領域は、深さ方向に前記第4半導体領域に対向する位置に配置され、
前記第6半導体領域は、隣り合う前記第4半導体領域の間に配置された2つ以上の前記トレンチの終端部付近に配置され、
前記第1電極は、前記第5半導体領域および前記第6半導体領域を介して前記第1半導体領域に接続されていることを特徴とする請求項5に記載の炭化珪素半導体装置。 - 前記所定ピッチは4μm以下であることを特徴とする請求項1〜6のいずれか一つに記載の炭化珪素半導体装置。
- 第1導電型の炭化珪素基板のおもて面から所定の深さで設けられたトレンチと、前記トレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極と、で構成された1つの絶縁ゲート構造を有する単位構造を所定ピッチで複数配置した炭化珪素半導体装置の製造方法であって、
前記炭化珪素基板のおもて面から所定の深さで複数の前記トレンチを形成する第1工程と、
前記トレンチの内壁に沿ってゲート絶縁膜を形成する第2工程と、
前記トレンチの内部に埋め込むように、前記炭化珪素基板のおもて面および前記ゲート絶縁膜の表面にポリシリコン層を形成する第3工程と、
前記ゲート絶縁膜が露出するまで前記ポリシリコン層をエッチバックして、前記トレンチの内部に前記ゲート電極となる前記ポリシリコン層を残す第4工程と、によって前記絶縁ゲート構造を有する前記単位構造を形成することを特徴とする炭化珪素半導体装置の製造方法。 - 前記絶縁ゲート構造は、
隣り合う前記トレンチ間に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられた第1導電型の第2半導体領域と、を備え、
前記第1工程の前に、
炭化珪素からなる出発基板のおもて面に、第1導電型の第1炭化珪素層を堆積する工程と、
前記第1炭化珪素層の内部に、第2導電型の第3半導体領域を選択的に形成する工程と、
前記第1炭化珪素層の内部に、前記第1炭化珪素層の表面に露出するように、第2導電型の第4半導体領域を選択的に形成する工程と、
前記第3半導体領域および第4半導体領域を覆うように、前記第1半導体領域となる第2導電型の第2炭化珪素層を堆積し、前記出発基板、前記第1炭化珪素層および前記第2炭化珪素層を順に堆積してなる前記炭化珪素基板を形成する工程と、
前記第2炭化珪素層の内部に、前記第2半導体領域を選択的に形成する工程と、をさらに含み、
前記第1工程では、前記第2半導体領域および前記第2炭化珪素層を貫通して前記第3半導体領域に達する前記トレンチを形成することを特徴とする請求項8に記載の炭化珪素半導体装置の製造方法。 - 前記第4工程の後、
前記第2半導体領域および前記第2炭化珪素層に接続する第1電極を形成する工程と、
前記炭化珪素基板の裏面に接続する第2電極を形成する工程と、をさらに含むことを特徴とする請求項9に記載の炭化珪素半導体装置の製造方法。
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Cited By (9)
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