JP2018011070A - 集積回路構造、非平面型半導体デバイスおよび非平面型半導体デバイスを製造する方法 - Google Patents
集積回路構造、非平面型半導体デバイスおよび非平面型半導体デバイスを製造する方法 Download PDFInfo
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- JP2018011070A JP2018011070A JP2017169678A JP2017169678A JP2018011070A JP 2018011070 A JP2018011070 A JP 2018011070A JP 2017169678 A JP2017169678 A JP 2017169678A JP 2017169678 A JP2017169678 A JP 2017169678A JP 2018011070 A JP2018011070 A JP 2018011070A
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Abstract
Description
Claims (20)
- 基板の上方に配置され、組成の異なる上層と下層との間にヘテロ接合を有するヘテロ構造と、
前記ヘテロ構造の上方に配置され、前記ヘテロ構造の前記上層および前記下層とは異なる組成を有する活性層と、
前記活性層のチャネル領域上に配置されて前記チャネル領域を完全に包囲するとともに、前記ヘテロ構造の前記上層中および少なくとも部分的に前記下層中のトレンチに配置されるゲート電極スタックと、
前記ゲート電極スタックのどちらかの側において前記活性層中および前記上層中に配置され、前記下層中には配置されないソース・ドレイン領域と、
を備える非平面型半導体デバイス。 - 前記活性層の前記チャネル領域は前記下層よりも低いバンドギャップを有し、前記下層は前記上層よりも低いバンドギャップを有する、請求項1に記載の非平面型半導体デバイス。
- 前記活性層の前記チャネル領域は本質的にゲルマニウムから成り、前記下層はSixGe1−xを含み、前記上層はSiyGe1−yを含み、y>xである、請求項2に記載の非平面型半導体デバイス。
- yは約0.5であり、xは約0.3である、請求項3に記載の非平面型半導体デバイス。
- 前記活性層、前記下層、および前記上層は、それぞれ異なるIII−V族材料を含む、請求項2に記載の非平面型半導体デバイス。
- 前記ゲート電極スタックは、前記ヘテロ構造中にて、前記ヘテロ構造中の前記ソース・ドレイン領域の深さの約2−4倍の深さまで配置される、請求項1から請求項5のいずれか1項に記載の非平面型半導体デバイス。
- 前記ソース・ドレイン領域に隣接し、少なくとも部分的に前記ヘテロ構造中に配置される複数の分離領域をさらに備え、
前記ゲート電極スタックは、前記ヘテロ構造中にて、前記複数の分離領域の深さよりも深い深さまで配置される、請求項1から請求項6のいずれか1項に記載の非平面型半導体デバイス。 - 前記ゲート電極スタックは、前記トレンチと並ぶhigh−kゲート誘電体層、および、前記high−kゲート誘電体層内のメタルゲート電極を含む、請求項1から請求項7のいずれか1項に記載の非平面型半導体デバイス。
- 前記活性層の上方において、垂直に並ぶように配置された一または複数のナノワイヤをさらに備え、
前記ゲート電極スタックは、前記一または複数のナノワイヤのそれぞれのチャネル領域上に配置され、前記チャネル領域を完全に包囲する、請求項1から請求項8のいずれか1項に記載の非平面型半導体デバイス。 - 組成の異なる上層と下層との間にヘテロ接合を有するヘテロ構造を基板の上方に形成する段階と、
前記ヘテロ構造の前記上層および前記下層とは異なる組成を有する活性層を前記ヘテロ構造の上方に形成する段階と、
前記上層中および少なくとも部分的に前記下層中にトレンチを形成する段階と、
ゲート電極スタックを、前記活性層のチャネル領域上にて前記チャネル領域を完全に包囲するように、且つ、前記上層中および少なくとも部分的に前記下層中の前記トレンチに形成する段階と、
ソース・ドレイン領域を、前記下層中には形成せずに、前記ゲート電極スタックのどちらかの側において前記活性層中および前記上層中に形成する段階と、
を備える、非平面型半導体デバイスを製造する方法。 - 前記上層中および少なくとも部分的に前記下層中に前記トレンチを形成する段階は、リプレースメントゲートプロセスにおけるダミーゲート構造の除去の後に続けて実行される、請求項10に記載の方法。
- 前記活性層の前記チャネル領域は前記下層よりも低いバンドギャップを有し、前記下層は前記上層よりも低いバンドギャップを有する、請求項10または請求項11に記載の方法。
- 前記活性層の前記チャネル領域は本質的にゲルマニウムから成り、前記下層はSixGe1−xを含み、前記上層はSiyGe1−yを含み、y>xである、請求項12に記載の方法。
- yは約0.5であり、xは約0.3である、請求項13に記載の方法。
- 前記活性層の前記チャネル領域、前記下層、および前記上層は、それぞれ異なるIII−V族材料を含む、請求項12に記載の方法。
- 前記ゲート電極スタックは、前記ヘテロ構造中にて、前記ヘテロ構造中の前記ソース・ドレイン領域の深さの約2−4倍の深さまで形成される、請求項10から請求項15のいずれか1項に記載の方法。
- 前記ソース・ドレイン領域に隣接する複数の分離領域を、少なくとも部分的に前記ヘテロ構造中に形成する段階をさらに備える、請求項10から請求項16のいずれか1項に記載の方法。
- 前記ゲート電極スタックは、前記ヘテロ構造中にて、前記複数の分離領域の深さよりも深い深さまで形成される、請求項17に記載の方法。
- 前記ゲート電極スタックは、前記トレンチと並ぶhigh−kゲート誘電体層、および、前記high−kゲート誘電体層内のメタルゲート電極を含む、請求項10から請求項18のいずれか1項に記載の方法。
- 前記活性層の上方に、一または複数のナノワイヤを垂直に並ぶように形成する段階をさらに備え、前記ゲート電極スタックは、前記一または複数のナノワイヤのそれぞれのチャネル領域上に形成され、前記チャネル領域を完全に包囲する、請求項10から請求項19のいずれか1項に記載の方法。
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