JP2017108070A - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP2017108070A
JP2017108070A JP2015242390A JP2015242390A JP2017108070A JP 2017108070 A JP2017108070 A JP 2017108070A JP 2015242390 A JP2015242390 A JP 2015242390A JP 2015242390 A JP2015242390 A JP 2015242390A JP 2017108070 A JP2017108070 A JP 2017108070A
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JP
Japan
Prior art keywords
layer
wiring
opening
metal layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015242390A
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English (en)
Japanese (ja)
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JP2017108070A5 (https=
Inventor
清水　浩
Hiroshi Shimizu
浩 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015242390A priority Critical patent/JP2017108070A/ja
Priority to US15/366,530 priority patent/US9780020B2/en
Publication of JP2017108070A publication Critical patent/JP2017108070A/ja
Publication of JP2017108070A5 publication Critical patent/JP2017108070A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2015242390A 2015-12-11 2015-12-11 配線基板、半導体装置及び配線基板の製造方法 Pending JP2017108070A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015242390A JP2017108070A (ja) 2015-12-11 2015-12-11 配線基板、半導体装置及び配線基板の製造方法
US15/366,530 US9780020B2 (en) 2015-12-11 2016-12-01 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015242390A JP2017108070A (ja) 2015-12-11 2015-12-11 配線基板、半導体装置及び配線基板の製造方法

Publications (2)

Publication Number Publication Date
JP2017108070A true JP2017108070A (ja) 2017-06-15
JP2017108070A5 JP2017108070A5 (https=) 2018-11-22

Family

ID=59020885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015242390A Pending JP2017108070A (ja) 2015-12-11 2015-12-11 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US9780020B2 (https=)
JP (1) JP2017108070A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163773B1 (en) * 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
JP2019149442A (ja) 2018-02-27 2019-09-05 株式会社デンソーウェーブ プリント配線の製造方法、及びプリント配線
JP2024108886A (ja) * 2023-01-31 2024-08-13 キオクシア株式会社 配線基板及び半導体装置

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342144A (ja) * 1986-08-08 1988-02-23 Hitachi Ltd 多層配線構造体
JPH0529375A (ja) * 1991-07-23 1993-02-05 Murata Mfg Co Ltd 半導体装置
JP2004087837A (ja) * 2002-08-27 2004-03-18 Ngk Spark Plug Co Ltd 配線基板の製造方法、配線基板
JP2005005743A (ja) * 2001-10-31 2005-01-06 Shinko Electric Ind Co Ltd 半導体装置用多層回路基板の製造方法
JP2006080571A (ja) * 2005-12-01 2006-03-23 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2006324642A (ja) * 2005-04-19 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
JP2008085308A (ja) * 2006-08-30 2008-04-10 Sanyo Electric Co Ltd 素子搭載用基板、半導体モジュールおよび携帯機器
JP2008263125A (ja) * 2007-04-13 2008-10-30 Shinko Electric Ind Co Ltd 配線基板の製造方法及び半導体装置の製造方法及び配線基板
JP2015162607A (ja) * 2014-02-27 2015-09-07 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2015179802A (ja) * 2013-09-30 2015-10-08 京セラサーキットソリューションズ株式会社 配線基板
JP2015211194A (ja) * 2014-04-30 2015-11-24 イビデン株式会社 プリント配線板および半導体パッケージ、ならびにプリント配線板の製造方法
JP2015222753A (ja) * 2014-05-22 2015-12-10 イビデン株式会社 プリント配線板及びその製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342144A (ja) * 1986-08-08 1988-02-23 Hitachi Ltd 多層配線構造体
JPH0529375A (ja) * 1991-07-23 1993-02-05 Murata Mfg Co Ltd 半導体装置
JP2005005743A (ja) * 2001-10-31 2005-01-06 Shinko Electric Ind Co Ltd 半導体装置用多層回路基板の製造方法
JP2004087837A (ja) * 2002-08-27 2004-03-18 Ngk Spark Plug Co Ltd 配線基板の製造方法、配線基板
JP2006324642A (ja) * 2005-04-19 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
JP2006080571A (ja) * 2005-12-01 2006-03-23 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2008085308A (ja) * 2006-08-30 2008-04-10 Sanyo Electric Co Ltd 素子搭載用基板、半導体モジュールおよび携帯機器
JP2008263125A (ja) * 2007-04-13 2008-10-30 Shinko Electric Ind Co Ltd 配線基板の製造方法及び半導体装置の製造方法及び配線基板
JP2015179802A (ja) * 2013-09-30 2015-10-08 京セラサーキットソリューションズ株式会社 配線基板
JP2015162607A (ja) * 2014-02-27 2015-09-07 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2015211194A (ja) * 2014-04-30 2015-11-24 イビデン株式会社 プリント配線板および半導体パッケージ、ならびにプリント配線板の製造方法
JP2015222753A (ja) * 2014-05-22 2015-12-10 イビデン株式会社 プリント配線板及びその製造方法

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Publication number Publication date
US9780020B2 (en) 2017-10-03
US20170170104A1 (en) 2017-06-15

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