JP2008085308A - 素子搭載用基板、半導体モジュールおよび携帯機器 - Google Patents
素子搭載用基板、半導体モジュールおよび携帯機器 Download PDFInfo
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- JP2008085308A JP2008085308A JP2007211172A JP2007211172A JP2008085308A JP 2008085308 A JP2008085308 A JP 2008085308A JP 2007211172 A JP2007211172 A JP 2007211172A JP 2007211172 A JP2007211172 A JP 2007211172A JP 2008085308 A JP2008085308 A JP 2008085308A
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- element mounting
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- pad electrode
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
【解決手段】素子搭載用基板100は、基材1に設けられたパッド電極4と、パッド電極4の上面部の少なくとも一部に開口部5を有するように基材1を覆う絶縁層6と、パッド電極4の上の開口部5内に設けられた融着層7と、を備え、融着層7の表面が開口部5の上端よりも低いことを特徴とした。
【選択図】図1
Description
以下、本発明にかかる素子搭載用基板を具体化した第1の実施形態について、図1及び図2を参照して説明する。
図5(A)は、素子搭載用基板100が有するソルダーレジスト層6の側面の形状を示す。図5(B)は、はんだバンプに使用されるはんだ107の接触角を示す。ソルダーレジスト層6の側面最下部の接線Sと、パッド電極4の表面とがなす角(θ1:図5(A)参照)が、はんだバンプを形成するはんだ107とパッド電極4との接触角(θ2:図5(B)参照)に比べて大きいことが望ましい。すなわち、ソルダーレジスト層6の側面形状に関連するθ1に関して、θ1>θ2という関係が成立していることが望ましい。
はんだバンプ7の厚みは、実装対象となるLSIチップを搭載したときに、はんだバンプ7と当該LSIチップに設けられたはんだボールとが接するように形成されていることが望ましい。これによれば、はんだ溶融時にはんだバンプ7とLSIチップのはんだボールとが一体化しやすくなり、はんだの表面張力によるセルフアライメントによりアライメント精度が向上する。
r:LSIチップ18bに設けられたはんだボール7bの半径
a:LSIチップ18bに設けられたはんだボール7bと接するソルダーレジスト層6の開口部の半径
d:LSIチップ18bに設けられたはんだボール7bとソルダーレジスト層6との接点Mからはんだバンプ7の表面の最上部までの距離
この場合には、下記関係式が成立する場合にはんだバンプ7とLSIチップ18a側のはんだボール7bとが接する。
d≦r−(r2−a2)1/2
すわなち、はんだバンプ7は、上記関係式が成立するのに十分な厚みを有することが望ましい。
a≧rの場合:
この場合には、LSIチップ18b側のはんだボール7bがソルダーレジスト層6の開口部に入り込めるため、はんだバンプ7とLSIチップ18b側のはんだボール7bとは常に接する。このため、はんだバンプ7は、ソルダーレジスト層6の厚みより小さい厚みを有していればよい。
次に、本発明にかかる素子搭載用基板を具体化した第2の実施形態について説明する。本実施形態にかかる素子搭載用基板も、その基本的な構造は先の第1の実施形態の素子搭載用基板に準じたものとなっている。ただし、本実施形態にかかる素子搭載用基板では、配線板が多層である点で異なる。こうした素子搭載用基板について、図5を参照しつつ説明する。なお、先の第1の実施形態と同様あるいはそれに準じた構造については、同一符合を付すと共にその詳細な説明を割愛する。
形成されている。ソルダーレジスト層6は、導電層16の保護膜として機能する。また、ソルダーレジスト層6は、メラミン誘導体、液晶ポリマー、エポキシ樹脂、PPE(ポリフェニレンエーテル)樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂およびポリアミドビスマレイミドなどの熱硬化性樹脂からなる。なお、液晶ポリマー、エポキシ樹脂およびメラミン誘導体は、高周波特性に優れているので、ソルダーレジスト層6の材料として好ましい。また、ソルダーレジスト層6に、SiO2などのフィラーを添加してもよい。
図14は、第3の実施形態に係る素子搭載用基板300にLSIチップが実装された半導体モジュール310の構造を示す断面図である。本実施形態の半導体モジュール310は、LSIなどの回路素子18c、18d、および抵抗、キャパシタなどの受動素子319を含む。まず、素子搭載用基板300の構造について説明する。コア材となる絶縁層302の上に配線層303がパターニングされている。素子搭載用基板300の中央部分に、フリップチップ接続用としてニッケル金メッキ層304を有するフリップチップパッド305が設けられている。ニッケル金メッキ層304の上に、はんだバンプ312が設けられている。
こうした素子搭載用基板は、上記各実施形態として示した構造に限らず、本発明の趣旨を逸脱しない範囲で同実施形態を適宜変更した例えば次のような形態として実施することもできる。
4 パッド電極
6 ソルダーレジスト層
7 はんだバンプ
100 素子搭載用基板
Claims (10)
- 基板に設けられたパッド電極と、
前記パッド電極の上面部の少なくとも一部に開口部を有するように前記基板を覆う絶縁層と、
前記パッド電極の上の前記開口部内に設けられた融着層と、を備え、
前記融着層の表面は前記開口部の上端よりも低く位置していることを特徴とした素子搭載用基板。 - 搭載対象となる回路素子に前記融着層と対応して形成されたはんだボールの曲率半径をr、前記開口部の半径をaとし、rがaより小さい場合に、
前記絶縁層の厚みと前記融着層の厚みとの差dが、d≦r−(r2−a2)1/2なる関係式を満たすことを特徴とする請求項1に記載の素子搭載用基板。 - 前記パッド電極の表面にニッケル金めっき層が設けられていることを特徴とする請求項1または2に記載の素子搭載用基板。
- 基板に設けられたパッド電極と、
前記パッド電極の上面部の少なくとも一部に開口部を有するように前記基板を覆う絶縁層と、
前記パッド電極の上の前記開口部内に設けられた融着層と、を備え、
前記開口部の側面が前記融着層の方向に凸状に湾曲していることを特徴とする素子搭載用基板。 - 前記開口部の半径が上部になるにつれて大きくなっていることを特徴とする請求項4に記載の素子搭載用基板。
- 前記融着層の表面は前記開口部の上端よりも低く位置していることを特徴とした請求項4または5に記載の素子搭載用基板。
- 前記絶縁層の側面最下部の接線と、前記融着層の表面とがなす角が、前記パッド電極上の前記融着層の接触角に比べて大きいことを特徴とする請求項4乃至6のいずれか1項に記載の素子搭載用基板。
- 前記パッド電極の表面にニッケル金めっき層が設けられていることを特徴とする請求項4乃至7のいずれか1項に記載の素子搭載用基板。
- 請求項1乃至8のいずれか1項に記載の素子搭載用基板と、
はんだバンプが設けられた回路素子と、
を備え、
前記融着層と前記はんだバンプとが接合されていることを特徴とする半導体モジュール。 - 請求項9に記載の半導体モジュールを備えることを特徴とした携帯機器。
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