JP2017102903A - メモリ管理メカニズムを具備する電子システム - Google Patents

メモリ管理メカニズムを具備する電子システム Download PDF

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Publication number
JP2017102903A
JP2017102903A JP2016200814A JP2016200814A JP2017102903A JP 2017102903 A JP2017102903 A JP 2017102903A JP 2016200814 A JP2016200814 A JP 2016200814A JP 2016200814 A JP2016200814 A JP 2016200814A JP 2017102903 A JP2017102903 A JP 2017102903A
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JP
Japan
Prior art keywords
memory
electronic system
bit line
hierarchical
sense amplifier
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Application number
JP2016200814A
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Japanese (ja)
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JP2017102903A5 (enExample
Inventor
クリシュナ ティー． マラディ，
T Malladi Krishna
クリシュナ ティー． マラディ，
郁 成 姜
Yucheng Jiang
郁 成 姜
宏 忠 チョン
Hong-Zhong Zheng
宏 忠 チョン
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2017102903A publication Critical patent/JP2017102903A/ja
Publication of JP2017102903A5 publication Critical patent/JP2017102903A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2016200814A 2015-12-03 2016-10-12 メモリ管理メカニズムを具備する電子システム Pending JP2017102903A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562262493P 2015-12-03 2015-12-03
US62/262,493 2015-12-03
US15/174,986 2016-06-06
US15/174,986 US9934154B2 (en) 2015-12-03 2016-06-06 Electronic system with memory management mechanism and method of operation thereof

Publications (2)

Publication Number Publication Date
JP2017102903A true JP2017102903A (ja) 2017-06-08
JP2017102903A5 JP2017102903A5 (enExample) 2019-10-03

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JP2016200814A Pending JP2017102903A (ja) 2015-12-03 2016-10-12 メモリ管理メカニズムを具備する電子システム

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US (1) US9934154B2 (enExample)
JP (1) JP2017102903A (enExample)
KR (1) KR102772894B1 (enExample)
CN (1) CN106847331B (enExample)
TW (1) TWI724036B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018196631A (ja) * 2017-05-24 2018-12-13 株式会社大一商会 遊技機
JP2018196628A (ja) * 2017-05-24 2018-12-13 株式会社大一商会 遊技機

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* Cited by examiner, † Cited by third party
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KR102353859B1 (ko) 2017-11-01 2022-01-19 삼성전자주식회사 컴퓨팅 장치 및 비휘발성 듀얼 인라인 메모리 모듈
US11288070B2 (en) 2019-11-04 2022-03-29 International Business Machines Corporation Optimization of low-level memory operations in a NUMA environment

Citations (7)

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JPH0969063A (ja) * 1995-06-07 1997-03-11 Hitachi Ltd 低電力メモリシステム
JP2007323192A (ja) * 2006-05-30 2007-12-13 Toshiba Corp キャッシュメモリ装置および処理方法
US20100095048A1 (en) * 2008-10-10 2010-04-15 Andreas Bechtolsheim Self-contained densely packed solid-state storage subsystem
JP2011118469A (ja) * 2009-11-30 2011-06-16 Toshiba Corp メモリ管理装置およびメモリ管理方法
US20120137075A1 (en) * 2009-06-09 2012-05-31 Hyperion Core, Inc. System and Method for a Cache in a Multi-Core Processor
US20130254488A1 (en) * 2012-03-20 2013-09-26 Stefanos Kaxiras System and method for simplifying cache coherence using multiple write policies
WO2014203383A1 (ja) * 2013-06-20 2014-12-24 株式会社日立製作所 異種メモリを混載したメモリモジュール、及びそれを搭載した情報処理装置

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US6178517B1 (en) * 1998-07-24 2001-01-23 International Business Machines Corporation High bandwidth DRAM with low operating power modes
US6992919B2 (en) 2002-12-20 2006-01-31 Integrated Magnetoelectronics Corporation All-metal three-dimensional circuits and memories
US7203123B2 (en) * 2004-12-08 2007-04-10 Infineon Technologies Ag Integrated DRAM memory device
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KR101498673B1 (ko) * 2007-08-14 2015-03-09 삼성전자주식회사 반도체 드라이브, 그것의 데이터 저장 방법, 그리고 그것을포함한 컴퓨팅 시스템
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JPH0969063A (ja) * 1995-06-07 1997-03-11 Hitachi Ltd 低電力メモリシステム
JP2007323192A (ja) * 2006-05-30 2007-12-13 Toshiba Corp キャッシュメモリ装置および処理方法
US20100095048A1 (en) * 2008-10-10 2010-04-15 Andreas Bechtolsheim Self-contained densely packed solid-state storage subsystem
US20120137075A1 (en) * 2009-06-09 2012-05-31 Hyperion Core, Inc. System and Method for a Cache in a Multi-Core Processor
JP2011118469A (ja) * 2009-11-30 2011-06-16 Toshiba Corp メモリ管理装置およびメモリ管理方法
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WO2014203383A1 (ja) * 2013-06-20 2014-12-24 株式会社日立製作所 異種メモリを混載したメモリモジュール、及びそれを搭載した情報処理装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018196631A (ja) * 2017-05-24 2018-12-13 株式会社大一商会 遊技機
JP2018196628A (ja) * 2017-05-24 2018-12-13 株式会社大一商会 遊技機

Also Published As

Publication number Publication date
CN106847331B (zh) 2019-11-26
KR20170065433A (ko) 2017-06-13
TW201729069A (zh) 2017-08-16
US9934154B2 (en) 2018-04-03
TWI724036B (zh) 2021-04-11
CN106847331A (zh) 2017-06-13
KR102772894B1 (ko) 2025-02-27
US20170161201A1 (en) 2017-06-08

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