JP2017102903A5 - - Google Patents

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Publication number
JP2017102903A5
JP2017102903A5 JP2016200814A JP2016200814A JP2017102903A5 JP 2017102903 A5 JP2017102903 A5 JP 2017102903A5 JP 2016200814 A JP2016200814 A JP 2016200814A JP 2016200814 A JP2016200814 A JP 2016200814A JP 2017102903 A5 JP2017102903 A5 JP 2017102903A5
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JP
Japan
Prior art keywords
memory
electronic system
hierarchical
hierarchical memory
bit line
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Pending
Application number
JP2016200814A
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English (en)
Japanese (ja)
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JP2017102903A (ja
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Publication date
Priority claimed from US15/174,986 external-priority patent/US9934154B2/en
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Publication of JP2017102903A publication Critical patent/JP2017102903A/ja
Publication of JP2017102903A5 publication Critical patent/JP2017102903A5/ja
Pending legal-status Critical Current

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JP2016200814A 2015-12-03 2016-10-12 メモリ管理メカニズムを具備する電子システム Pending JP2017102903A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562262493P 2015-12-03 2015-12-03
US62/262,493 2015-12-03
US15/174,986 2016-06-06
US15/174,986 US9934154B2 (en) 2015-12-03 2016-06-06 Electronic system with memory management mechanism and method of operation thereof

Publications (2)

Publication Number Publication Date
JP2017102903A JP2017102903A (ja) 2017-06-08
JP2017102903A5 true JP2017102903A5 (enExample) 2019-10-03

Family

ID=58799726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016200814A Pending JP2017102903A (ja) 2015-12-03 2016-10-12 メモリ管理メカニズムを具備する電子システム

Country Status (5)

Country Link
US (1) US9934154B2 (enExample)
JP (1) JP2017102903A (enExample)
KR (1) KR102772894B1 (enExample)
CN (1) CN106847331B (enExample)
TW (1) TWI724036B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6635469B2 (ja) * 2017-05-24 2020-01-22 株式会社大一商会 遊技機
JP6635472B2 (ja) * 2017-05-24 2020-01-29 株式会社大一商会 遊技機
KR102353859B1 (ko) 2017-11-01 2022-01-19 삼성전자주식회사 컴퓨팅 장치 및 비휘발성 듀얼 인라인 메모리 모듈
US11288070B2 (en) 2019-11-04 2022-03-29 International Business Machines Corporation Optimization of low-level memory operations in a NUMA environment

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687382A (en) * 1995-06-07 1997-11-11 Hitachi America, Ltd. High speed, reduced power memory system implemented according to access frequency
US6384439B1 (en) 1998-02-02 2002-05-07 Texas Instruments, Inc. DRAM memory cell and array having pass transistors with recessed channels
US6178517B1 (en) * 1998-07-24 2001-01-23 International Business Machines Corporation High bandwidth DRAM with low operating power modes
US6992919B2 (en) 2002-12-20 2006-01-31 Integrated Magnetoelectronics Corporation All-metal three-dimensional circuits and memories
US7203123B2 (en) * 2004-12-08 2007-04-10 Infineon Technologies Ag Integrated DRAM memory device
US7483422B2 (en) * 2005-02-10 2009-01-27 International Business Machines Corporation Data processing system, method and interconnect fabric for selective link information allocation in a data processing system
JP4208895B2 (ja) * 2006-05-30 2009-01-14 株式会社東芝 キャッシュメモリ装置および処理方法
KR101498673B1 (ko) * 2007-08-14 2015-03-09 삼성전자주식회사 반도체 드라이브, 그것의 데이터 저장 방법, 그리고 그것을포함한 컴퓨팅 시스템
US8335122B2 (en) * 2007-11-21 2012-12-18 The Regents Of The University Of Michigan Cache memory system for a data processing apparatus
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
US7934124B2 (en) * 2008-10-10 2011-04-26 Oracle America, Inc. Self-contained densely packed solid-state storage subsystem
KR20100095048A (ko) * 2009-02-20 2010-08-30 세심광전자기술(주) 금속 반사막을 갖는 액정변조기와 이를 이용한 박막트랜지스터 기판 검사장치
WO2010142432A2 (en) * 2009-06-09 2010-12-16 Martin Vorbach System and method for a cache in a multi-core processor
JP2011118469A (ja) * 2009-11-30 2011-06-16 Toshiba Corp メモリ管理装置およびメモリ管理方法
US8671263B2 (en) 2011-02-03 2014-03-11 Lsi Corporation Implementing optimal storage tier configurations for a workload in a dynamic storage tiering system
JP2012234940A (ja) * 2011-04-28 2012-11-29 Elpida Memory Inc 半導体装置
KR101246475B1 (ko) 2011-05-25 2013-03-21 에스케이하이닉스 주식회사 반도체 셀 및 반도체 소자
US8738875B2 (en) 2011-11-14 2014-05-27 International Business Machines Corporation Increasing memory capacity in power-constrained systems
DE112011105984B4 (de) 2011-12-20 2024-10-17 Intel Corporation Dynamische teilweise Abschaltung eines arbeitsspeicherseitigen Zwischenspeichers in einer Arbeitsspeicherhierarchie auf zwei Ebenen
US8873329B1 (en) * 2012-01-17 2014-10-28 Rambus Inc. Patterned memory page activation
US9274960B2 (en) * 2012-03-20 2016-03-01 Stefanos Kaxiras System and method for simplifying cache coherence using multiple write policies
US8811110B2 (en) 2012-06-28 2014-08-19 Intel Corporation Configuration for power reduction in DRAM
US11687292B2 (en) * 2013-02-26 2023-06-27 Seagate Technology Llc Data update management in a cloud computing environment
US9342443B2 (en) * 2013-03-15 2016-05-17 Micron Technology, Inc. Systems and methods for memory system management based on thermal information of a memory system
JP2014191622A (ja) * 2013-03-27 2014-10-06 Fujitsu Ltd 処理装置
US9858181B2 (en) * 2013-06-20 2018-01-02 Hitachi, Ltd. Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein
US9710226B1 (en) * 2013-07-16 2017-07-18 Rambus Inc. Unsuccessful write retry buffer

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