JP2016536584A - 集積回路をテストするための方法 - Google Patents

集積回路をテストするための方法 Download PDF

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Publication number
JP2016536584A
JP2016536584A JP2016526790A JP2016526790A JP2016536584A JP 2016536584 A JP2016536584 A JP 2016536584A JP 2016526790 A JP2016526790 A JP 2016526790A JP 2016526790 A JP2016526790 A JP 2016526790A JP 2016536584 A JP2016536584 A JP 2016536584A
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JP
Japan
Prior art keywords
integrated circuit
output
input
circuit portion
pad
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Pending
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JP2016526790A
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English (en)
Japanese (ja)
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JP2016536584A5 (cg-RX-API-DMAC7.html
Inventor
ボーゲラ、サガー
シンシア、デイジー
スリニバサン、スリカンス
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2016536584A publication Critical patent/JP2016536584A/ja
Publication of JP2016536584A5 publication Critical patent/JP2016536584A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2016526790A 2013-11-07 2014-10-28 集積回路をテストするための方法 Pending JP2016536584A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/074,672 US9304163B2 (en) 2013-11-07 2013-11-07 Methodology for testing integrated circuits
US14/074,672 2013-11-07
PCT/US2014/062538 WO2015069490A1 (en) 2013-11-07 2014-10-28 Methodology for testing integrated circuits

Publications (2)

Publication Number Publication Date
JP2016536584A true JP2016536584A (ja) 2016-11-24
JP2016536584A5 JP2016536584A5 (cg-RX-API-DMAC7.html) 2017-11-09

Family

ID=51900523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016526790A Pending JP2016536584A (ja) 2013-11-07 2014-10-28 集積回路をテストするための方法

Country Status (6)

Country Link
US (1) US9304163B2 (cg-RX-API-DMAC7.html)
EP (1) EP3066485A1 (cg-RX-API-DMAC7.html)
JP (1) JP2016536584A (cg-RX-API-DMAC7.html)
KR (1) KR20160083086A (cg-RX-API-DMAC7.html)
CN (1) CN105705957B (cg-RX-API-DMAC7.html)
WO (1) WO2015069490A1 (cg-RX-API-DMAC7.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020064040A (ja) * 2018-10-18 2020-04-23 普誠科技股▲ふん▼有限公司 集積回路、および、そのテスト方法
JP2020165711A (ja) * 2019-03-28 2020-10-08 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置

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US10559374B2 (en) * 2017-02-20 2020-02-11 Piecemakers Technology, Inc. Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
CN115843466B (zh) 2020-07-09 2025-07-15 特克特朗尼克公司 指示制造电子电路的探测目标
KR102884475B1 (ko) * 2021-11-24 2025-11-12 삼성전자주식회사 전자 장치의 진단 방법 및 장치
US12066490B2 (en) * 2022-05-16 2024-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis
CN117269735B (zh) * 2023-11-21 2024-01-23 甘肃送变电工程有限公司 基于电磁微波手段的电力工器具智能电子芯片检测方法
CN118733370B (zh) * 2024-09-02 2024-12-31 深圳市中兴微电子技术有限公司 一种芯粒、芯片及芯片调测方法

Citations (5)

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JP2004523912A (ja) * 2001-03-02 2004-08-05 クゥアルコム・インコーポレイテッド 混合アナログおよびデジタル集積回路
US6825683B1 (en) * 2002-04-18 2004-11-30 Cypress Semiconductor Corporation System and method for testing multiple integrated circuits that are in the same package
US20050193302A1 (en) * 2004-02-27 2005-09-01 Javier Arguelles Test switching circuit for a high speed data interface
JP2009528535A (ja) * 2006-03-01 2009-08-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｊｔａｇインターフェースを用いた試験アクセス制御回路を有するｉｃ回路
US20130035090A1 (en) * 2011-08-03 2013-02-07 Mehran Moshfeghi Repeater device for reducing the electromagnetic radiation transmitted from cellular phone antennas and extending phone battery life

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JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
US7161175B2 (en) 1997-09-30 2007-01-09 Jeng-Jye Shau Inter-dice signal transfer methods for integrated circuits
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US20030126533A1 (en) * 2001-12-28 2003-07-03 Mcadams Mark Alan Testing of circuit modules embedded in an integrated circuit
US7412639B2 (en) 2002-05-24 2008-08-12 Verigy (Singapore) Pte. Ltd. System and method for testing circuitry on a wafer
JP3898609B2 (ja) * 2002-09-17 2007-03-28 株式会社東芝 半導体集積回路
US7309999B2 (en) * 2002-11-27 2007-12-18 Inapac Technology, Inc. Electronic device having an interface supported testing mode
DE10355116B4 (de) * 2003-11-24 2016-07-14 Infineon Technologies Ag Ein- und Ausgangsschaltung eines integrierten Schaltkreises, Verfahren zum Testen eines integrierten Schaltkreises sowie integrierter Schaltkreis mit einer solchen Ein- und Ausgangsschaltung
EP1797442B1 (en) * 2004-09-27 2009-01-28 Nxp B.V. Integrated circuit with input and/or output bolton pads with integrated logic
JP4103010B2 (ja) 2005-04-01 2008-06-18 セイコーエプソン株式会社 半導体ウエハ
US7375541B1 (en) * 2005-11-08 2008-05-20 Mediatek Inc. Testing method utilizing at least one signal between integrated circuits, and integrated circuit and testing system thereof
US7579689B2 (en) * 2006-01-31 2009-08-25 Mediatek Inc. Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package
JPWO2007097053A1 (ja) * 2006-02-23 2009-07-09 パナソニック株式会社 半導体集積回路とその検査方法
JP4891892B2 (ja) * 2007-12-27 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置とそのテスト方法
US8400181B2 (en) 2010-03-26 2013-03-19 Advanced Micro Devices, Inc. Integrated circuit die testing apparatus and methods
US8648615B2 (en) 2010-06-28 2014-02-11 Xilinx, Inc. Testing die-to-die bonding and rework
KR20120062281A (ko) 2010-12-06 2012-06-14 삼성전자주식회사 관통 전극을 가지는 적층 구조의 반도체 장치 및 이에 대한 테스트 방법
KR20130044048A (ko) 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 반도체 웨이퍼 및 이를 이용한 스택 패키지 제조방법
US20130185608A1 (en) 2012-01-18 2013-07-18 Qualcomm Incorporated Scan chain access in 3d stacked integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004523912A (ja) * 2001-03-02 2004-08-05 クゥアルコム・インコーポレイテッド 混合アナログおよびデジタル集積回路
US6825683B1 (en) * 2002-04-18 2004-11-30 Cypress Semiconductor Corporation System and method for testing multiple integrated circuits that are in the same package
US20050193302A1 (en) * 2004-02-27 2005-09-01 Javier Arguelles Test switching circuit for a high speed data interface
JP2009528535A (ja) * 2006-03-01 2009-08-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｊｔａｇインターフェースを用いた試験アクセス制御回路を有するｉｃ回路
US20130035090A1 (en) * 2011-08-03 2013-02-07 Mehran Moshfeghi Repeater device for reducing the electromagnetic radiation transmitted from cellular phone antennas and extending phone battery life

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020064040A (ja) * 2018-10-18 2020-04-23 普誠科技股▲ふん▼有限公司 集積回路、および、そのテスト方法
JP2020165711A (ja) * 2019-03-28 2020-10-08 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置
JP7316818B2 (ja) 2019-03-28 2023-07-28 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置

Also Published As

Publication number Publication date
CN105705957B (zh) 2018-12-11
WO2015069490A1 (en) 2015-05-14
KR20160083086A (ko) 2016-07-11
WO2015069490A9 (en) 2015-07-02
EP3066485A1 (en) 2016-09-14
US9304163B2 (en) 2016-04-05
US20150123696A1 (en) 2015-05-07
CN105705957A (zh) 2016-06-22

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