KR20160083086A - 집적 회로들을 테스트하기 위한 방법 - Google Patents

집적 회로들을 테스트하기 위한 방법 Download PDF

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Publication number
KR20160083086A
KR20160083086A KR1020167014974A KR20167014974A KR20160083086A KR 20160083086 A KR20160083086 A KR 20160083086A KR 1020167014974 A KR1020167014974 A KR 1020167014974A KR 20167014974 A KR20167014974 A KR 20167014974A KR 20160083086 A KR20160083086 A KR 20160083086A
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KR
South Korea
Prior art keywords
integrated circuit
circuit portion
output
input
test signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167014974A
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English (en)
Korean (ko)
Inventor
사가르 보겔라
데이지 신시아
스리칸트 스리니바산
Original Assignee
퀄컴 인코포레이티드
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Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160083086A publication Critical patent/KR20160083086A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
KR1020167014974A 2013-11-07 2014-10-28 집적 회로들을 테스트하기 위한 방법 Withdrawn KR20160083086A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/074,672 US9304163B2 (en) 2013-11-07 2013-11-07 Methodology for testing integrated circuits
US14/074,672 2013-11-07
PCT/US2014/062538 WO2015069490A1 (en) 2013-11-07 2014-10-28 Methodology for testing integrated circuits

Publications (1)

Publication Number Publication Date
KR20160083086A true KR20160083086A (ko) 2016-07-11

Family

ID=51900523

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167014974A Withdrawn KR20160083086A (ko) 2013-11-07 2014-10-28 집적 회로들을 테스트하기 위한 방법

Country Status (6)

Country Link
US (1) US9304163B2 (cg-RX-API-DMAC7.html)
EP (1) EP3066485A1 (cg-RX-API-DMAC7.html)
JP (1) JP2016536584A (cg-RX-API-DMAC7.html)
KR (1) KR20160083086A (cg-RX-API-DMAC7.html)
CN (1) CN105705957B (cg-RX-API-DMAC7.html)
WO (1) WO2015069490A1 (cg-RX-API-DMAC7.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230076693A (ko) * 2021-11-24 2023-05-31 삼성전자주식회사 전자 장치의 진단 방법 및 장치
KR20230160193A (ko) * 2022-05-16 2023-11-23 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3dic 테스트 및 진단을 위한 래퍼 셀 설계 및 내장형 자체 테스트 아키텍처

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US10559374B2 (en) * 2017-02-20 2020-02-11 Piecemakers Technology, Inc. Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer
TWI686924B (zh) * 2018-10-18 2020-03-01 普誠科技股份有限公司 積體電路及其測試方法
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
JP7316818B2 (ja) * 2019-03-28 2023-07-28 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置
CN115843466B (zh) 2020-07-09 2025-07-15 特克特朗尼克公司 指示制造电子电路的探测目标
CN117269735B (zh) * 2023-11-21 2024-01-23 甘肃送变电工程有限公司 基于电磁微波手段的电力工器具智能电子芯片检测方法
CN118733370B (zh) * 2024-09-02 2024-12-31 深圳市中兴微电子技术有限公司 一种芯粒、芯片及芯片调测方法

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JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
US7161175B2 (en) 1997-09-30 2007-01-09 Jeng-Jye Shau Inter-dice signal transfer methods for integrated circuits
US6472747B2 (en) * 2001-03-02 2002-10-29 Qualcomm Incorporated Mixed analog and digital integrated circuits
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US20030126533A1 (en) * 2001-12-28 2003-07-03 Mcadams Mark Alan Testing of circuit modules embedded in an integrated circuit
US6825683B1 (en) * 2002-04-18 2004-11-30 Cypress Semiconductor Corporation System and method for testing multiple integrated circuits that are in the same package
US7412639B2 (en) 2002-05-24 2008-08-12 Verigy (Singapore) Pte. Ltd. System and method for testing circuitry on a wafer
JP3898609B2 (ja) * 2002-09-17 2007-03-28 株式会社東芝 半導体集積回路
US7309999B2 (en) * 2002-11-27 2007-12-18 Inapac Technology, Inc. Electronic device having an interface supported testing mode
DE10355116B4 (de) * 2003-11-24 2016-07-14 Infineon Technologies Ag Ein- und Ausgangsschaltung eines integrierten Schaltkreises, Verfahren zum Testen eines integrierten Schaltkreises sowie integrierter Schaltkreis mit einer solchen Ein- und Ausgangsschaltung
US7723995B2 (en) * 2004-02-27 2010-05-25 Infineon Technologies Ag Test switching circuit for a high speed data interface
EP1797442B1 (en) * 2004-09-27 2009-01-28 Nxp B.V. Integrated circuit with input and/or output bolton pads with integrated logic
JP4103010B2 (ja) 2005-04-01 2008-06-18 セイコーエプソン株式会社 半導体ウエハ
US7375541B1 (en) * 2005-11-08 2008-05-20 Mediatek Inc. Testing method utilizing at least one signal between integrated circuits, and integrated circuit and testing system thereof
US7579689B2 (en) * 2006-01-31 2009-08-25 Mediatek Inc. Integrated circuit package, and a method for producing an integrated circuit package having two dies with input and output terminals of integrated circuits of the dies directly addressable for testing of the package
JPWO2007097053A1 (ja) * 2006-02-23 2009-07-09 パナソニック株式会社 半導体集積回路とその検査方法
JP2009528535A (ja) * 2006-03-01 2009-08-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｊｔａｇインターフェースを用いた試験アクセス制御回路を有するｉｃ回路
JP4891892B2 (ja) * 2007-12-27 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置とそのテスト方法
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KR20120062281A (ko) 2010-12-06 2012-06-14 삼성전자주식회사 관통 전극을 가지는 적층 구조의 반도체 장치 및 이에 대한 테스트 방법
US9313733B2 (en) * 2011-08-03 2016-04-12 Golba Llc Repeater device for reducing the electromagnetic radiation transmitted from cellular phone antennas and extending phone battery life
KR20130044048A (ko) 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 반도체 웨이퍼 및 이를 이용한 스택 패키지 제조방법
US20130185608A1 (en) 2012-01-18 2013-07-18 Qualcomm Incorporated Scan chain access in 3d stacked integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230076693A (ko) * 2021-11-24 2023-05-31 삼성전자주식회사 전자 장치의 진단 방법 및 장치
KR20230160193A (ko) * 2022-05-16 2023-11-23 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3dic 테스트 및 진단을 위한 래퍼 셀 설계 및 내장형 자체 테스트 아키텍처

Also Published As

Publication number Publication date
CN105705957B (zh) 2018-12-11
WO2015069490A1 (en) 2015-05-14
WO2015069490A9 (en) 2015-07-02
JP2016536584A (ja) 2016-11-24
EP3066485A1 (en) 2016-09-14
US9304163B2 (en) 2016-04-05
US20150123696A1 (en) 2015-05-07
CN105705957A (zh) 2016-06-22

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Date Code Title Description
PA0105 International application

Patent event date: 20160603

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid