JP2008286773A - 混合信号処理回路を有するプローブカードおよび被試験カード - Google Patents
混合信号処理回路を有するプローブカードおよび被試験カード Download PDFInfo
- Publication number
- JP2008286773A JP2008286773A JP2007222461A JP2007222461A JP2008286773A JP 2008286773 A JP2008286773 A JP 2008286773A JP 2007222461 A JP2007222461 A JP 2007222461A JP 2007222461 A JP2007222461 A JP 2007222461A JP 2008286773 A JP2008286773 A JP 2008286773A
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- JP
- Japan
- Prior art keywords
- test
- mixed signal
- generation circuit
- under test
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/3167—Testing of combined analog and digital circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31924—Voltage or current aspects, e.g. driver, receiver
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
【解決手段】混合信号処理回路をテストインターフェースに統合し、特に混合信号処理回路をプローブカードまたは被試験素子カードのテストインターフェースに統合し、かつ混合信号処理回路と試験機のピン電気チャンネルを統合し、混合信号処理回路の動作プロセスを試験機のシステムソフトウェアに統合する。
【選択図】図3
Description
11 金属導線
122 クロック生成回路
124 ロジック信号生成回路
126 混合信号生成回路
13 ピン電気チャンネル
14 被試験素子テストインターフェース
15 被試験混合信号素子
16 ソケット
20 試験機
22 被試験混合信号モジュール
222 クロック生成回路
224 ロジック信号生成回路
226 クロック信号
228 デジタル信号
24 被試験素子テストインターフェース
242 ピン電気チャンネル
244 電気コネクタ
246 混合信号生成回路
248 被試験混合信号素子
Claims (1)
- 被試験素子と電気的に接続するために用いられる電気コネクタと、
前記テストインターフェース上に配置される複数の混合信号生成回路と、
前記テストインターフェース上に配置され、前記電気コネクタおよび前記複数の混合信号生成回路と電気的に接続する複数のピン電気チャンネルと、を含む、
混合信号素子テスト装置のテストインターフェース。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096117692A TWI338149B (en) | 2007-05-18 | 2007-05-18 | An under testing device interface with mixed-signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008286773A true JP2008286773A (ja) | 2008-11-27 |
Family
ID=40026879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007222461A Pending JP2008286773A (ja) | 2007-05-18 | 2007-08-29 | 混合信号処理回路を有するプローブカードおよび被試験カード |
Country Status (3)
Country | Link |
---|---|
US (1) | US7688087B2 (ja) |
JP (1) | JP2008286773A (ja) |
TW (1) | TWI338149B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI398649B (zh) * | 2009-02-11 | 2013-06-11 | King Yuan Electronics Co Ltd | Semiconductor test system with self - test for electrical channel |
US10296433B2 (en) * | 2012-06-01 | 2019-05-21 | Litepoint Corporation | Method for transferring and confirming transfer of predefined data to a device under test (DUT) during a test sequence |
US9372227B2 (en) * | 2013-03-11 | 2016-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit test system and method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002162450A (ja) * | 2000-11-22 | 2002-06-07 | Mitsubishi Electric Corp | 半導体集積回路の試験装置および半導体集積回路の試験方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4806852A (en) * | 1984-09-07 | 1989-02-21 | Megatest Corporation | Automatic test system with enhanced performance of timing generators |
US5095483A (en) * | 1989-04-28 | 1992-03-10 | International Business Machines Corporation | Signature analysis in physical modeling |
US5909186A (en) * | 1997-07-01 | 1999-06-01 | Vlsi Technology Gmbh | Methods and apparatus for testing analog-to-digital and digital-to-analog device using digital testers |
US6005408A (en) * | 1997-07-31 | 1999-12-21 | Credence Systems Corporation | System for compensating for temperature induced delay variation in an integrated circuit |
JP2000292504A (ja) * | 1999-04-02 | 2000-10-20 | Mitsubishi Electric Corp | Lsiテスタ |
TW495616B (en) * | 1999-04-06 | 2002-07-21 | Advantest Corp | Test device and method for electrically testing electronic device |
JP2002236152A (ja) * | 2001-02-08 | 2002-08-23 | Mitsubishi Electric Corp | 半導体集積回路の試験装置及び試験方法 |
-
2007
- 2007-05-18 TW TW096117692A patent/TWI338149B/zh active
- 2007-08-29 JP JP2007222461A patent/JP2008286773A/ja active Pending
- 2007-11-05 US US11/979,511 patent/US7688087B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002162450A (ja) * | 2000-11-22 | 2002-06-07 | Mitsubishi Electric Corp | 半導体集積回路の試験装置および半導体集積回路の試験方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI338149B (en) | 2011-03-01 |
US7688087B2 (en) | 2010-03-30 |
TW200846684A (en) | 2008-12-01 |
US20080284454A1 (en) | 2008-11-20 |
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