JP2016174170A5 - - Google Patents

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Publication number
JP2016174170A5
JP2016174170A5 JP2016095168A JP2016095168A JP2016174170A5 JP 2016174170 A5 JP2016174170 A5 JP 2016174170A5 JP 2016095168 A JP2016095168 A JP 2016095168A JP 2016095168 A JP2016095168 A JP 2016095168A JP 2016174170 A5 JP2016174170 A5 JP 2016174170A5
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JP
Japan
Prior art keywords
insulating layer
layer
circuit
soi structure
passive
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JP2016095168A
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English (en)
Japanese (ja)
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JP2016174170A (ja
JP6099794B2 (ja
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Priority claimed from US13/356,717 external-priority patent/US9496255B2/en
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Publication of JP2016174170A publication Critical patent/JP2016174170A/ja
Publication of JP2016174170A5 publication Critical patent/JP2016174170A5/ja
Application granted granted Critical
Publication of JP6099794B2 publication Critical patent/JP6099794B2/ja
Expired - Fee Related legal-status Critical Current
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JP2016095168A 2011-11-16 2016-05-11 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法 Expired - Fee Related JP6099794B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US61/560,471 2011-11-16
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US13/356,717 2012-01-24

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2014542512A Division JP5937225B2 (ja) 2011-11-16 2012-11-16 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法

Publications (3)

Publication Number Publication Date
JP2016174170A JP2016174170A (ja) 2016-09-29
JP2016174170A5 true JP2016174170A5 (enExample) 2017-02-09
JP6099794B2 JP6099794B2 (ja) 2017-03-22

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JP2014542512A Active JP5937225B2 (ja) 2011-11-16 2012-11-16 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法
JP2016095168A Expired - Fee Related JP6099794B2 (ja) 2011-11-16 2016-05-11 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法

Family Applications Before (1)

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JP2014542512A Active JP5937225B2 (ja) 2011-11-16 2012-11-16 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法

Country Status (7)

Country Link
US (1) US9496255B2 (enExample)
EP (1) EP2780942A1 (enExample)
JP (2) JP5937225B2 (enExample)
KR (2) KR101759689B1 (enExample)
CN (1) CN104054175B (enExample)
IN (1) IN2014MN01027A (enExample)
WO (1) WO2013075007A1 (enExample)

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WO2017142849A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
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JP7002456B2 (ja) 2016-03-07 2022-01-20 グローバルウェーハズ カンパニー リミテッド 低温流動性酸化物層を含む半導体オンインシュレータ構造およびその製造方法
US11848227B2 (en) 2016-03-07 2023-12-19 Globalwafers Co., Ltd. Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
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