CN104054175B - 具有绝缘层和二级层的层叠芯片组及其形成方法 - Google Patents

具有绝缘层和二级层的层叠芯片组及其形成方法 Download PDF

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Publication number
CN104054175B
CN104054175B CN201280067053.4A CN201280067053A CN104054175B CN 104054175 B CN104054175 B CN 104054175B CN 201280067053 A CN201280067053 A CN 201280067053A CN 104054175 B CN104054175 B CN 104054175B
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insulating barrier
layer
circuit layer
silicon
semiconductor layer
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Chinese (zh)
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CN104054175A (zh
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C·左
C·尹
S-J·朴
C·S·罗
M·F·维伦茨
J·金
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Micromachines (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
CN201280067053.4A 2011-11-16 2012-11-16 具有绝缘层和二级层的层叠芯片组及其形成方法 Active CN104054175B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US61/560,471 2011-11-16
US13/356,717 2012-01-24
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
PCT/US2012/065644 WO2013075007A1 (en) 2011-11-16 2012-11-16 Stacked chipset having an insulating layer and a secondary layer and method of forming same

Publications (2)

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CN104054175A CN104054175A (zh) 2014-09-17
CN104054175B true CN104054175B (zh) 2018-03-06

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US (1) US9496255B2 (enExample)
EP (1) EP2780942A1 (enExample)
JP (2) JP5937225B2 (enExample)
KR (2) KR20140100526A (enExample)
CN (1) CN104054175B (enExample)
IN (1) IN2014MN01027A (enExample)
WO (1) WO2013075007A1 (enExample)

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JP6881066B2 (ja) * 2017-06-19 2021-06-02 大日本印刷株式会社 貫通電極基板および貫通電極基板の製造方法
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Also Published As

Publication number Publication date
US9496255B2 (en) 2016-11-15
CN104054175A (zh) 2014-09-17
KR101759689B1 (ko) 2017-07-19
KR20160044591A (ko) 2016-04-25
IN2014MN01027A (enExample) 2015-05-01
JP6099794B2 (ja) 2017-03-22
JP5937225B2 (ja) 2016-06-22
EP2780942A1 (en) 2014-09-24
KR20140100526A (ko) 2014-08-14
US20130120951A1 (en) 2013-05-16
JP2016174170A (ja) 2016-09-29
WO2013075007A1 (en) 2013-05-23
JP2015503228A (ja) 2015-01-29

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