CN104054175B - 具有绝缘层和二级层的层叠芯片组及其形成方法 - Google Patents

具有绝缘层和二级层的层叠芯片组及其形成方法 Download PDF

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Publication number
CN104054175B
CN104054175B CN201280067053.4A CN201280067053A CN104054175B CN 104054175 B CN104054175 B CN 104054175B CN 201280067053 A CN201280067053 A CN 201280067053A CN 104054175 B CN104054175 B CN 104054175B
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insulating barrier
layer
circuit layer
silicon
semiconductor layer
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CN104054175A (zh
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C·左
C·尹
S-J·朴
C·S·罗
M·F·维伦茨
J·金
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
CN201280067053.4A 2011-11-16 2012-11-16 具有绝缘层和二级层的层叠芯片组及其形成方法 Active CN104054175B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US61/560,471 2011-11-16
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US13/356,717 2012-01-24
PCT/US2012/065644 WO2013075007A1 (en) 2011-11-16 2012-11-16 Stacked chipset having an insulating layer and a secondary layer and method of forming same

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CN104054175A CN104054175A (zh) 2014-09-17
CN104054175B true CN104054175B (zh) 2018-03-06

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US (1) US9496255B2 (enExample)
EP (1) EP2780942A1 (enExample)
JP (2) JP5937225B2 (enExample)
KR (2) KR101759689B1 (enExample)
CN (1) CN104054175B (enExample)
IN (1) IN2014MN01027A (enExample)
WO (1) WO2013075007A1 (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104058363B (zh) * 2013-03-22 2016-01-20 上海丽恒光微电子科技有限公司 基于mems透射光阀的显示装置及其形成方法
US9418985B2 (en) * 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
US9032353B2 (en) 2013-10-10 2015-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for three-dimensional layout design of integrated circuit elements in stacked CMOS
US9257407B2 (en) * 2013-10-28 2016-02-09 Qualcomm Incorporated Heterogeneous channel material integration into wafer
US9443758B2 (en) * 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
WO2015112308A1 (en) 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
US9786613B2 (en) * 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
US20160043108A1 (en) * 2014-08-07 2016-02-11 Silanna Semiconductor U.S.A., Inc. Semiconductor Structure with Multiple Active Layers in an SOI Wafer
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
WO2016081363A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A system-on-chip on a semiconductor-on-insulator wafer and a method of manufacturing
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
US10483152B2 (en) 2014-11-18 2019-11-19 Globalwafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
EP4120320A1 (en) 2015-03-03 2023-01-18 GlobalWafers Co., Ltd. Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
CN107408532A (zh) 2015-03-17 2017-11-28 太阳能爱迪生半导体有限公司 用于绝缘体上半导体结构的制造的热稳定电荷捕获层
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
US10332782B2 (en) 2015-06-01 2019-06-25 Globalwafers Co., Ltd. Method of manufacturing silicon germanium-on-insulator
US10304722B2 (en) 2015-06-01 2019-05-28 Globalwafers Co., Ltd. Method of manufacturing semiconductor-on-insulator
US20160379943A1 (en) * 2015-06-25 2016-12-29 Skyworks Solutions, Inc. Method and apparatus for high performance passive-active circuit integration
WO2017019676A1 (en) * 2015-07-28 2017-02-02 Skyworks Solutions, Inc. Integrated passive device on soi substrate
US9768109B2 (en) * 2015-09-22 2017-09-19 Qualcomm Incorporated Integrated circuits (ICS) on a glass substrate
JP6585978B2 (ja) * 2015-09-24 2019-10-02 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
CN117198983A (zh) 2015-11-20 2023-12-08 环球晶圆股份有限公司 使半导体表面平整的制造方法
US10256863B2 (en) * 2016-01-11 2019-04-09 Qualcomm Incorporated Monolithic integration of antenna switch and diplexer
US10468294B2 (en) 2016-02-19 2019-11-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
WO2017142849A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a buried high resistivity layer
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
EP3758050A1 (en) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
WO2017155808A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
WO2017214084A1 (en) 2016-06-08 2017-12-14 Sunedison Semiconductor Limited High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
US20180068886A1 (en) * 2016-09-02 2018-03-08 Qualcomm Incorporated Porous semiconductor layer transfer for an integrated circuit structure
US9812580B1 (en) * 2016-09-06 2017-11-07 Qualcomm Incorporated Deep trench active device with backside body contact
SG11201903090SA (en) 2016-10-26 2019-05-30 Globalwafers Co Ltd High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
JP6801105B2 (ja) 2016-12-05 2020-12-16 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 高抵抗シリコンオンインシュレータ構造及びその製造方法
SG10201913071XA (en) 2016-12-28 2020-03-30 Sunedison Semiconductor Ltd Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield
JP6881066B2 (ja) * 2017-06-19 2021-06-02 大日本印刷株式会社 貫通電極基板および貫通電極基板の製造方法
JP7034186B2 (ja) 2017-07-14 2022-03-11 サンエディソン・セミコンダクター・リミテッド 絶縁体上半導体構造の製造方法
JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
JP2019212729A (ja) * 2018-06-04 2019-12-12 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP7123182B2 (ja) 2018-06-08 2022-08-22 グローバルウェーハズ カンパニー リミテッド シリコン箔層の移転方法
FR3091004B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences
EP3675168A1 (en) * 2018-12-24 2020-07-01 IMEC vzw 3d power semiconductor device and system
JP2020141090A (ja) * 2019-03-01 2020-09-03 ソニーセミコンダクタソリューションズ株式会社 容量素子、半導体素子基板及び電子機器
KR102804065B1 (ko) 2020-07-13 2025-05-09 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN114122134B (zh) * 2020-09-01 2023-12-22 苏州华太电子技术股份有限公司 一种射频ldmos集成器件
DE102022211198A1 (de) * 2022-10-21 2024-05-02 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines mikromechanischen Bauelements

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399997B1 (en) * 2000-08-01 2002-06-04 Megic Corporation High performance system-on-chip using post passivation process and glass substrates

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102523A (ja) 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
JP4244120B2 (ja) 2001-06-20 2009-03-25 株式会社半導体エネルギー研究所 発光装置及びその作製方法
TW548860B (en) 2001-06-20 2003-08-21 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
US7402897B2 (en) 2002-08-08 2008-07-22 Elm Technology Corporation Vertical system integration
JP2004165269A (ja) 2002-11-11 2004-06-10 Canon Inc 積層形半導体装置
JP2004349513A (ja) 2003-05-22 2004-12-09 Seiko Epson Corp 薄膜回路装置及びその製造方法、並びに電気光学装置、電子機器
CN101714512B (zh) * 2004-08-20 2012-10-10 佐伊科比株式会社 具有三维层叠结构的半导体器件的制造方法
US7179719B2 (en) 2004-09-28 2007-02-20 Sharp Laboratories Of America, Inc. System and method for hydrogen exfoliation
US20070207592A1 (en) 2006-03-03 2007-09-06 Lu James J Wafer bonding of damascene-patterned metal/adhesive redistribution layers
US7408798B2 (en) 2006-03-31 2008-08-05 International Business Machines Corporation 3-dimensional integrated circuit architecture, structure and method for fabrication thereof
US20080128901A1 (en) * 2006-11-30 2008-06-05 Peter Zurcher Micro-electro-mechanical systems device and integrated circuit device integrated in a three-dimensional semiconductor structure
US20080149832A1 (en) * 2006-12-20 2008-06-26 Miguel Zorn Scanning Probe Microscope, Nanomanipulator with Nanospool, Motor, nucleotide cassette and Gaming application
JP2009067098A (ja) 2007-09-10 2009-04-02 Harison Toshiba Lighting Corp 照明装置
JP2009267098A (ja) * 2008-04-25 2009-11-12 Denso Corp 半導体装置及びその製造方法
US7943428B2 (en) * 2008-12-24 2011-05-17 International Business Machines Corporation Bonded semiconductor substrate including a cooling mechanism
US7943423B2 (en) 2009-03-10 2011-05-17 Infineon Technologies Ag Reconfigured wafer alignment
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
JP2011029609A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法およびｓｏｉ基板
US9076664B2 (en) * 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399997B1 (en) * 2000-08-01 2002-06-04 Megic Corporation High performance system-on-chip using post passivation process and glass substrates

Also Published As

Publication number Publication date
US9496255B2 (en) 2016-11-15
KR20160044591A (ko) 2016-04-25
CN104054175A (zh) 2014-09-17
JP2015503228A (ja) 2015-01-29
WO2013075007A1 (en) 2013-05-23
EP2780942A1 (en) 2014-09-24
JP6099794B2 (ja) 2017-03-22
JP5937225B2 (ja) 2016-06-22
US20130120951A1 (en) 2013-05-16
IN2014MN01027A (enExample) 2015-05-01
JP2016174170A (ja) 2016-09-29
KR101759689B1 (ko) 2017-07-19
KR20140100526A (ko) 2014-08-14

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