KR20140100526A - 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 - Google Patents

절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 Download PDF

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Publication number
KR20140100526A
KR20140100526A KR1020147016198A KR20147016198A KR20140100526A KR 20140100526 A KR20140100526 A KR 20140100526A KR 1020147016198 A KR1020147016198 A KR 1020147016198A KR 20147016198 A KR20147016198 A KR 20147016198A KR 20140100526 A KR20140100526 A KR 20140100526A
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South Korea
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chipset
layer
insulating layer
circuit
silicon substrate
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Korean (ko)
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쳉지에 주오
창한 윤
상준 박
치 ? 로
마리오 에프. 베레즈
종해 김
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퀄컴 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Micromachines (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
KR1020147016198A 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법 Ceased KR20140100526A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US61/560,471 2011-11-16
US13/356,717 2012-01-24
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
PCT/US2012/065644 WO2013075007A1 (en) 2011-11-16 2012-11-16 Stacked chipset having an insulating layer and a secondary layer and method of forming same

Related Child Applications (1)

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KR1020167009373A Division KR101759689B1 (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법

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KR20140100526A true KR20140100526A (ko) 2014-08-14

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KR1020147016198A Ceased KR20140100526A (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법
KR1020167009373A Expired - Fee Related KR101759689B1 (ko) 2011-11-16 2012-11-16 절연층 및 보조층을 갖는 적층 칩셋 및 이를 형성하는 방법

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Country Status (7)

Country Link
US (1) US9496255B2 (enExample)
EP (1) EP2780942A1 (enExample)
JP (2) JP5937225B2 (enExample)
KR (2) KR20140100526A (enExample)
CN (1) CN104054175B (enExample)
IN (1) IN2014MN01027A (enExample)
WO (1) WO2013075007A1 (enExample)

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JP6831911B2 (ja) 2016-10-26 2021-02-17 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板
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KR102306730B1 (ko) 2016-12-28 2021-09-30 썬에디슨 세미컨덕터 리미티드 고유 게터링 및 게이트 산화물 무결성 수율을 갖도록 규소 웨이퍼들을 처리하는 방법
JP6881066B2 (ja) * 2017-06-19 2021-06-02 大日本印刷株式会社 貫通電極基板および貫通電極基板の製造方法
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Also Published As

Publication number Publication date
EP2780942A1 (en) 2014-09-24
CN104054175A (zh) 2014-09-17
JP6099794B2 (ja) 2017-03-22
US20130120951A1 (en) 2013-05-16
WO2013075007A1 (en) 2013-05-23
JP2015503228A (ja) 2015-01-29
JP5937225B2 (ja) 2016-06-22
IN2014MN01027A (enExample) 2015-05-01
CN104054175B (zh) 2018-03-06
KR20160044591A (ko) 2016-04-25
JP2016174170A (ja) 2016-09-29
KR101759689B1 (ko) 2017-07-19
US9496255B2 (en) 2016-11-15

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