JP2016066789A - 配線基板の製造方法、および半導体パッケージの製造方法 - Google Patents

配線基板の製造方法、および半導体パッケージの製造方法 Download PDF

Info

Publication number
JP2016066789A
JP2016066789A JP2015180837A JP2015180837A JP2016066789A JP 2016066789 A JP2016066789 A JP 2016066789A JP 2015180837 A JP2015180837 A JP 2015180837A JP 2015180837 A JP2015180837 A JP 2015180837A JP 2016066789 A JP2016066789 A JP 2016066789A
Authority
JP
Japan
Prior art keywords
resist layer
opening
solder resist
conductive pattern
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015180837A
Other languages
English (en)
Japanese (ja)
Inventor
宙 早井
Chiyuu Hayai
宙 早井
元 山戸
Hajime Yamato
元 山戸
猛 八月朔日
Takeshi Hozumi
猛 八月朔日
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Publication of JP2016066789A publication Critical patent/JP2016066789A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
JP2015180837A 2014-09-19 2015-09-14 配線基板の製造方法、および半導体パッケージの製造方法 Pending JP2016066789A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014190828 2014-09-19
JP2014190828 2014-09-19

Publications (1)

Publication Number Publication Date
JP2016066789A true JP2016066789A (ja) 2016-04-28

Family

ID=55661999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015180837A Pending JP2016066789A (ja) 2014-09-19 2015-09-14 配線基板の製造方法、および半導体パッケージの製造方法

Country Status (3)

Country Link
JP (1) JP2016066789A (ko)
KR (1) KR20160034214A (ko)
TW (1) TW201631673A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017212429A (ja) * 2017-01-20 2017-11-30 住友ベークライト株式会社 樹脂シートおよび回路基板
WO2018088345A1 (ja) * 2016-11-11 2018-05-17 住友ベークライト株式会社 金属箔付き樹脂膜、構造体、配線基板の製造方法、半導体装置の製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102039711B1 (ko) * 2018-03-13 2019-11-01 삼성전자주식회사 팬-아웃 부품 패키지
CN108770226B (zh) * 2018-05-15 2020-07-03 惠州市金百泽电路科技有限公司 一种线路板阻焊侧蚀位置渗金短路预防加工方法
TWI745162B (zh) 2020-11-12 2021-11-01 力成科技股份有限公司 半導體封裝結構

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018088345A1 (ja) * 2016-11-11 2018-05-17 住友ベークライト株式会社 金属箔付き樹脂膜、構造体、配線基板の製造方法、半導体装置の製造方法
JPWO2018088345A1 (ja) * 2016-11-11 2018-11-08 住友ベークライト株式会社 金属箔付き樹脂膜、構造体、配線基板の製造方法、半導体装置の製造方法
JP2017212429A (ja) * 2017-01-20 2017-11-30 住友ベークライト株式会社 樹脂シートおよび回路基板

Also Published As

Publication number Publication date
TW201631673A (zh) 2016-09-01
KR20160034214A (ko) 2016-03-29

Similar Documents

Publication Publication Date Title
TWI494337B (zh) 電路基板用環氧樹脂組成物，預浸體，積層板，樹脂片，印刷佈線板用積層基材，印刷佈線板及半導體裝置
JP7258453B2 (ja) 熱硬化性樹脂組成物、キャリア付樹脂膜、プリプレグ、プリント配線基板および半導体装置
JP5263374B2 (ja) 配線基板及び半導体装置並びに配線基板の製造方法
JP2016066789A (ja) 配線基板の製造方法、および半導体パッケージの製造方法
WO2017038713A1 (ja) プリント配線板の製造方法、半導体装置の製造方法
US7981963B2 (en) Insulation material of reactive elastomer, epoxy resin, curing agent and crosslinked rubber
JP6932475B2 (ja) 有機樹脂基板の製造方法、有機樹脂基板および半導体装置
WO2018088345A1 (ja) 金属箔付き樹脂膜、構造体、配線基板の製造方法、半導体装置の製造方法
JP7225553B2 (ja) ソルダーレジスト形成用の樹脂シート
JP6409390B2 (ja) 配線基板、半導体パッケージ、電子装置、配線基板の製造方法、および半導体パッケージの製造方法
JP2020132646A (ja) 樹脂組成物、それを用いたキャリア付樹脂膜、プリプレグ、積層板、プリント配線基板および半導体装置
JP6217870B2 (ja) 構造体、配線基板および配線基板の製造方法
JP6439960B2 (ja) 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP6107992B1 (ja) 樹脂シート
JP6413437B2 (ja) 配線基板の製造方法、および半導体パッケージの製造方法
JP4385555B2 (ja) インターポーザ、半導体パッケージおよびその製造方法
TW201718798A (zh) 樹脂片材及電子裝置
JP7240085B2 (ja) 熱硬化性樹脂組成物、キャリア付樹脂膜、プリプレグ、プリント配線基板および半導体装置
JP2019204974A (ja) 有機樹脂基板の製造方法、有機樹脂基板および半導体装置
JP2019033205A (ja) 配線基板の製造方法、半導体装置の製造方法
JP5353547B2 (ja) 金属箔付きプリプレグ、積層板およびインターポーザ
JP2017212429A (ja) 樹脂シートおよび回路基板
JP2019095719A (ja) 配線基板の製造方法、半導体装置の製造方法
JP2019033206A (ja) 配線基板の製造方法、半導体装置の製造方法
JP2017212400A (ja) 樹脂シートおよび回路基板