JP2016066789A - Wiring board manufacturing method and semiconductor package manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board manufacturing method which can manufacture a semiconductor package which does not cause under etching and which is excellent in connection reliability, with high yield; and provide a manufacturing method of a semiconductor package excellent in connection reliability.SOLUTION: A wiring board manufacturing method comprises in the following order: a process (S102) of preparing a structure 1000 which has a substrate 22 having a conductive pattern 24 on at least one surface and a solder resist layer 10 laminated on the substrate 22 so as to cover the conductive pattern 24; and a process (S104) of forming an opening 28 for exposing a part of the conductive pattern 24 in a predetermined region of the solder resist layer 10. The process of forming the opening 28 includes a process of performing sandblasting on a region of the solder resist layer 10 where the opening 28 is to be formed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a wiring board and a method for manufacturing a semiconductor package.

  A process described in the following document is known as a process for forming an opening in a pad portion in the outermost layer of a semiconductor element.

Patent Document 1 describes the following process.
First, a solder resist layer is formed using the photosensitive resin composition. Next, a solder resist layer is laminated on the substrate so as to cover the surface of the conductive pad formed on the substrate. Next, it exposes using the mask with the pattern which the said conductive pad exposes, and forms an opening part in a soldering resist layer. Thereafter, the resin residue (smear) adhering to the exposed conductive pad surface is removed by performing desmear treatment and plasma treatment in this order. Subsequently, solder bumps and bonding wires are connected to the exposed conductive pads.

Patent Document 2 describes the following process.
First, a solder resist layer is formed using a thermosetting resin composition. Next, a solder resist layer is laminated on the substrate so as to cover the surface of the conductive pad formed on the substrate. Next, for example, a carbon dioxide gas laser is irradiated to the solder resist layer so that the conductive pad is exposed to form an opening. Thereafter, the resin residue (smear) adhering to the exposed conductive pad surface is removed by performing desmear treatment and plasma treatment in this order. Subsequently, solder bumps and bonding wires are connected to the exposed conductive pads.

JP 2014-115672 A JP 2013-129170 A

  However, the process described in Patent Document 1 has the following technical problems. That is, in the manufacturing process described in Patent Document 1 in which a solder resist layer is formed using a photosensitive resin composition, as shown in FIG. 10, when an opening is formed in the solder resist layer 10, the solder resist layer is formed. There is a possibility that a phenomenon called under-etching occurs in which a portion existing on the side of the conductive pad (conductive pattern 24) of the layer 10 is eroded. That is, the manufacturing process described in Patent Document 1 has a problem that the opening is enlarged due to under-etching.

  On the other hand, the process described in Patent Document 2 has the following technical problems, although the above-described problem of under-etching can be solved. That is, when forming the opening in the solder resist layer, it has been difficult to efficiently and uniformly remove the solder resist layer in a short time so that the upper surface of the conductive pad is exposed to the opening. The semiconductor package obtained by the manufacturing process described in Patent Document 2 has room for improvement in terms of connection reliability between a conductive pad and a solder bump or bonding wire formed on the conductive pad. It was. That is, the manufacturing process described in Patent Document 2 has a problem that the yield of a semiconductor package having excellent connection reliability is not sufficiently improved.

  In view of the above, an object of the present invention is to provide a method of manufacturing a wiring board that can produce a semiconductor package having excellent connection reliability without generating under-etching with high yield. Another object of the present invention is to provide a method for manufacturing a semiconductor package having excellent connection reliability.

According to the present invention,
Preparing a structure having a substrate having a conductive pattern on at least one surface and a solder resist layer laminated on the substrate so as to cover the conductive pattern;
Forming an opening in the solder resist layer to expose a part of the conductive pattern;
In this order,
The step of forming the opening is provided with a method for manufacturing a wiring board, including a process of performing a sandblasting process on a region of the solder resist layer where the opening is to be formed.

Furthermore, according to the present invention,
Preparing a structure having a substrate having a conductive pattern on at least one surface and a solder resist layer laminated on the substrate so as to cover the conductive pattern;
Forming an opening in the solder resist layer to expose a part of the conductive pattern;
On the exposed conductive pattern, a step of melting and fusing solder bumps or ends of bonding wires;
In this order,
There is provided a method for manufacturing a semiconductor package, wherein the step of forming the opening includes a process of performing a sandblasting process on a region of the solder resist layer where the opening is to be formed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the wiring board which can produce the semiconductor package excellent in connection reliability without generating under-etching with a sufficient yield can be provided. In addition, a method for manufacturing a semiconductor package having excellent connection reliability can be provided.

It is a flowchart which shows an example of the flow of the manufacturing method of the wiring board which concerns on this embodiment. 2A and 2B are schematic views showing an example of a method for manufacturing a wiring board according to the present embodiment. 3A and 3B are schematic views showing an example of a method for manufacturing a wiring board according to the present embodiment. It is an expansion schematic diagram of the opening vicinity vicinity formed in the soldering resist layer of the wiring board which concerns on this embodiment. FIG. 4A is a schematic plan view in the vicinity of the opening, and FIG. 4B is a schematic cross-sectional view in the vicinity of the opening. It is sectional drawing which shows typically the example of the surface form of the soldering resist layer which concerns on this embodiment. It is a schematic diagram which shows the example of the structure of the wiring board which concerns on this embodiment. It is a cross-sectional schematic diagram which shows an example of the structure of the semiconductor package which concerns on this embodiment. It is a cross-sectional schematic diagram which shows an example of the structure of the electronic device which concerns on this embodiment. 9A to 9C are schematic views illustrating an example of a method for manufacturing a wiring board according to the present embodiment. It is an expanded sectional view of the wiring board for demonstrating the conventional manufacturing process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

<< First Embodiment >>
<Method for Manufacturing Wiring Board 20>
FIG. 1 is a flowchart showing an example of the flow of a method for manufacturing the wiring board 20 according to the present embodiment. 2 (FIGS. 2A and 2B) and FIG. 3 (FIGS. 3A and 3B) are schematic views showing an example of a method for manufacturing the wiring board 20 according to the present embodiment.
As shown in FIG. 1, the method of manufacturing the wiring board 20 according to the present embodiment includes a step of preparing the structure 1000 (S102) and a step of forming the opening 28 in the solder resist layer 10 (S104). In order.

In the step of preparing the structure 1000 (S102), the structure 1000 having the substrate 22 having the conductive pattern 24 on at least one surface and the solder resist layer 10 laminated on the substrate 22 so as to cover the conductive pattern 24. Prepare. In this embodiment, the solder resist layer 10 is positioned (stacked) on the outermost side of the structure 1000 (see FIG. 2B).
In the step of forming the opening 28 in the solder resist layer 10 (S104), the opening 28 that exposes a part of the conductive pattern 24 is formed in the solder resist layer 10. And this process (S104) includes the process of performing a sandblast process to the predetermined area | region which should form the opening part 28 of the soldering resist layer 10. FIG. By this process, the solder resist layer 10 can be efficiently and uniformly removed in a short time without causing under-etching. Thereby, the upper surface of the conductive pattern 24 can be reliably exposed to the opening 28. Therefore, according to the manufacturing method according to the present embodiment, it is possible to manufacture the semiconductor package 102 (see FIG. 7) excellent in connection reliability with a higher yield than the conventional manufacturing processes described in Patent Documents 1 and 2. The wiring board 20 can be obtained.

  Furthermore, according to the manufacturing method according to the present embodiment, a plurality of openings 28 may be formed as shown in FIG. According to the manufacturing method concerning this embodiment, the opening shape of each opening part 28 can be reliably formed in a desired shape without variation. In particular, it is possible to reliably prevent variations in the opening shape and the opening depth between the plurality of opening portions 28 to be formed in the same shape. Therefore, the upper surface of the conductive pattern 24 can be exposed to the opening 28 in all the openings 28 to be formed.

  Next, with reference to FIGS. 1-3, the manufacturing method of the wiring board 20 which concerns on this embodiment is demonstrated in detail.

First, in the step of preparing the structure 1000 (S102), the substrate 22 having the conductive pattern 24 provided on at least one of the outermost surfaces of the front and back surfaces is prepared. As shown in FIG. 2A, in the present embodiment, a double-sided substrate 22 having conductive patterns 24 formed on both sides is used. Here, the substrate 22 may be a core substrate or a coreless substrate.
Hereinafter, the manufacturing method according to the present embodiment will be described by taking the case where the substrate 22 is a core substrate as an example.

As shown in FIG. 2B, the solder resist layer 10 is laminated on the conductive pattern 24 so as to cover the conductive pattern 24 of the substrate 22. Specifically, a varnish-like thermosetting resin composition (P) (solder resist), which will be described later, is applied on the outermost surface provided with the conductive pattern 24. Thereafter, the applied solder resist is dried to form the solder resist layer 10. As described above, the structure 1000 is manufactured in the manufacturing method according to the present embodiment.
Although the film thickness of the soldering resist layer 10 is not specifically limited, For example, it can be set as 5 micrometers or more and 300 micrometers or less.

  Next, as shown in FIG. 3A, an opening 28 for exposing a part of the conductive pattern 24 is formed in a predetermined region of the solder resist layer 10. Specifically, the opening 28 is formed in a predetermined region of the solder resist layer 10 so as to expose the land 244 of the conductive pattern 24. According to the manufacturing method according to the present embodiment, when the opening 28 is formed, it is important to perform a sandblasting process on a predetermined region in the solder resist layer 10 where the opening 28 is to be formed. By doing so, the solder resist layer 10 can be efficiently and uniformly removed in a short time so that under etching does not occur and the upper surface of the conductive pattern 24 is exposed to the opening 28.

Usually, in this sandblasting process, a resist mask (not shown) for sandblasting is provided on the solder resist layer 10 to perform the process. Thereby, it is possible to prevent polishing (cutting) of a region other than the region where the opening 28 of the solder resist layer 10 is to be formed (hereinafter simply referred to as “protective region”) by the sandblasting process.
The resist mask can be provided on the solder resist layer 10 by using a method as described in the following (I) or (II), for example. In the method (I), a photoresist film (dry film) having an opening pattern corresponding to the opening 28 of the solder resist layer 10 is prepared in advance, and the photoresist film is pressure-bonded to the solder resist layer 10. In the method (II), after a liquid photoresist material is applied onto the solder resist layer 10 and dried to form a film, the film is exposed and developed, and then the solder resist layer 10 An opening pattern corresponding to the opening 28 is formed.

As a constituent material of such a resist mask, a positive or negative photoresist material can be used.
Although it does not specifically limit as a photoresist material, The photosensitive resin composition containing various photosensitive resins, such as a photosensitive acrylic resin, a photosensitive urethane resin, a photosensitive phenol resin, and a photosensitive polyimide, is mentioned. Among these photosensitive resins, it is particularly preferable to use a photosensitive acrylic resin. Since the photosensitive acrylic resin has excellent moldability, a resist mask having a high resolution of the pattern to be formed can be obtained. Further, such a photosensitive acrylic resin is relatively inexpensive and can easily form a pattern, so that the manufacturing cost of the resist mask can be kept low.

  The thickness of the photoresist film forming the resist mask is not particularly limited, but is preferably 15 μm or more and less than 50 μm, more preferably 15 μm or more and 40 μm or less, and further preferably 20 μm or more and 30 μm or less. If the thickness of the photoresist film is within the above range, a resist mask with higher resolution can be easily formed by exposure and development. In particular, such a relatively thin resist mask can be easily formed by using a photosensitive acrylic resin.

  Although the effect obtained by using the sandblasting will be described later, when the solder bump 30 or the bonding wire 50 is connected to the conductive pattern 24 in a later step, the conductive pattern 24 and the solder bump 30 or the bonding wire 50 The connection relationship can be strengthened. In this case, even when an impact is applied when manufacturing the wiring substrate 20 or the semiconductor package 102, it is possible to realize high adhesion without causing the fine circuit (conductive pattern 24) on the substrate to peel off from the substrate 22. it can.

  Here, the sandblasting process according to the present embodiment refers to a technique of polishing a corresponding portion by spraying particles having an average particle diameter (D50) of 1 μm or more and 70 μm or less, for example. In general, in the sandblast treatment, by increasing the particle size of the particles to be sprayed, the force (polishing power) for polishing the corresponding portion is increased. Therefore, by increasing the particle size of the particles to be sprayed by the sand blasting process, the corresponding portion can be polished to a predetermined depth in a short time. On the other hand, by reducing the particle size of the particles to be sprayed, the depth of the opening 28 to be polished and the shape of the side wall portion defining the opening 28 can be controlled with high accuracy. That is, the opening 28 can be formed with high polishing accuracy (processing accuracy).

  In the manufacturing method according to the present embodiment, it is desirable to use, for example, a microblasting method for spraying fine particles having an average particle diameter (D50) of 1 μm or more and 25 μm or less as the sandblasting method. By doing so, the shape of the side wall portion that defines the opening 28 of the solder resist layer 10 and the shape of the upper surface portion of the conductive pattern 24 can be further controlled. In addition, the degree of adhesion of the resin residue (smear) to the substrate 20 can be controlled to a higher degree. Therefore, it is possible to obtain the wiring substrate 20 capable of manufacturing the semiconductor package 102 with better connection reliability.

  Moreover, when using a microblast processing method, it is preferable that the average particle diameter (D50) of the fine particle sprayed is 1 micrometer or more and 20 micrometers or less from a viewpoint of improving the processing precision of the opening part 28, and is 7 micrometers or more and 20 micrometers or less. It is more preferable that the thickness is 10.5 μm or more and 20 μm or less. If the D50 of the fine particles is within the above range, sandblasting with an excellent balance between polishing force and processing accuracy can be performed. Therefore, the depth and shape of the opening 28 formed in the solder resist layer 10 can be controlled with high accuracy, and the opening 28 having a desired depth and desired shape can be formed in a shorter time. .

  As described above, when the opening 28 is formed in the solder resist layer 10 using the sand blasting process, a resist mask is provided on the solder resist layer 10, and the sand blasting process is performed on the solder resist layer 10 through the resist mask. It is preferred to do so. In particular, when performing microblast processing in which D50 of fine particles to be sprayed falls within the above range, a resist mask having a relatively thin thickness (15 μm or more and less than 50 μm) and high pattern resolution can be used.

  Here, since the sandblasting is a processing method having a high polishing force (cutting force), it is preferable to select a urethane-based material (photosensitive urethane resin) having a high cushioning property as a constituent material of the resist mask. it is conceivable that. In addition, it is considered preferable to design the resist mask to be relatively thick in order to improve the durability of the resist mask (for example, 50 μm or more). On the other hand, in the present embodiment, the particle size of the particles sprayed onto the solder resist layer 10 by sandblasting is within the above-described range, so that the durability of the resist mask is slightly higher than that of the photosensitive urethane resin. Although it is inferior, the protective region of the solder resist layer 10 can be reliably protected even when a photosensitive acrylic resin that is inexpensive and has good moldability is used.

  Furthermore, the depth of the opening 28 can be controlled to a high degree by using a microblasting method when forming the opening 28. In this way, when the depth of the opening 28 is highly controlled, it is possible to leave the portion of the solder resist layer 10 present on the side of the conductive pattern 24 without removing it. In other words, the solder resist layer 10 can be left in contact with the side surface of the conductive pattern 24 by highly controlling the depth of the opening 28. Thereby, the opening 28 can be formed without exposing the fine circuit. Therefore, even when an impact is applied when the wiring substrate 20 or the semiconductor package 102 is manufactured, high adhesion without causing the fine circuit to peel from the substrate 22 can be realized.

  In addition, when D50 of the fine particles sprayed onto the solder resist layer 10 by the microblast treatment is within the above range, the depth of the opening 28 to be polished (cut) is preferably 10 μm or more and 50 μm or less, and 20 μm. More preferably, it is 40 μm or less. If the depth of the opening 28 to be polished is within the above range, the protective region of the solder resist layer 10 can be reliably protected even when a relatively thin resist mask (less than 15 μm and less than 50 μm) is used. Moreover, the part which exists in the side of the conductive pattern 24 of the soldering resist layer 10 can remain more reliably. Thereby, when forming the opening part 28 in the soldering resist layer 10, it can prevent more reliably that an under etching generate | occur | produces around the conductive pattern 28. FIG.

FIG. 4 is an enlarged schematic view of the opening 28 formed in the solder resist layer 10 of the wiring board 20 according to the present embodiment. More specifically, FIG. 4A is a schematic plan view near the opening, and FIG. 4B is a schematic cross-sectional view near the opening.
As shown in FIG. 4A, the opening 28 formed in the solder resist layer 10 of the wiring board 20 is an opening of the opening 28 (the upper end of the opening 28 in FIG. 4B). The area is larger than the opening area of the bottom surface portion of the opening portion 28 (the lower end portion of the opening portion 28 in FIG. 4B). That is, the opening 28 formed in the solder resist layer 10 of the wiring board 20 has a diameter that increases from the bottom surface of the opening 28 toward the opening. In other words, the opening area of the opening 28 decreases from the surface of the solder resist layer 10 opposite to the conductive pattern 24 toward the conductive pattern 24.

  4B, the cross-sectional shape of the opening 28 formed in the solder resist layer 10 of the wiring board 20 is a tapered shape that spreads from the lower surface portion of the opening 28 toward the upper surface portion. The side wall portion that defines the opening 28 of the solder resist layer 10 is formed so as to draw a convex curve from the center of the opening 28 outward. Further, the end (lower end) of the side wall defining the opening 28 of the solder resist layer 10 is in contact with the side surface (upper end of the side surface) of the conductive pattern 24. Thus, by forming the opening 28 having a specific shape, the connection reliability between the pad (the portion exposed to the opening 28 of the conductive pattern 24) and the bump or the wire can be improved. The reason for this is not clear, but by restricting the shape of the solder bump and wire end near the pad connection location, the interfacial stress between the pad and the bump or wire is reduced, thereby reducing the interfacial adhesion. It is assumed that it is due to improvement.

  Note that the cross-sectional shape of the opening 28 (tapered shape shown in FIG. 4B) is sprayed on the constituent material of the solder resist layer 10, the constituent material of particles used in the sandblasting process, the average particle diameter (D50), and the particles. It can be changed by setting various conditions such as the conditions (discharge direction from the nozzle, discharge pressure), the shape of the opening pattern formed in the resist mask, and the thickness thereof. In particular, the resist mask was sprayed onto the region so as to form the opening 28 of the solder resist layer 10 by making the thickness of the resist mask sufficiently thin so as to be within the above-described range (15 μm or more and less than 50 μm). After colliding with the solder resist layer 10, the particles are blown off to the outside of the resist mask opening. Therefore, since the abrasive grains are prevented from being deposited in the opening 28, the solder resist layer 10 can be preferentially polished along the thickness direction. As a result, the cross-sectional shape of the formed opening 28 is rectangular.

Further, the abrasive (blasting material) used for the sandblasting treatment is not particularly limited, and for example, particles composed of SiC, SiO ₂ , Al ₂ O ₃ , ZrO, or the like can be used. These particles may be used alone or in combination of two or more.

Moreover, it is preferable that it is about 0.1-1.0 MPa, and, as for the pressure of the blast in sandblasting process, it is more preferable that it is about 0.15-0.8 MPa. If the blast pressure is within the above range, the opening 28 can be formed in a shorter time while the protective region of the solder resist layer 10 is more reliably protected.

As described above, the opening 28 can be formed in the solder resist layer 10.
Note that the resist mask as described above can be peeled off from the solder resist layer 10 using, for example, an alkaline solvent containing sodium hydroxide, potassium hydroxide, organic amine, or the like.

Next, in the process of desmear treatment, smear generated by the formation of the opening 28 is removed. Specifically, the smear attached to the side wall portion defining the opening portion 28 of the solder resist layer 10 and the upper surface portion (portion exposed to the opening portion 28) of the conductive pattern 24 is removed.
The method of desmear treatment is not particularly limited, but can be performed as follows, for example. First, the substrate 22 on which the conductive pattern 24 and the solder resist layer 10 are laminated is immersed in a swelling liquid containing an organic solvent. Then, it is treated by immersing in an alkaline permanganate aqueous solution.
As the permanganate, for example, potassium permanganate, sodium permanganate and the like can be used.
When potassium permanganate is used as the permanganate, the temperature of the potassium permanganate aqueous solution to be immersed is preferably 45 ° C. or higher, and preferably 95 ° C. or lower. The immersion time in the aqueous potassium permanganate solution is preferably 2 minutes or more, and preferably 20 minutes or less. If the temperature and the immersion time are each not more than the above upper limit value and not less than the above lower limit value, smear can be efficiently removed.

  In addition, about the process of performing the said desmear process, it can also be abbreviate | omitted by controlling the above-mentioned sandblast processing conditions highly. Specifically, the resin residue (smear) adheres to the surface of the conductive pattern 24 exposed by forming the openings 28 by highly controlling the average particle diameter (D50) of the particles sprayed during the sandblasting process. Can be suppressed. Therefore, when the average particle diameter (D50) of the particles sprayed during the sandblasting process is highly controlled, the desmearing process can be omitted, and the manufacturing process of the wiring board 20 can be simplified. .

In the desmear process, only the above-described wet desmear process can be performed. However, instead of or in addition to the above-described wet process, plasma irradiation may be performed as a desmear process.
At this time, for example, argon gas, O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, NO ₂ gas, or fluorine-based gas can be used as the processing gas. The plasma treatment time is preferably 30 seconds or longer, more preferably 1 minute or longer. On the other hand, the time is preferably 10 minutes or less, and more preferably 5 minutes or less. If the plasma treatment time is not less than the above lower limit and not more than the above upper limit, smear can be efficiently removed. Further, by adopting the above processing conditions, it is possible to improve the adhesion of the semiconductor package to the sealing material.

Next, a plating film 246 is formed on the exposed surface of the conductive pattern 24 as shown in FIG. Specifically, the plating film 246 is formed so as to cover the conductive portion of the conductive pattern 24 exposed in the opening 28.
The plating film 246 includes, for example, a solder plating film, a tin plating film, a two-layer plating film in which a gold plating film is laminated on a nickel plating film, and an under bump metal (UBM) film formed by electroless plating. can do.
Moreover, the film thickness of the plating film 246 is not particularly limited, but may be, for example, 2 μm or more and 10 μm or less. Thereby, the land 244 portion can be a connection portion suitable for wire bonding or soldering in a mounting process using the wiring board 20.

The method for the plating treatment is not particularly limited, and for example, an electrolytic plating method or an electroless plating method can be used. When the electroless plating method is used, the plating film 246 can be formed as follows. In addition, although the example which forms the plating film 246 which consists of two layers, a nickel plating film and a gold plating film, is demonstrated here, it is not limited to this.
First, a nickel plating film is formed. When performing electroless nickel plating, the structure 1000 provided with the opening 28 in the plating solution is immersed. Thus, a nickel plating film can be formed on the conductive portion of the conductive pattern 24 exposed at the opening 28.
As such a plating solution, nickel lead and a plating solution containing hypophosphite as a reducing agent can be used. Subsequently, electroless gold plating is performed on the nickel plating film. Although the method of electroless gold plating is not particularly limited, for example, it can be performed by substitution gold plating performed by substitution of gold ions and ions of a base metal.

Next, the surfaces of the solder resist layer 10 and the plating film 246 are subjected to plasma treatment.
In the plasma processing, for example, argon gas, oxidizing gas, or fluorine-based gas can be used as the processing gas. Examples of the oxidizing gas include O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, and NO ₂ gas.
The conditions for the plasma treatment in the present embodiment are not particularly limited, but may be a treatment in contact with plasma derived from an inert gas in addition to the ashing treatment. In addition, it is preferable that this plasma treatment is not a plasma treatment that involves etching of the solder resist layer 10. Here, plasma treatment with etching refers to plasma treatment in which a bias voltage is applied to a treatment target and an etching gas is used as a treatment gas. That is, the plasma processing according to the present embodiment is preferably a plasma processing performed without applying a bias voltage to the processing target or a plasma processing performed using a non-reactive gas.

In the present embodiment, the configuration in which no bias voltage is applied to the processing target is a configuration in which no bias voltage is applied to either the conductive pattern 24 or the plating film 246 of the substrate 22. Further, a bias voltage is not applied to a sample stage of a plasma processing apparatus for fixing the substrate 22 during the plasma processing. Note that the surface of the solder resist layer 10 may be slightly shaved by plasma treatment to such an extent that the degree of exposure of the filler 120 (see FIG. 5) included in the solder resist layer 10 is not increased. The plasma treatment time is preferably 30 seconds or longer, more preferably 1 minute or longer. On the other hand, the time is preferably 10 minutes or less, and more preferably 5 minutes or less. If the plasma treatment time is not less than the lower limit and not more than the upper limit, the durability of the package can be improved more reliably.
In the manufacturing method according to the present embodiment, the wiring board 20 is manufactured as described above.

Further, on the surface of the solder resist layer 10 of the wiring substrate 20 according to the present embodiment, as shown in FIG. 5, at least one filler 120 is partially embedded in the solder resist layer 10 and the other part is solder resist layer 10. It is preferable to protrude from the surface (upper surface in FIG. 5).
Moreover, it is preferable that the surface of the solder resist layer 10 of the manufactured wiring board 20 has a crater-shaped recess 110 formed by separating the filler 120.
In addition, on the surface of the solder resist layer 10 of the manufactured wiring board 20, either one of the protruding portion formed by protruding a part of the filler 120 from the surface of the solder resist layer 10 and the concave portion 110. However, it is more preferable that both the protruding portion and the concave portion 110 exist. By setting it as the surface form of such a soldering resist layer 10, the wiring board 20 which can manufacture the package excellent in durability can be implement | achieved more reliably.

  The surface of the solder resist layer 10 can be brought into the above-described form by appropriately adjusting the inclusion condition of the filler 120, the desmear treatment condition, the plating treatment condition, the plasma treatment condition, and the like. . Details of the filler 120 will be described later.

  In the conventional manufacturing processes described in Patent Documents 1 and 2, in the process of forming a plurality of openings in the solder resist layer, physical properties such as the degree of curing of the material forming the solder resist layer vary. For this reason, the opening shape and the opening depth of each opening portion vary between the opening portion opened first and the opening portion opened last. According to the manufacturing method according to the present embodiment, even when the plurality of openings 28 are formed in this way, the solder resist layer 10 can be uniformly and efficiently (with no variation) without occurrence of under-etching. ) Can be removed. Thereby, the upper surface of the conductive pattern 24 can be reliably exposed to the opening 28.

  In the conventional method for forming an opening described in Patent Documents 1 and 2, the depth of the solder resist layer 10 to be removed cannot be controlled. On the other hand, according to the manufacturing method according to the present embodiment, it is possible to control the depth of the solder resist layer 10 to be removed when forming the opening 28 by using a specific method called sandblasting. Therefore, in the manufacturing method according to the present embodiment, depending on the conditions of the sandblasting process, other than the portion (land 244 described later) connected to the solder bump or the bonding wire in the fine circuit (conductive pattern 24) provided on the substrate. The opening 28 can be formed without exposing the region.

  Specifically, according to the manufacturing method according to the present embodiment, the depth of the opening 28 can be controlled by highly controlling the conditions of the sandblast treatment. Therefore, the shape of the opening 28 can be controlled so that the end of the solder resist layer 10 is in contact with the side surface of the conductive pattern 24. In the case of such an opening shape, the side surface of the conductive pattern 24 can be protected by the solder resist layer 10. Accordingly, even when an impact is applied when the wiring substrate 20 or the semiconductor package 102 is manufactured, the adhesion between the fine circuit and the substrate 22 is increased, so that the fine circuit is prevented from peeling off from the substrate 22. Can do.

  Further, in the manufacturing method according to the present embodiment, when the sandblast processing conditions are highly controlled, the solder bump (solder ball) 30 (see FIG. 7) and the bonding wire 50 (see FIG. 7) are performed without performing desmear processing. And the conductive pattern 24 are connected with excellent connection reliability. Therefore, according to the manufacturing method according to the present embodiment, the manufacturing process of the wiring board 20 can be simplified as compared with the conventional manufacturing processes described in Patent Documents 1 and 2.

  Furthermore, according to the manufacturing method according to the present embodiment, since the opening 28 is formed in the solder resist layer 10 using a specific method called sandblasting, the surface of the exposed conductive pattern 24 is appropriately roughened (unevenness). ) Can be generated. When the above-described moderate roughness (unevenness) is present on the surface of the conductive pattern 24, the conductive pattern 24 and the solder bumps 30 and the bonding wires 50 can be more firmly connected in a subsequent process. Therefore, according to the manufacturing method according to the present embodiment, a thermal history is applied when the semiconductor package 102 or electronic device using the obtained wiring board 20 is manufactured or used, or the semiconductor package 102 or the electronic device is used for a long time. Even in this case, high reliability can be maintained over time.

  In the conventional manufacturing process described in Patent Documents 1 and 2, even when a chemical etching method or a plasma processing method is used to form an opening in the solder resist layer, the surface of the exposed conductive pattern 24 is exposed. Roughness can occur. However, the surface roughness of the conductive pattern 24 that occurs when a specific method called sandblasting is used as in the manufacturing method according to the present embodiment, and the conductive pattern that occurs in the conventional manufacturing process described in Patent Documents 1 and 2 With surface roughness, the shape and chemical state of the conductive pattern surface are different. When a specific method called sandblasting is used as in the manufacturing method according to this embodiment, the reason is not clear, but the connection between the conductive pattern 24 and the solder bump 30 or the bonding wire 50 is strengthened. Can do.

  And in the manufacturing method of the wiring board 20 which concerns on this embodiment, with respect to the part (upper surface part) exposed to the side wall part which prescribes | regulates the opening part 28 of the soldering resist layer 10, and the opening part 28 of the exposed conductive pattern 24. You may perform a desmear process. By doing so, even if the sandblasting conditions are not controlled, the inner peripheral surface that defines the opening 28 of the solder resist layer 10, that is, the side wall portion that defines the opening 28 of the solder resist layer 10 and Resin residue (smear) adhering to the portion exposed to the opening 28 of the conductive pattern 24 can be completely removed. Therefore, when the desmear process is performed after the opening 28 is formed by a specific method called sandblasting, the connection reliability is further improved compared to the conventional manufacturing processes described in Patent Documents 1 and 2. Thus, the wiring substrate 20 capable of manufacturing the semiconductor package 102 having a high yield can be obtained.

  Furthermore, when the desmear process is performed after the opening 28 is formed by the sandblast process as described above, the wiring board 20 having excellent adhesion with the sealant (sealing resin) can be manufactured with a high yield. Although the reason is not clear, it is thought that the chemical state and form of the surface of the wiring board are appropriate.

<Wiring board 20>
FIG. 6 is a schematic diagram showing an example of the structure of the wiring board 20 according to the present embodiment.
As shown in FIG. 6, the wiring substrate 20 obtained by the method for manufacturing the wiring substrate 20 according to the present embodiment includes a substrate 22, a conductive pattern 24, and a solder resist layer 10. The conductive pattern 24 is provided on at least one of the front and back outermost surfaces of the substrate 22. The solder resist layer 10 is the outermost layer of the wiring board 20 and is provided on the conductive pattern 24 so as to cover a part of the conductive pattern 24. For example, a plurality of openings 28 are provided in a predetermined region of the solder resist layer 10, and a part of the conductive portion of the conductive pattern 24 is located in at least one opening 28.

When the substrate 22 is a core substrate, it includes at least one insulating layer. At this time, the insulating layer with which the board | substrate 22 is provided is a resin base material formed by impregnating a fiber base material with a resin composition, for example. As described above, the wiring board 20 according to this embodiment will be described by taking the case where the board 22 is a core board as an example.
A thermosetting resin can be used as the resin composition constituting the insulating layer of the substrate 22. The substrate 22 may be a rigid substrate or a flexible substrate. The thickness of the substrate 22 is not particularly limited, but can be, for example, 10 μm or more and 300 μm or less.

Further, the substrate 22 may be a single-sided plate having only one insulating layer and having a conductive pattern 24 formed on only one side thereof, or having only one insulating layer and having a conductive pattern 24 on both the front and back surfaces. May be a double-sided board provided with a multi-layer board having two or more insulating layers. When the substrate 22 is a multilayer board, one or more wiring layers sandwiched between two insulating layers are formed in the substrate 22.
When the substrate 22 is a double-sided board or a multilayer board, the conductive pattern 24 provided on one surface (one outermost surface) of the substrate 22 is on the opposite surface (the other outermost surface). The conductive pattern 24 provided and the wiring layer provided inside the substrate 22 are electrically connected to each other via a through hole (not shown) penetrating at least a part of the insulating layer.

A conductive pattern 24 is provided on at least one surface (outermost surface) of the front surface and the back surface of the substrate 22. The conductive pattern 24 is, for example, a pattern formed by selectively etching a copper film laminated on the substrate 22.
The conductive pattern 24 includes lands 244 and lines 242 as conductive portions. The land 244 is a connection part that electrically connects an element or component mounted on the wiring board 20 and the conductive pattern 24, and is connected to, for example, another part of the conductive pattern 24 or a wiring layer in the board 22. It is a round or square part.
Note that a hole for inserting a terminal of an electronic component or the like may be provided at the center of the land 244. The line 242 is mainly a linear portion that electrically connects the lands 244 to each other.

In the wiring board 20, the solder resist layer 10 is laminated on the conductive pattern 24.
The solder resist layer 10 is provided with an opening 28 mainly in a region where the land 244 is provided, and the upper surface of the land 244 is not covered with the solder resist layer 10. That is, the solder resist layer 10 is not provided on the land 244, and the land 244 is exposed.
Note that a conductive film such as a nickel and gold plating film or a solder plating film may be laminated on the land 244. However, the solder resist layer 10 may be further provided with an opening 28 in a portion other than the land 244, or may have an opening 28 that exposes a part of the line 242. Further, it is not necessary for all of the lands 244 to be located in the openings 28, and there may be lands 244 covered with the solder resist layer 10.

The solder resist layer 10 of the wiring board 20 has an arithmetic average roughness Ra of the surface of preferably 0.08 μm or more, and more preferably 0.25 μm or more. Further, Ra is preferably 0.50 μm or less, and more preferably 0.40 μm or less. The arithmetic average roughness Ra can be measured according to JIS-B0601.
When Ra is equal to or higher than the lower limit value and equal to or lower than the upper limit value, a variation in adhesion between the solder resist layer 10 and the sealing resin 40 due to a temperature change is small, so that stable durability is obtained. Moreover, if Ra is below the said upper limit, when patterning liquid sealing resin on the soldering resist layer 10, high patterning precision will be obtained. Therefore, it is excellent not only in transfer molding but also in the degree of freedom in selecting a process for forming the sealing resin on the solder resist layer 10.
For example, when sufficient patterning accuracy is not obtained, the sealing resin is formed in unnecessary portions on the solder resist layer 10 when the resin is sealed, resulting in a defective package. Therefore, the sealing resin cannot be molded by a coating method or a transfer method. Therefore, when Ra is equal to or lower than the upper limit value and equal to or higher than the lower limit value, the wiring board 20 having a good performance balance of durability with patterning accuracy can be realized. In addition, when Ra is equal to or lower than the upper limit value and equal to or higher than the lower limit value, a decrease in adhesion between the solder resist layer 10 and the sealing resin 40 at a high temperature is reliably suppressed.

  The glass transition temperature (Tg) of the solder resist layer 10 is preferably 150 ° C. or higher, for example. As a result, it is possible to improve the heat resistance and reflow resistance of the solder resist layer 10. On the other hand, the upper limit value of the Tg is not particularly limited, but can be, for example, 280 ° C.

  The storage elastic modulus at 25 ° C. of the solder resist layer 10 is preferably 1 GPa or more, and more preferably 5 GPa or more. Moreover, it is preferable that it is 20 GPa or less. If the storage elastic modulus at 25 ° C. of the solder resist layer 10 is not more than the above upper limit value and not less than the above lower limit value, the wiring board 20 capable of producing a package having excellent durability can be obtained more reliably. Moreover, if the said storage elastic modulus is more than the said lower limit, the wiring board 20 provided with the tolerance outstanding with respect to curvature etc. will be obtained.

  In the present embodiment, the storage elastic modulus and the Tg are measured results obtained by performing a dynamic viscoelasticity test using a dynamic viscoelasticity measuring device under the conditions of a frequency of 1 Hz and a heating rate of 5 ° C./min. From this, it can be calculated. Although it does not specifically limit as a dynamic viscoelasticity measuring apparatus, For example, TA Instruments company make and DMA983 can be used.

The linear expansion coefficient of the solder resist layer 10 is preferably 10 ppm / ° C. or higher at Tg or lower. Moreover, it is preferable that it is 50 ppm / degrees C or less. If the linear expansion coefficient is equal to or lower than the upper limit value and equal to or higher than the lower limit value, the wiring board 20 capable of manufacturing a package having excellent durability can be more reliably realized.
In the present embodiment, for example, an average at 25 to 50 ° C. of the linear expansion coefficient obtained by measuring at a temperature rising rate of 10 ° C./min using a thermomechanical measurement device is calculated, and this is Tg or less. It can be set as the above linear expansion coefficient.

  In the present embodiment, for example, the type and blending amount of each component contained in the thermosetting resin composition (P) described later, a method for preparing the thermosetting resin composition (P), and the like are appropriately selected. Thus, the storage elastic modulus, the Tg, and the linear thermal expansion coefficient can be controlled.

  The wiring board 20 can be used as an interposer or a mother board, for example.

For manufacturing a package or an electronic device, a sealing resin 40 is formed on the wiring substrate 20.
In a finished product such as a package using the wiring board 20 as described above, high adhesion between the solder resist layer 10 and the sealing resin 40 is ensured. Therefore, it is possible to stably manufacture highly reliable packages and electronic devices that are excellent in durability and moisture resistance. The package refers to an electronic component in which various parts are mounted on the wiring board 20 and these parts are collectively sealed with a sealing resin 40, for example. The semiconductor package 102 is an example of a package, and the package includes an ECU (Electric Control Unit) and the like that are collectively sealed.

<Semiconductor package 102>
FIG. 7 is a schematic cross-sectional view showing an example of the structure of the semiconductor package 102 according to the present embodiment.
As shown in FIG. 7, the semiconductor package 102 according to this embodiment includes a wiring substrate 20, a semiconductor element 60, and a sealing resin 40. The semiconductor element 60 is disposed on the wiring board 20. The sealing resin 40 covers at least the surface of the wiring substrate 20 on which the semiconductor element 60 is provided and the semiconductor element 60. The wiring substrate 20 includes a substrate 22, a conductive pattern 24, and a solder resist layer 10. The conductive pattern 24 is provided on at least one of the outermost surfaces of the front and back surfaces (upper and lower surfaces in FIG. 7) of the substrate 22. The solder resist layer 10 is the outermost layer of the wiring board 20 and is provided on the conductive pattern 24. A plurality of openings 28 are provided in the solder resist layer 10, and a part of the conductive portion of the conductive pattern 24 is located in at least one opening 28. This will be described in detail below.

In the semiconductor package 102 according to the present embodiment, at least one semiconductor element 60 is disposed on the solder resist layer 10 on one surface (hereinafter referred to as “upper surface”) of the wiring substrate 20 described above.
In the semiconductor package 102, the wiring substrate 20 is, for example, an interposer, and the semiconductor element 60 is, for example, an LSI chip cut out from a semiconductor wafer.
In addition to the semiconductor element 60, for example, an electronic component functioning as a resistor or a capacitor may be further disposed on the upper surface of the wiring board 20. The semiconductor element 60 is fixed on the solder resist layer 10 via a die attach material 62.

The semiconductor element 60 is provided with a connection pad (not shown) that can be electrically connected to the surface thereof, and the connection pad is connected to, for example, a circuit built in the semiconductor element 60. A land 244 which is a part of the conductive pattern 24 provided on the wiring board 20 is provided in the opening 28 of the solder resist layer 10.
The land 244 and the connection pad of the semiconductor element 60 are connected by a bonding wire 50. In the semiconductor package 102 according to the present embodiment, a plating film 246 is further provided on the land 244, and the land 244 is connected to the bonding wire 50 via the plating film 246. Further, instead of being connected by the bonding wire 50, it may be connected by a lead wire or solder.

  The sealing resin 40 is a surface other than the surface of the solder resist layer 10 exposed on the upper surface of the wiring substrate 20, the substrate 22, the plating film 246, and the surface of the semiconductor element 60 bonded to the wiring substrate 20 by the die attach material 62. And the bonding wire 50 are covered. The sealing resin 40 may cover the entire surface of the wiring substrate 20 on which the semiconductor element 60 is provided, or may cover a part of the surface exposed.

The wiring substrate 20 of the semiconductor package 102 is further provided with a plurality of openings 28 and lands 244 inside the openings 28 on the surface opposite to the upper surface (hereinafter referred to as “lower surface”). Each land 244 is covered with a plating film 246, and further, solder bumps 30 connected to the plating film 246 are provided.
Here, the example of the flip chip connection package has been described as the semiconductor package 102 according to the present embodiment, but the present invention is not limited to this. The semiconductor package may be, for example, a package that is connected by wire bonding or TAB (Tape Automated Bonding).

In the semiconductor package 102, between the solder resist layer 10 and the sealing resin 40, 25 when the shear strength at ℃ was _{S 1,} it is preferred that _{S 1} is 15N / mm ² or more, 29N / mm ² more It is more preferable that If the shear strength is equal to or higher than the lower limit, the adhesion between the solder resist layer 10 and the sealing resin 40 is excellent, and the durability of the semiconductor package 102 is more reliably improved.

In the semiconductor package 102, between the solder resist layer 10 and the sealing resin 40, when the shear strength at 260 ° C. was _{S 2,} it is preferred that _{S 2} is 8N / mm ² or more. If it is more than the said lower limit, durability of the semiconductor package 102 will improve more reliably. This is because high adhesion between the solder resist layer 10 and the sealing resin 40 is maintained even when the temperature of the semiconductor package 102 rises due to use in a high temperature environment or heat generation in circuit operation.

Furthermore, in the semiconductor package 102, S ₂ / S ₁ is preferably 0.1 or more, and more preferably 0.2 or more. Further, S ₂ / S ₁ can be set to 0.9 or less. When S ₂ / S ₁ is equal to or higher than the lower limit, the durability of the semiconductor package 102 is more reliably improved. This is because a decrease in adhesion between the solder resist layer 10 and the sealing resin 40 at a high temperature is effectively suppressed.
The shear strength at each temperature can be measured using, for example, a shear strength measuring device (manufactured by DAGE, PC2400).

<Electronic device 70>
FIG. 8 is a schematic cross-sectional view showing an example of the structure of the electronic device 70 according to the present embodiment.
As shown in FIG. 8, the electronic device 70 according to this embodiment includes a semiconductor package 102. The semiconductor package 102 includes a wiring substrate 20, a semiconductor element 60, and a sealing resin 40. The semiconductor element 60 is disposed on the wiring board 20. The sealing resin 40 covers at least one surface (the upper surface in FIG. 8) of the wiring substrate 20 and the semiconductor element 60. The wiring substrate 20 includes a substrate 22, a conductive pattern 24, and a solder resist layer 10. The conductive pattern 24 is provided on at least one of the front and back outermost surfaces of the substrate 22. The solder resist layer 10 is the outermost layer of the wiring board 20 and is provided on the conductive pattern 24. The solder resist layer 10 is provided with a plurality of openings 28. A part of the conductive part of the conductive pattern 24 is located in the at least one opening 28. This will be described in detail below.

  In the electronic device 70, at least one semiconductor package 102 is disposed on a mother board 710 that is a wiring board. The mother board 710 may be the same wiring board as the wiring board 20 described above, or may be a different wiring board. The semiconductor package 102 is a semiconductor package 102 including the wiring board 20 described above. On the motherboard 710, in addition to the semiconductor package 102, one or more necessary electronic components 720 such as a connector, a resistor, and a capacitor may be disposed.

  The semiconductor package 102 disposed on the motherboard 710, other electronic components 720, and the like are connected to the exposed conductive portion 714 in the conductive pattern 712 of the motherboard 710 by the connection portion 716. The semiconductor package 102 and the electronic component 720 are connected to a conductive pattern 712 provided on the mother board 710 to constitute an electronic circuit.

<Method for Manufacturing Semiconductor Package 102>
In the manufacturing method of the semiconductor package 102 of the present embodiment, a part of the conductive pattern 24 is formed on the solder resist layer 10 as shown in FIG. 3A and a step of preparing the structure 1000 shown in FIG. A step of forming the opening 28 to be exposed and a step of melting and fusing the end portion of the solder bump 30 or the bonding wire 50 on the exposed conductive pattern 24 are included in this order. And the process of forming the opening part 28 in the soldering resist layer 10 includes the process of performing the sandblast process to the predetermined area | region which should form the opening part 28 among the soldering resist layers 10. FIG. By this process, the solder resist layer 10 can be efficiently and uniformly removed in a short time without causing under-etching. Thereby, the upper surface of the conductive pattern 24 can be reliably exposed to the opening 28. Therefore, according to the manufacturing method according to the present embodiment, a semiconductor package having excellent connection reliability can be obtained with a high yield as compared with the conventional manufacturing processes described in Patent Documents 1 and 2.

According to the manufacturing method according to the present embodiment, it is possible to firmly connect the conductive pattern 24 to the solder bump 30 and the bonding wire 50. Therefore, compared with the conventional manufacturing processes described in Patent Documents 1 and 2, the connection reliability can be improved. And the method of forming the opening 28 in the conventional manufacturing process described in Patent Documents 1 and 2 Then, the depth of the solder resist layer 10 to be removed could not be controlled. On the other hand, according to the manufacturing method according to the present embodiment, it is possible to control the depth of the solder resist layer 10 to be removed when forming the opening 28 by using a specific method called sandblasting. Therefore, in the manufacturing method according to the present embodiment, depending on the conditions of the sandblasting process, the opening 28 is formed without exposing the region other than the portion connected to the solder bump or the bonding wire in the fine circuit provided on the substrate. Can be formed. As a result, it is possible to obtain a highly durable semiconductor package 102 that can prevent a fine circuit from being damaged by an impact applied when the wiring substrate 20 or the semiconductor package 102 is manufactured.

  Moreover, according to the manufacturing method according to the present embodiment, the opening 28 is formed in the solder resist layer 10 using a specific method called sandblasting. Therefore, it is possible to prevent the resin residue (smear) from adhering to the side wall portion defining the opening portion 28 of the solder resist layer 10 and the upper surface portion of the conductive pattern 24 when forming the opening portion 28. When the sandblasting conditions are highly controlled, the conductive pattern 24 having excellent connection reliability with the solder bumps 30 and the bonding wires 50 can be formed without performing desmearing. Therefore, according to the manufacturing method according to the present embodiment, the manufacturing process of the semiconductor package 102 can be simplified as compared with the conventional manufacturing processes described in Patent Documents 1 and 2.

  Hereinafter, a method for manufacturing the semiconductor package 102 according to the present embodiment will be described in detail. In the manufacturing method according to the present embodiment, first, the wiring board 20 is prepared in the same manner as the above-described manufacturing method of the wiring board 20.

  Next, in the step of disposing the semiconductor element 60, the semiconductor element 60 is disposed on the solder resist layer 10 of the prepared wiring board 20. At this time, for example, the semiconductor element 60 is mounted on the wiring board 20 via the die attach material 62. The bonding wire 50 that connects the semiconductor element 60 and the wiring board 20 is bonded to the conductive pattern 24 exposed in the opening 28 on the upper surface of the wiring board 20, for example. Next, in the sealing step, the upper surface of the wiring substrate 20, the semiconductor element 60, and the bonding wire 50 are sealed with a sealing resin 40. As the sealing resin 40, for example, an epoxy resin composition can be used. As a method of molding (sealing) the wiring substrate 20 or the like with the sealing resin 40, a transfer molding method, an injection molding method, a transfer method, a coating method, or the like can be used. Moreover, hardening of the sealing resin 40 is performed by heating at 150 degreeC or more and 200 degrees C or less, for example.

  In the example in which the solder bumps 30 that are external connection terminals are provided on the wiring board 20, for example, the solder bumps 30 are formed on the conductive pattern 24 exposed in the opening 28 on the lower surface side of the wiring board 20. Although an example of a flip chip connection package has been described as the semiconductor package 102 according to the present embodiment, the semiconductor package 102 is not limited to this. As the semiconductor package, for example, a wire bonding or TAB connection package may be used.

<Method for Manufacturing Electronic Device>
The electronic device 70 illustrated in FIG. 8 is obtained by mounting the semiconductor package 102 obtained as described above on the mother board 710 together with other electronic components 720.
The semiconductor package 102 and the electronic component 720 each have one or more connection terminals such as a connection portion 716 and a solder bump 30, and the connection terminals are electrically connected to the exposed conductive portion 714 in the conductive pattern 712 of the motherboard 710. . The connection between the connection terminal and the conductive portion 714 can be performed as follows, for example.
First, a solder paste is printed on a necessary portion of the exposed conductive portion 714 of the motherboard 710. Here, when the semiconductor package 102 has the solder bumps 30, it is not necessary to print solder paste on the conductive portions 714 that connect the solder bumps 30.
Next, the electronic component 720 and the semiconductor package 102 are arranged at predetermined positions on the mother board 710.
Thereafter, the motherboard 710 on which the semiconductor package 102 and the electronic component 720 are placed is introduced into a reflow furnace, and reflow processing (heating processing) is performed. The solder paste and solder bumps 30 printed by the reflow process are melted and then cooled, whereby the semiconductor package 102 and the electronic component 720 are respectively soldered to the mother board 710.

  The method for manufacturing the electronic device 70 according to the present embodiment includes a heat treatment process. The heat treatment is, for example, a reflow process. For example, when the semiconductor package 102 is a package connected to the motherboard 710 by wire bonding, heat treatment can be performed to surface-mount the electronic component 720. Therefore, even after the heat treatment, if the bonding strength between the solder resist layer 10 and the sealing resin 40 is sufficiently high, the durability of the package can be improved more reliably.

  Also, the electronic device 70 may be used under high humidity. Even in such a case, if the bonding strength between the solder resist layer 10 and the sealing resin 40 is sufficiently high, the durability of the package can be improved more reliably.

  In addition, since the semiconductor package 102 included in the electronic device 70 has excellent durability and excellent moisture resistance, the highly reliable electronic device 70 can be obtained. The electronic device 70 may be further collectively sealed with a sealing resin. When the motherboard 710 is the wiring substrate 20 described above and the electronic device 70 is collectively sealed, the electronic device 70 can be manufactured as a package.

According to the manufacturing method according to the present embodiment, the solder resist layer 10 can be efficiently and uniformly removed in a short time without occurrence of under-etching. Thereby, the upper surface of the conductive pattern 24 can be reliably exposed to the opening 28. Therefore, according to the manufacturing method according to the present embodiment, it is possible to obtain the semiconductor package 102 excellent in connection reliability with a high yield as compared with the conventional manufacturing processes described in Patent Documents 1 and 2.
And according to the manufacturing method which concerns on this embodiment, it is possible to control the depth of the soldering resist layer 10 removed when forming the opening part 28 by using the specific construction method called sandblasting. Thus, the solder resist layer 10 can be left so as to be in contact with the side surface of the conductive pattern 24. Thereby, the opening 28 can be formed without exposing the fine circuit. For this reason, even when an impact is applied when manufacturing the wiring substrate 20 or the semiconductor package 102, it is possible to realize high adhesion without causing the fine circuit to peel from the substrate 22.

Further, according to the manufacturing method according to the present embodiment, since the opening 28 is formed in the solder resist layer 10 using a specific method called sandblasting, resin residue (smear) is formed when the opening 28 is formed. In addition, it is possible to prevent the solder resist layer 10 from adhering to the side wall portion that defines the opening 28 and the upper surface portion of the conductive pattern 24.
When the sandblasting conditions are highly controlled, the conductive pattern 24 having excellent connection reliability with the solder bumps 30 and the bonding wires 50 can be formed without performing desmearing. Therefore, according to the manufacturing method according to the present embodiment, the manufacturing process can be simplified as compared with the conventional manufacturing processes described in Patent Documents 1 and 2.
Furthermore, according to the manufacturing method according to the present embodiment, even when a plurality of openings 28 is formed, the upper surface of the conductive pattern 24 can be exposed to the openings 28 in all the openings 28. A plurality of openings 28 having no variation in the opening shape and opening depth of each opening 28 can be formed. That is, according to the manufacturing method according to the present embodiment, the plurality of openings 28 are accurate to such an extent that there is no variation in the shape and depth of the openings, the under-etching does not occur, and the conductive pattern 24 is formed. The solder resist layer 10 can be efficiently and uniformly removed in a short time so that the upper surface is exposed in the opening 28.

<< Second Embodiment >>
FIG. 9 (FIGS. 9A to 9C) is a schematic diagram showing an example of a method for manufacturing a wiring board according to the present embodiment.
In the manufacturing method according to the present embodiment, first, as shown in FIG. 9A, a double-sided substrate 22 having conductive patterns 24 formed on both sides is prepared. Next, as shown in FIG. 9B, a laminated film in which the release film 12 and the solder resist film 10 are laminated is pasted (laminated) on the conductive pattern 24 so as to cover the conductive pattern 24 of the substrate 22. ). Thereafter, this is vacuum-heated and pressure-molded. Next, as shown in FIG. 9C, the peeling film 12 is peeled off to produce a structure 1000. The wiring board manufacturing method according to the present embodiment is different from the first embodiment in this respect.
Although the said peeling film 12 is not specifically limited, For example, it is comprised by PET (Polyethylene terephthalate). Also according to this embodiment, the same effects as those of the first embodiment can be obtained.

  Next, the configuration of the solder resist layer 10 according to this embodiment will be described. The solder resist layer 10 can be formed from, for example, the following thermosetting resin composition (P), but is not particularly limited.

  The thermosetting resin composition (P) is not particularly limited as long as it is a resin composition that can be used as an insulating material for the wiring board 20. The thermosetting resin composition (P) includes, for example, at least a curing agent for thermosetting resins such as epoxy resins, cyanate ester resins, phenol resins, bismaleimide-triazine resins, polyimide resins, acrylic resins, and vinylbenzyl resins. It can be set as the compounded composition. Especially, the composition containing an epoxy resin (A) is preferable.

(Epoxy resin (A))
The thermosetting resin composition (P) can mainly contain an epoxy resin (A). The epoxy resin (A) is, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, hydrogenated bisphenol A type epoxy resin, bisphenol M type epoxy resin (4,4 ' -(1,3-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 '-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Z type epoxy Bisphenol type epoxy resins such as resins (4,4'-cyclohexyldiene bisphenol type epoxy resins); phenol novolac type epoxy resins, brominated phenol novolac type epoxy resins, cresol novolac type epoxy resins, tetrapheno Novolak-type epoxy resins such as novolak-type epoxy resins having a ruthenium ethane-type novolak-type epoxy resin and condensed ring aromatic hydrocarbon structures; biphenyl-type epoxy resins; aralkyl-type epoxy resins such as xylylene-type epoxy resins and biphenyl-aralkyl-type epoxy resins ; Having a naphthalene skeleton such as naphthylene ether type epoxy resin, naphthol type epoxy resin, naphthalene type epoxy resin, naphthalene diol type epoxy resin, bifunctional or tetrafunctional epoxy type naphthalene resin, binaphthyl type epoxy resin, naphthalene aralkyl type epoxy resin, etc. Epoxy resin; anthracene type epoxy resin; phenoxy type epoxy resin; dicyclopentadiene type epoxy resin; norbornene type epoxy resin; adamantane type epoxy resin; Type epoxy resin, phosphorus-containing epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, bisphenol A novolak type epoxy resin, bixylenol type epoxy resin, trihydroxyphenylmethane type epoxy resin, tetraphenylolethane type epoxy resin , Heterocyclic epoxy resins such as triglycidyl isocyanurate; N, N, N ′, N′-tetraglycidylmetaxylenediamine, N, N, N ′, N′-tetraglycidylbisaminomethylcyclohexane, N, N— Diglycidylamines such as diglycidylaniline, copolymers of glycidyl (meth) acrylate and compounds with ethylenically unsaturated double bonds, epoxy resins having a butadiene structure, diglycidyl etherified products of bisphenol, diglycidyl of naphthalenediol Etherate, it can include one or more selected from glycidyl ethers of phenols.

  Among these, it is more preferable to include an epoxy resin having a naphthalene skeleton from the viewpoint of improving adhesion and embedding properties between the solder resist layer 10 and the substrate 22, the conductive pattern 24, and the sealing resin 40. Thereby, while the linear expansion coefficient of the soldering resist layer 10 can be reduced, the elasticity modulus can also be improved. In addition, it is possible to improve the workability by improving the rigidity of the wiring substrate 20 and to improve the reflow resistance and suppress the warpage of the semiconductor package 102. In addition, from the viewpoint of improving the adhesion between the solder resist layer 10 and the substrate 22, the conductive pattern 24, and the sealing resin 40 and improving the embedding property of the conductive pattern 24 in the solder resist layer 10, a trifunctional or higher functional naphthalene is used. It is particularly preferable to include an epoxy resin having a skeleton.

  In this embodiment, it is mentioned as an example of a preferable aspect that the epoxy resin shown to the following formula | equation (1) is included as an epoxy resin (A).

（式（１）中、ｎは０〜１０の整数であり、Ｒ_１およびＲ_２は互いに独立して水素原子、炭素数１〜６のアルキル基、または炭素数１〜６のアルコキシ基である）

(In the formula (1), n is an integer of 0, _{R 1} and _{R 2} independently of one another are hydrogen atom, is an alkyl group or an alkoxy group having 1 to 6 carbon atoms, 1 to 6 carbon atoms )

  The content of the epoxy resin (A) is, for example, preferably 3% by mass or more and more preferably 5% by mass or more with respect to the total solid content of the thermosetting resin composition (P). By setting the content of the epoxy resin (A) to the above lower limit or more, the solder resist layer 10 formed using the thermosetting resin composition (P), the substrate 22, the conductive pattern 24, and the sealing resin Thus, it is possible to contribute to the improvement of the adhesiveness to 40 and the embedding property of the conductive pattern 24 in the solder resist layer 10. On the other hand, the content of the epoxy resin (A) is preferably 30% by mass or less, and more preferably 20% by mass or less, for example, based on the total solid content of the thermosetting resin composition (P). . By making content of an epoxy resin (A) below the said upper limit, the heat resistance and moisture resistance of the soldering resist layer 10 formed using a thermosetting resin composition (P) can be aimed at. . The total solid content of the thermosetting resin composition (P) refers to the entire component excluding the solvent contained in the thermosetting resin composition (P). The same applies hereinafter.

(Filler (B))
It is preferable that a thermosetting resin composition (P) contains a filler (B). Examples of the filler (B) include spherical silica and crushed silica. From the viewpoint of improving the adhesion between the solder resist layer 10 and the substrate 22, the conductive pattern 24, and the sealing resin 40 and the embedding property of the conductive pattern 24 in the solder resist layer 10, it may contain spherical silica. preferable. The filler (B) is, for example, fused silica. The filler (B) is included in the solder resist layer 10 as the filler 120 as shown in FIG.

More preferably, the filler (B) contains fine particle silica having an average particle diameter of 2 nm or more and 100 nm or less in the thermosetting resin composition (P). Thereby, the adhesiveness of the soldering resist layer 10, and the board | substrate 22, the conductive pattern 24, and the sealing resin 40, and the embedding property to the soldering resist layer 10 of the conductive pattern 24 can be improved. It is included in the thermosetting resin composition (P) that the fine particle silica having an average particle diameter of 2 nm or more and 100 nm or less and the silica having an average particle diameter of more than 100 nm are contained in the thermosetting resin composition (P). 24 and an example of a preferable embodiment in improving the embedding property of the conductive pattern 24 in the solder resist layer 10.
In addition, the average particle diameter of a filler (B) can be measured, for example using a laser diffraction type particle size distribution measuring apparatus (the product made by HORIBA, LA-500).

  The content of the filler (B) is, for example, preferably 30% by mass or more and more preferably 50% by mass or more with respect to the total solid content of the thermosetting resin composition (P). By making content of a filler (B) more than the said lower limit, the heat resistance and moisture resistance of the soldering resist layer 10 obtained using a thermosetting resin composition (P) can be improved effectively. . Moreover, if content of a filler is more than the said lower limit, while the linear expansion coefficient of the soldering resist layer 10 can be reduced, the elasticity modulus can be improved. Thereby, it is possible to contribute to the reduction of warpage of the obtained semiconductor package 102. On the other hand, the content of the filler (B) is, for example, preferably 95% by mass or less, and more preferably 85% by mass or less, based on the total solid content of the thermosetting resin composition (P). By making content of a filler (B) below the said upper limit, adhesiveness with the soldering resist layer 10, the board | substrate 22, the conductive pattern 24, and the sealing resin 40, and the soldering resist layer 10 of the conductive pattern 24 It becomes possible to improve the embedding property.

(Cyanate resin (C))
The thermosetting resin composition (P) can contain, for example, a cyanate resin (C). Thereby, while being able to reduce the linear expansion coefficient of the soldering resist layer 10, the elasticity modulus and rigidity can be improved. It is also possible to contribute to improvement of heat resistance and moisture resistance of the obtained semiconductor device.
The cyanate resin (C) is, for example, a novolak-type cyanate resin; a bisphenol-type cyanate resin such as a bisphenol A-type cyanate resin, a bisphenol E-type cyanate resin, or a tetramethylbisphenol F-type cyanate resin; a naphthol aralkyl-type phenol resin; 1 type or 2 types or more selected from naphthol aralkyl type cyanate resin obtained by reaction of this; dicyclopentadiene type cyanate resin; biphenyl alkyl type cyanate resin can be included. Among these, from the viewpoint of lowering the linear expansion coefficient of the solder resist layer 10 and improving the elastic modulus and rigidity, it is more preferable to include at least one of a novolak-type cyanate resin and a naphthol aralkyl-type cyanate resin. It is particularly preferable to include a type cyanate resin.

The content of the cyanate resin (C) is, for example, preferably 3% by mass or more and more preferably 5% by mass or more with respect to the total solid content of the thermosetting resin composition (P). By making content of cyanate resin (C) more than the said lower limit, the linear expansion coefficient of the soldering resist layer 10 formed using a thermosetting resin composition (P) can be reduced more effectively. When it is possible, the elastic modulus can be improved. Moreover, it can contribute to the improvement of the adhesiveness between the solder resist layer 10 and the substrate 22, the conductive pattern 24, and the sealing resin 40 and the embedding property of the conductive pattern 24 in the solder resist layer 10.
On the other hand, the content of the cyanate resin (C) is, for example, preferably 30% by mass or less, and more preferably 20% by mass or less, based on the total solid content of the thermosetting resin composition (P). By making content of cyanate resin (C) below the said upper limit, the heat resistance and moisture resistance of the soldering resist layer 10 formed using a thermosetting resin composition (P) can be aimed at. .

(Curing accelerator (D))
The thermosetting resin composition (P) can contain, for example, a curing accelerator (D). Thereby, the sclerosis | hardenability of a thermosetting resin composition (P) can be improved.
As a hardening accelerator (D), the hardening accelerator which accelerates | stimulates hardening reaction of an epoxy resin (A) can be used, The kind in particular is not limited. In the present embodiment, examples of the curing accelerator (D) include zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, zinc octylate, bisacetylacetonate cobalt (II), and trisacetylacetonate cobalt. Organometallic salts such as (III), tertiary amines such as triethylamine, tributylamine, diazabicyclo [2,2,2] octane, 2-phenyl-4-methylimidazole, 2-ethyl-4-ethylimidazole, 2- Imidazoles such as phenyl-4-ethylimidazole, 2-phenyl-4-methyl-5-hydroxyimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, 2-phenyl-4,5-dihydroxyimidazole, phenol Bisphenol A, no Phenolic compounds such as Le phenol, acetic acid, benzoic acid, salicylic, organic acids such as p-toluenesulfonic acid, and one or more selected from an onium salt compound. Among these, it is more preferable to include an onium salt compound from the viewpoint of more effectively improving curability.

  Although the onium salt compound used as a hardening accelerator (D) is not specifically limited, For example, the compound represented by following General formula (2) can be used.

（式（２）中、Ｐはリン原子、Ｒ_３、Ｒ_４、Ｒ_５およびＲ_６は、それぞれ、置換もしくは無置換の芳香環または複素環を有する有機基、あるいは置換もしくは無置換の脂肪族基を示し、互いに同一であっても異なっていてもよい。Ａ⁻は分子外に放出しうるプロトンを少なくとも１個以上分子内に有するｎ（ｎ≧１）価のプロトン供与体のアニオン、またはその錯アニオンを示す）

(In formula (2), P is a phosphorus atom, R ₃ , R ₄ , R ₅ and R ₆ are each an organic group having a substituted or unsubstituted aromatic ring or heterocyclic ring, or a substituted or unsubstituted aliphatic group. Each of which may be the same as or different from each other, and A ⁻ represents an anion of an n-valent proton donor having at least one proton that can be released to the outside of the molecule in the molecule, or Indicates the complex anion)

The content of the curing accelerator (D) is preferably 0.1% by mass or more, for example, 0.3% by mass or more with respect to the total solid content of the thermosetting resin composition (P). More preferred. By making content of a hardening accelerator (D) more than the said lower limit, sclerosis | hardenability of a thermosetting resin composition (P) can be improved more effectively.
On the other hand, the content of the curing accelerator (D) is, for example, preferably 10% by mass or less and more preferably 5% by mass or less with respect to the total solid content of the thermosetting resin composition (P). preferable. By making content of a hardening accelerator (D) below the said upper limit, the preservability of a thermosetting resin composition (P) can be improved.

(Colorant (E))
The thermosetting resin composition (P) can contain, for example, a colorant (E).
The colorant (E) includes one or more selected from dyes, pigments, and pigments such as green, red, blue, yellow, and black. Among these, from the viewpoint of improving the visibility of the opening 28 and the like, it is more preferable to include a green colorant, and it is particularly preferable to include a green dye. As the green colorant, for example, one or more known colorants such as anthraquinone, phthalocyanine, and perylene can be contained.

The content of the colorant (E) is, for example, preferably 0.05% by mass or more, and more preferably 0.1% by mass or more with respect to the total solid content of the thermosetting resin composition (P). More preferred. By making content of a coloring agent (E) more than the said lower limit, visibility and concealment of the opening part 28 of the soldering resist layer 10 obtained using a thermosetting resin composition (P) are more effective. Can be improved.
On the other hand, the content of the colorant (E) is, for example, preferably 5% by mass or less and more preferably 3% by mass or less with respect to the total solid content of the thermosetting resin composition (P). . By making content of a coloring agent (E) below the said upper limit, it becomes possible to improve sclerosis | hardenability etc. of a thermosetting resin composition (P) more effectively.

(Other ingredients)
In addition to the above components, the thermosetting resin composition (P) includes a coupling agent, a leveling agent, a curing agent, a photosensitizer, an antifoaming agent, an ultraviolet absorber, a foaming agent, an antioxidant, as necessary. One or more additives selected from a flame retardant and an ion scavenger may be added.
Examples of the coupling agent include silane coupling agents such as epoxy silane coupling agents, cationic silane coupling agents, aminosilane coupling agents, titanate coupling agents, and silicone oil type coupling agents.
Examples of the leveling agent include acrylic copolymers.
Examples of the curing agent include a phenolic curing agent such as a phenol resin, a naphthol curing agent such as a naphthol type novolak resin, an amine curing agent, a guanidine curing agent, an imidazole curing agent, an acid anhydride curing agent, or the like. Examples thereof include epoxy adducts, microencapsulated compounds, and cyanate ester resins. Of these, phenol-based curing agents and naphthol-based curing agents are preferred.
Examples of the photosensitive agent include photosensitive diazoquinone compounds.
In addition, the thermosetting resin composition (P) is a polyvinyl acetal from the viewpoint of improving the adhesion between the substrate 22 and the solder resist layer 10 and improving the adhesion between the sealing resin 40 and the solder resist layer 10. Resin may be included. Examples of the polyvinyl acetal resin include polyvinyl butyral resin and polyvinyl acetoacetal resin.

(solvent)
The thermosetting resin composition (P) can contain a solvent, for example.
Examples of the solvent include acetone, methyl ethyl ketone, methyl isobutyl ketone, toluene, xylene, ethyl acetate, butyl acetate, butyl lactate, tetramethylbenzene, ethylene glycol monoethyl ether, cyclohexane, heptane, cyclohexane, cyclohexanone, tetrahydrofuran, dimethylformamide, dimethyl One or more selected from organic solvents such as acetamide, dimethyl sulfoxide, ethylene glycol, cellosolve, carbitol, anisole, and N-methylpyrrolidone can be included.

  In the case where the thermosetting resin composition (P) is varnished, the solid content of the thermosetting resin composition (P) in the varnish is preferably, for example, 30% by mass or more and 80% by mass or less. 40 mass% or more and 70 mass% or less is more preferable. Thereby, the thermosetting resin composition (P) excellent in workability | operativity and film formability is obtained. In addition, the varnish-like thermosetting resin composition (P) includes, for example, the above-described components, an ultrasonic dispersion method, a high-pressure collision dispersion method, a high-speed rotation dispersion method, a bead mill method, a high-speed shear dispersion method, and a rotation. It can prepare by melt | dissolving, mixing, and stirring in a solvent using various mixers, such as a revolution type dispersion system.

  In addition, the thermosetting resin composition (P) according to the present embodiment may include, for example, a fiber substrate such as a glass fiber substrate or a paper substrate. Thereby, the rigidity of the solder resist layer 10 can be improved, and the curvature of the wiring board 20 is suppressed.

  When the thermosetting resin composition (P) is in the form of a film, the film-like thermosetting resin composition (P) is used as it is as a resin film obtained using the thermosetting resin composition (P). Can be used. On the other hand, when the thermosetting resin composition (P) is varnished, the solvent is used for the thermosetting resin film obtained by forming the varnish-like thermosetting resin composition (P). The resin film subjected to the removal treatment can be used as a resin film obtained using the thermosetting resin composition (P). This solvent removal process is performed on the conditions that the solvent content rate of a thermosetting resin film will be 5 mass% or less with respect to the whole thermosetting resin film. In addition, the thermosetting resin film after the solvent removal treatment has a weight change rate of 5% by mass or less before and after heat treatment at 170 ° C. for 2 minutes. In this embodiment, for example, the solvent removal treatment can be performed under conditions of 100 to 160 ° C. and 5 to 60 minutes.

  In addition, this invention is not limited to the above-mentioned embodiment. Modifications, improvements and the like within the scope that can achieve the object of the present invention are included in the present invention.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

Hereinafter, specific examples of the present invention will be described. The present invention is not limited to this.
1. Production of wiring board (Example 1)
[1] Preparation of thermosetting resin composition (P) 13.3 parts by weight of epoxy resin having a naphthalene skeleton as epoxy resin (A) (manufactured by DIC Corporation, SBM-0150), average particle diameter as filler (B) 6 parts by weight of spherical silica having a D50 of 2 μm (manufactured by Admatechs CO., LTD., SC4050-KNR) and 7 parts by weight of spherical silica having an average particle diameter D50 of 0.05 μm (manufactured by Admatechs CO., LTD., Admanano) 13.4 parts by weight of phenol novolac type cyanate resin (Lonza Japan Ltd., PT30) as cyanate resin (C), tetraphenylphosphonium bis (naphthalene-2,3-dioxy) phenyl silicate as curing accelerator (D) Additive 0.6 parts by weight, colorant ( ) 0.4 part by weight of a green dye (manufactured by Nippon Kayaku CO., LTD., Kayset Green AB), 0.4 part by weight of a coupling agent (manufactured Performance Materials Inc., A-187), and level 0.3 parts by weight of a ring agent (BYK-Chemie Japan KK, BYK-361N) was dissolved in methyl ethyl ketone to obtain a mixed solution. By stirring this mixed liquid for 1 hour using a high-speed stirring device, a varnish-like thermosetting resin composition (P) was obtained.

[2] Preparation of structure First, both surfaces of a 240 μm-thick core substrate (manufactured by SUMITOMO BAKELITE CO., LTD., LαZ-4785TH-G) are laminated with a 12 μm-thick copper foil. A copper clad laminate was prepared. Next, the copper foil of this copper-clad laminate was subjected to an etching process to obtain a circuit board having conductor patterns formed on both sides. Next, after applying a varnish-like thermosetting resin composition (P) on one surface of the circuit board so as to cover the conductor pattern, the circuit board is dried at 150 ° C. for 10 minutes, whereby one of the circuit boards is covered. A solder resist layer having a thickness of 40 μm was formed on the surface. Similarly, a solder resist layer having a thickness of 40 μm was formed on the other surface of the circuit board. As a result, a structure as shown in FIG. 2B was obtained.

[3] Formation of Resist Mask A photoresist solution containing a photosensitive acrylic resin was applied on one solder resist layer of the structure obtained as described above, and then dried. Thereby, a photoresist film having a thickness of 25 μm was formed on the solder resist layer on one side of the structure. Similarly, a photoresist film having a thickness of 25 μm was formed on the other solder resist layer of the structure.
Next, each photoresist film was exposed and developed to form an opening pattern corresponding to the opening to be formed in the solder resist layer. In this way, a resist mask was formed on each solder resist layer.

[4] Formation of openings Next, a sandblast process is performed on each solder resist layer of the structure through a resist mask to form a plurality of openings that expose part of the conductive pattern (plural lands). did. The sand blasting process was performed at a blast pressure of 0.15 MPa using SiC beads having an average particle diameter (D50) of 3 μm as an abrasive. Moreover, the average depth of the openings polished by the sandblasting treatment was about 30 μm.
Thereafter, the resist mask is removed from each solder resist layer using an aqueous alkali solution containing sodium hydroxide, and wiring having six or more openings formed in the solder resist layer as shown in FIG. A substrate was obtained.

(Examples 2 to 6)
A wiring board was obtained in the same manner as in Example 1 except that the materials shown in Table 1 and the D50 (μm) abrasive were used as the abrasive for sandblasting.

2. Evaluation 2-1. Formation time of opening In Examples 1-6, when sandblasting was performed on one solder resist layer, the time until the land of the conductive pattern was exposed from the opening was evaluated according to the following criteria.
A: Time until all lands are exposed to the opening is 10 seconds or less B: Time until all lands are exposed to the opening is over 10 seconds to 20 seconds or less C: All lands are exposed to the opening Time over 20 seconds to 30 seconds or less D: Time until all lands are exposed to the opening is over 30 seconds

2-2. Processing accuracy of openings In Examples 1 to 6, the processing accuracy of each opening formed by sandblasting was evaluated according to the following criteria.
A: In all the openings, the part existing on the land upper surface of the solder resist layer is completely removed, and the part existing on the side of the land of the solder resist layer remains.
B: In one or two of the plurality of openings, a part of the solder resist layer remains on the top surface of the land, or the core base material is exposed around the land.
C: Among a plurality of openings, in three or more openings, a part of the solder resist layer remains on the top surface of the land, or the core base material is exposed around the land.
D: In three or more openings among the plurality of openings, a part of the solder resist layer remains on the top surface of the land, and the core base material is exposed around the land.
The evaluation results of 2-1 and 2-2 are shown in Table 1.

  As is apparent from Table 1, in Examples 1 to 6, the depth and shape of the opening formed in the solder resist layer are controlled with high accuracy, and such an opening is formed in a short time. I was able to.

3. Production of wiring board (Examples 7 to 11)
A wiring board in the same manner as in Example 1 except that the material and thickness of the resist mask (photoresist film) formed on each solder resist layer and the type of abrasive for sandblasting are as shown in Table 2. Got.

4). Evaluation 4-1. Blast resistance For each of the wiring boards obtained in Examples 7 to 11, the upper surface of the solder resist layer was visually observed, and the state of the region (protective region) other than the region where the opening was formed was based on the following criteria: Therefore, it was evaluated.
A: There is no chipping or cracking in the protective region of the solder resist layer.
B: One or two chips or cracks were observed in the protective region of the solder resist layer.
C: Three or four cracks or cracks were observed in the protective region of the solder resist layer.
D: Five or more chips or cracks were observed in the protective region of the solder resist layer.
Table 2 shows the evaluation results of 4-1 above. In Table 2, “Ac” is a photosensitive acrylic resin, and “Ur” is a photosensitive urethane resin.

  As apparent from Table 2, in Examples 7 to 11, almost no cracks or cracks were observed in the protective region of the solder resist layer. From this result, it can be said that the protective region of the solder resist layer is sufficiently protected by the resist mask during the sandblasting process. In particular, in Examples 7 to 11, a relatively thin resist mask is used, but the protective region of the solder resist layer can be protected by adjusting the particle size (D50) of the sandblasting abrasive. Although the durability is slightly inferior to that of the photosensitive urethane resin, the protective region of the solder resist layer can be protected even when a photosensitive acrylic resin that is inexpensive and has good moldability is used.

DESCRIPTION OF SYMBOLS 10 Solder resist layer 102 Semiconductor package 110 Recessed part 12 Release film 120 Filler 20 Wiring board 22 Substrate 24 Conductive pattern 242 Line 244 Land 246 Plating film 28 Opening part 30 Solder bump (solder ball)
40 sealing resin 50 bonding wire 60 semiconductor element 62 die attach material 70 electronic device 710 motherboard 712 conductive pattern 714 conductive portion 716 connection portion 720 electronic component 1000 structure

Claims (11)

Preparing a structure having a substrate having a conductive pattern on at least one surface and a solder resist layer laminated on the substrate so as to cover the conductive pattern;
Forming an opening in the solder resist layer to expose a part of the conductive pattern;
In this order,
The step of forming the opening includes a process of performing a sand blast process on a region of the solder resist layer where the opening is to be formed.   The method for manufacturing a wiring board according to claim 1, wherein the sandblasting is microblasting.   The method for manufacturing a wiring board according to claim 1 or 2, wherein an average particle diameter (D50) of particles used in the sandblast treatment is 1 µm or more and 25 µm or less.   The method for manufacturing a wiring board according to claim 1, further comprising a step of performing a desmear process on a side wall portion defining the opening of the solder resist layer and a portion exposed to the opening of the conductive pattern.   The method for manufacturing a wiring board according to claim 4, wherein, in the step of performing the desmear treatment, the structure is immersed in a swelling liquid and then immersed in an aqueous potassium permanganate solution at 45 ° C. or higher and 95 ° C. or lower.   2. The wiring board according to claim 1, wherein after the step of forming the opening, an opening area of the opening decreases from a surface of the solder resist layer opposite to the conductive pattern toward the conductive pattern. Manufacturing method. After the step of forming the opening,
Forming a plating film on the surface of the exposed conductive pattern;
The method for manufacturing a wiring board according to claim 1, further comprising: plasma processing the surface of the solder resist layer and the surface of the plating film in this order.   The method for manufacturing a wiring board according to claim 7, further comprising a step of melting and connecting a solder bump or an end portion of a bonding wire on the plating film. Preparing a structure having a substrate having a conductive pattern on at least one surface and a solder resist layer laminated on the substrate so as to cover the conductive pattern;
Forming an opening in the solder resist layer to expose a part of the conductive pattern;
On the exposed conductive pattern, a step of melting and fusing solder bumps or ends of bonding wires;
In this order,
The step of forming the opening includes a process of performing a sandblast process on a region of the solder resist layer where the opening is to be formed.   10. The method of manufacturing a semiconductor package according to claim 9, further comprising a step of performing a desmear process on a side wall portion defining the opening of the solder resist layer and a portion exposed to the opening of the conductive pattern.   The method of manufacturing a semiconductor package according to claim 9, further comprising a step of forming a plating film on the surface of the exposed conductive pattern.

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