JP6439960B2 - Insulating resin sheet, and circuit board and semiconductor package using the same - Google Patents

Description

  The present invention relates to an insulating resin sheet, and a circuit board and a semiconductor package using the insulating resin sheet.

  Currently, liquid type and molding materials are used for sealing ICs, wafers, passive components, and protective coatings.

  Liquid type materials have poor handling properties during printing and coating, and are difficult to handle. In addition, precise viscosity management and the like are required for controlling the coating amount, and thickness management is not easy, and there is a problem that the curing time is long. Furthermore, solventless materials have disadvantages such as difficulty in increasing the filling of the filler and limiting the curing agent. On the other hand, solvent-based materials have problems such as increasing the drying time.

  In addition, a molding material used for transfer molding is generally unsuitable for applications such as small-lot, high-mix production because a large amount of money is required for initial investment of a mold. In addition, since it has a tablet shape, flowability must be good, and when flowability is insufficient, control of molding conditions and material flowability such as thickness unevenness at the center and end portions is likely to occur. Is difficult.

  Thus, as a method for solving the above problems, an epoxy resin inorganic composite sheet containing an inorganic filler has been proposed (for example, Patent Document 1).

  With an epoxy resin inorganic composite sheet, if there is a simple press machine or laminator, it can be handled with a short time (several tens of seconds to several minutes), and the other steps add a necessary amount of heat using a dryer. Not only is the process simple, but it is also a clean process that is difficult to get your hands dirty. And the process which manufactures a semiconductor package using such an epoxy resin inorganic composite sheet is also reported (patent document 2).

JP 2006-124434 A JP 2009-60146 A Japanese Patent No. 5075157

  On the other hand, in recent years, with the increase in the density of electric circuits in the electric / electronic field, the wiring width has been reduced and the wiring interval has been reduced. Patent Document 3 discloses a method of forming a wiring circuit by selectively forming a circuit groove after forming a circuit groove in an insulating layer using a laser processing machine. In the case of forming a circuit by such a method, it is more advantageous in productivity because the processing speed can be increased if the laser processing property is excellent.

  However, in materials used for applications such as semiconductor packages and circuit boards, materials that have such high laser processability as well as handleability (flexibility) and high heat resistance as sheets are still achieved. The current situation is not.

  In order to solve such problems, the present inventors have intensively studied for the purpose of providing an insulating resin sheet having high laser processability in addition to handling and high heat resistance, and Achieved.

  That is, the insulating resin sheet according to one aspect of the present invention has an insulating layer, and the insulating layer contains a solid epoxy resin having two or more epoxy groups in one molecule and a liquid epoxy resin. The absorption coefficient of the cured resin composition is at least 300 cm-1 or more at 355 nm.

  Furthermore, in the insulating layer, a metal body is preferably embedded in a groove formed by laser processing from the outer surface.

  In the insulating resin sheet, it is preferable that the insulating layer further contains an inorganic filler.

  A circuit board according to another aspect of the present invention is characterized in that a circuit is further embedded in the insulating layer of the insulating resin sheet.

  A semiconductor package according to still another aspect of the present invention is characterized in that a circuit and a semiconductor element are further embedded in the insulating layer of the insulating resin sheet.

  A semiconductor package according to still another aspect of the present invention is a semiconductor device having an electrode on a main surface, a coating insulating layer covering the surface on which the electrode is formed, and laser processing from the outer surface side of the coating insulating layer A semiconductor package including a circuit in which a metal body is embedded in a groove formed by this, and a sealing resin layer formed on a back surface of the semiconductor element, wherein the covering insulating layer is the insulating resin sheet described above It is characterized by.

  In the semiconductor package, it is more preferable that the sealing resin layer includes a curable resin and an inorganic filler.

  Furthermore, in the semiconductor package, it is preferable that the sealing resin layer and the covering insulating layer are made of the same resin composition.

  According to the present invention, it is possible to obtain an insulating resin sheet having high laser workability (particularly, laser processing speed) in addition to handleability (flexibility) and high heat resistance. Moreover, a circuit board, a semiconductor package, etc. which have the outstanding characteristic can be obtained using the insulating resin sheet.

FIG. 1 is a schematic cross-sectional view for explaining each step in a method for manufacturing a semiconductor package according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view for explaining each step in the method of manufacturing a semiconductor package according to another embodiment of the present invention. FIG. 3 is a schematic cross-sectional view for explaining each step in the method of manufacturing a semiconductor package according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view schematically showing a semiconductor package obtained by the semiconductor package manufacturing method according to the embodiment of the present invention.

  Preferred embodiments according to the present invention will be specifically described below.

The insulating resin sheet according to the present embodiment (hereinafter sometimes simply referred to as a resin sheet) has an insulating layer, and the insulating layer is liquid with a solid epoxy resin having two or more epoxy groups in one molecule. It contains an epoxy resin, and the absorption coefficient of the cured resin composition is at least 300 cm ⁻¹ at 355 nm.

  Since the insulating layer has the above-described configuration, when forming a groove from the outer surface of the insulating layer, a very excellent workability can be exhibited, and thus it is suitable as a resin sheet for forming a groove. . In particular, the laser processing speed when forming grooves and the like by laser processing can be increased, and fine circuit formation by laser processing can be performed very efficiently. This is probably because the absorption efficiency of the cured resin composition is high, so that the laser beam absorption efficiency is increased and the processing efficiency is improved. In a groove formed by laser processing, for example, a metal body serving as a circuit or wiring can be embedded to form a circuit board, a semiconductor package, or the like.

  That is, the insulating resin sheet of this embodiment is preferably used as an insulating resin sheet for groove formation or embedded circuit formation, more preferably as an insulating resin sheet for laser processing.

  First, the material which comprises the insulating layer of the resin sheet of this embodiment is demonstrated.

  The insulating layer of this embodiment is composed of a resin composition containing an epoxy resin as a main component.

The epoxy resin used in this embodiment contains a solid epoxy resin and a liquid epoxy resin having two or more epoxy groups in one molecule, and the absorption coefficient of the cured resin composition is at least 355 nm. There is no particular limitation as long as it is 300 cm ⁻¹ or more. By including not only solid epoxy but also liquid epoxy, there is an advantage that the embedding property of circuits and parts is improved.

In the present embodiment, the absorption coefficient of the cured resin composition can be determined as follows. That is, the transmittance of a sample obtained by applying the resin composition before adding an additive such as a filler on a slide glass with a thickness of 10 μm using an applicator and effecting the effect at 200 ° C. for 60 minutes is expressed by the following formula: To calculate the absorption coefficient (α).
α (cm ⁻¹ ) = − d ⁻¹ · (−ln (% T / 100))
α: absorption coefficient (cm ⁻¹ )
d: Film thickness (cm)
% T: Transmittance (%)
If the absorption coefficient of the cured resin composition thus obtained is at least 300 cm ⁻¹ at 355 nm, the laser processing speed of the insulating layer can be improved. Although there is no limitation in particular about the upper limit of the said absorption coefficient, it is preferable that it is 1000 cm < ^-1 > or less from a viewpoint of the visibility of an alignment mark.

  Such an absorption coefficient can be adjusted by adjusting the compounding of an epoxy resin or an additive in the resin composition of the insulating layer. More specifically, for example, it is possible to appropriately select a polyfunctional epoxy resin having a naphthalene skeleton or a polycyclic aromatic skeleton excellent in UV absorption.

  The solid epoxy resin that can be used for the insulating resin layer of the present embodiment is an epoxy resin that is solid at room temperature and has two or more epoxy groups in one molecule. Specifically, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin, triphenylmethane type epoxy resin, dicyclopentadiene type epoxy resin, phenol aralkyl, biphenol aralkyl, tris Examples thereof include phenol type and naphthalene type polyfunctional epoxy. These may be used individually by 1 type according to a condition, and may be used in combination of 2 or more type.

  From the viewpoint of further improving the handleability of the sheet, it is preferable to use a solid epoxy having a softening point of 100 ° C. or lower. Furthermore, from the viewpoint of being superior in UV absorption, for example, a polyfunctional epoxy resin having a naphthalene skeleton, an aromatic polyfunctional epoxy resin crosslinked with an ethylene skeleton, or a polyfunctional epoxy resin having a polycyclic aromatic skeleton may be used. preferable.

  The liquid epoxy resin that can be used is an epoxy resin that has two or more epoxy groups in one molecule and is liquid at room temperature. Specifically, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, Examples thereof include alicyclic epoxy resins and hydrogenated bisphenol A type epoxy resins. From the viewpoint of further improving the embedding property of the component, it is preferable to use a liquid epoxy having a viscosity of 20000 cps or less. These may be used individually by 1 type according to a condition, and may be used in combination of 2 or more type.

  The combination of the solid epoxy resin and the liquid epoxy resin is not particularly limited as long as the absorption coefficient of the cured resin composition falls within the above range.

  In the total amount of the resin composition of the present embodiment, the epoxy resin is preferably 2 to 90% by mass, more preferably 5 to 80% by mass.

  In the case where a solid epoxy resin and a liquid epoxy resin are used in combination, the mixing ratio is not particularly limited, but it can usually be included at a ratio of about 55 to 95: 5 to 45.

  Furthermore, the insulating layer of the present embodiment may contain an inorganic filler.

  The inorganic filler that can be used in the present embodiment is not particularly limited. Examples of inorganic fillers include spherical silica, barium sulfate, silicon oxide powder, crushed silica, calcined talc, barium titanate, titanium oxide, clay, alumina, mica, boehmite, zinc borate, zinc stannate, and other metal oxides And metal hydrates. By including such an inorganic filler in the resin composition, the plating adhesion of the insulating resin sheet is improved.

  Among them, it is preferable to use spherical silica, and there are also advantages that both high filling of filler and fluidity can be achieved and the linear expansion coefficient of the insulating layer can be reduced.

  When an insulating layer contains an inorganic filler, content of the inorganic filler in the resin composition which comprises an insulating layer is 30-95 mass% with respect to the resin composition whole quantity, Furthermore, it is about 60-90 mass%. It is preferable.

  Moreover, the resin composition which comprises the insulating layer of this embodiment may contain components other than the above, for example, may contain a hardening | curing agent and / or a hardening accelerator.

  The curing agent that can be used is not particularly limited. Particularly, examples of the curing agent that can be preferably used as the curing agent for the epoxy resin include a phenol curing agent, an amine compound, an acid anhydride, an imidazole compound, a sulfide resin, and dicyandiamide. As mentioned. These may be used individually by 1 type according to a condition, and may be used in combination of 2 or more type.

  When using a hardening | curing agent in this embodiment, it is preferable that the epoxy equivalent of the epoxy resin to be used and the equivalent ratio of a hardening | curing agent are about 0.4-1.1.

  Further, the curing accelerator is not particularly limited. For example, imidazoles and derivatives thereof, organophosphorus compounds, metal soaps such as zinc octoate, secondary amines, and tertiary amines. A quaternary ammonium salt or the like can be used. These may be used individually by 1 type according to a condition, and may be used in combination of 2 or more type.

  When using a hardening accelerator in this embodiment, it is preferable that it is about 0.01-2 mass% in the resin composition whole quantity.

  The resin composition constituting the insulating layer of the present embodiment further includes other additives, for example, a silane coupling agent, a flame retardant, a flame retardant aid, a leveling agent, and a colorant, as long as the effects of the present invention are not impaired. Etc. may be contained as necessary.

  In addition, the resin composition as described above is usually prepared and used in a varnish form. Such a varnish is prepared as follows, for example.

  In other words, an organic solvent is blended in each component of the epoxy resin composition described above, and the inorganic filler and other additives are added as necessary, and dispersed uniformly using a ball mill, a bead mill, a mixer, a blender, or the like. -Can be mixed and prepared in a varnish form.

  Examples of the organic solvent include, but are not limited to, aromatic hydrocarbons such as benzene and toluene, amides such as N, N-dimethylformamide (DMF), ketones such as acetone and methyl ethyl ketone, methanol, ethanol, and the like. Alcohols, cellosolves and the like. These may be used alone or in combination of two or more.

  The resin sheet of the present embodiment is formed by applying the above-mentioned varnish-like resin composition onto a base material (for example, a carrier film such as PET (polyethylene terephthalate)) and drying by heating. Resin layer) can be formed.

  The thickness of the insulating layer formed in this way can be set as appropriate according to the use of the resin sheet, but is preferably about 5 to 500 μm from the viewpoint of handleability and residual solvent.

  The method, apparatus, and various conditions for forming the insulating layer may be the same as the conventional one, or various means as an improvement thereof.

  More specifically, for example, the substrate coated with the varnish-like resin composition is then heat-dried under desired heating conditions (eg, 70 to 150 ° C. for 2 to 15 minutes) to remove the solvent. The resin component can be semi-cured (B-staged) to obtain a resin sheet. Although the thickness of a resin layer changes with solid content and the viscosity of a varnish, it is preferable to adjust so that the thickness of the resin sheet after drying may be set to about 30-100 micrometers, for example.

  The insulating resin sheet of the present embodiment thus obtained is used for various electronic components obtained by a production method including a step of forming grooves by laser processing. In a groove formed by laser processing, for example, a metal body serving as a circuit or wiring can be embedded to form a circuit board, a semiconductor package, or the like.

  More specifically, for example, for a circuit board in which wiring or electrodes are further embedded in an insulating layer of an insulating resin sheet, or a semiconductor package in which circuits and semiconductor elements are further embedded in an insulating layer. It can be suitably used.

  Although the resin sheet of this embodiment changes with uses, it can be easily used by carrying out temporary press-bonding by a vacuum lamination on a predetermined base material, a board | substrate, and a semiconductor element, and hardening after that.

  In the present embodiment, the metal body (circuit) may be formed by any method, but examples include a method of applying electroless plating to a groove formed by a laser and a method of filling with a conductive paste.

  In addition, although there is no limitation in particular about the laser used for laser processing, a UV-YAG laser, an excimer laser, etc. can be illustrated. In particular, a UV-YAG laser having a good processing efficiency (for example, a wavelength of 355 nm) is preferably used.

  Below, the manufacturing method of the semiconductor package which concerns on this embodiment is demonstrated as a specific manufacture example.

  That is, a coating step of forming a coating insulating layer that covers the surface on which the electrode is formed of a semiconductor element having an electrode on the main surface, and a surface of the coating insulating layer on the electrode side of the semiconductor element A coating formation step for forming a resin coating, and a laser processing or machining on the coating insulating layer from the outer surface side of the resin coating, so that a recess reaching the surface of the electrode and a desired shape and depth A circuit pattern portion forming step for forming a circuit pattern portion including a circuit groove; a catalyst deposition step for depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion and the surface of the resin coating; and the coating A film peeling step for peeling the resin film from the insulating layer, and electroless plating on the coating insulating layer from which the resin film has been peeled to form a circuit electrically connected to the electrode. A method for manufacturing and a can processing step, first described.

  FIG. 1 is a schematic cross-sectional view for explaining each step in the method of manufacturing a semiconductor package according to this embodiment.

  First, a coating insulating layer is formed so as to embed the semiconductor element 11 having the electrode 11a on the main surface. The covering insulating layer is not particularly limited as long as it is an insulating layer that covers the semiconductor element 11 so as to be embedded therein. Specifically, as shown in FIG. What is comprised including the insulating layer 13 is mentioned. In this case, the insulating resin sheet of the present embodiment is used as the second insulating layer 13 that is the outer surface side of the covering insulating layer.

  Next, as illustrated in FIG. 1B, a resin coating 14 is formed on the surface of the covering insulating layer on the electrode 11 a side of the semiconductor element 11. The surface of the covering insulating layer on the electrode 11a side of the semiconductor element 11 is the surface of the second insulating layer 13 covering the electrode 11a of the semiconductor element 11 out of the surface of the covering insulating layer. This process corresponds to a film forming process.

  Next, as shown in FIG.1 (c), by carrying out laser processing from the outer surface side of the resin film 14 to the 2nd insulating layer 13 (layer comprised with the resin sheet of this embodiment) of a coating insulating layer, A circuit pattern portion 15 including a recess 15a reaching the surface of the electrode 11a and a circuit groove 15b having a desired shape and depth is formed. As a part of the circuit groove 15b, a concave portion for forming a land portion for ensuring electrical connection with a through hole or another electronic component may be formed. The circuit pattern portion 15 defines a portion where an electroless plating film is formed by electroless plating, that is, a portion where an electric circuit is formed. The laser processing or machining for forming the recess 15a is a drilling process for exposing the electrode 11a. In addition, the laser processing for forming the circuit groove 15 b is performed by cutting beyond the thickness of the resin coating 14 on the basis of the outer surface of the resin coating 14. This step corresponds to a circuit pattern portion forming step. In the present embodiment, since the insulating resin sheet of the present embodiment is used as the second insulating layer, the laser processability is extremely excellent, and the productivity is also excellent.

  Next, as shown in FIG. 1 (d), a plating catalyst or its precursor 16 is deposited on the surface of the circuit pattern portion 15 and the surface of the resin film 14 on which the circuit pattern portion 15 is not formed. This step corresponds to a catalyst deposition step.

  Next, as shown in FIG. 1 (e), after the circuit pattern portion 15 is formed from the surface of the covering insulating layer, specifically, the second insulating layer 13 covering the electrode 11 a of the semiconductor element 11, it remains. The resin coating 14 is peeled off. By doing so, the plating catalyst or its precursor 16 can remain only in the circuit pattern portion 15 of the second insulating layer 13. That is, the plating catalyst or the precursor 16a corresponding to the position can remain in the recess 15a, and the plating catalyst or the precursor 16b corresponding to the position can remain in the circuit groove 15b. On the other hand, the plating catalyst or its precursor deposited on the surface of the resin coating 14 is removed together with the resin coating 14 while being supported on the resin coating 14. This process corresponds to a film peeling process.

  Next, electroless plating is applied to the second insulating layer 13 from which the resin film 14 has been peeled off. By doing so, an electroless plating film is formed only in the portion where the plating catalyst or its precursor 16 remains. That is, as shown in FIG. 1F, an electroless plating film 17a corresponding to the position of the recess 15a and an electroless plating film 17b corresponding to the position of the circuit groove 15b are formed. This process corresponds to a plating process.

  The electroless plating film 17b corresponding to the position of the circuit groove 15b formed by the electroless plating may be an electric circuit as it is. Further, the electroless plating film 17b may not be an electric circuit as it is. In that case, electroless plating (fill-up plating) may be further applied to form an electric circuit.

  Note that the thickness of the electroless plating film 17b is not particularly limited. Specifically, the electroless plating film 17b may be formed so that the surface of the electroless plating film 17b is higher than the surface of the second insulating layer 13 as shown in FIG. The surface of the plating film 17 b may be formed to be the same as or lower than the surface of the second insulating layer 13.

  In addition, the electroless plating film 17a corresponding to the position of the recess 15a formed by the electroless plating serves as a via that ensures electrical connection between the electroless plating film 17b and the electrode 11a of the semiconductor element 11. It does not have to be a via as it is. If a via cannot be formed as it is, it may be made a via by further applying electroless plating (fill-up plating).

  According to such a manufacturing method, the circuit 17b is formed on the second insulating layer 13 (covering insulating layer) covering the semiconductor element 11, and the circuit 17b and the electrode 11a of the semiconductor element 11 are electrically connected. Therefore, the via can be formed with high accuracy.

  In addition, as shown in FIG. 1, the method for manufacturing a semiconductor package according to the present embodiment may form one layer of the rewiring circuit or may form two or more layers. Specifically, as shown in FIG. 1 (f), after forming an electric circuit, each of the above steps may be performed again to form two or more rewiring circuits.

  Finally, after forming the via 17a and the circuit 17b, an insulating layer 18 is separately formed on the second insulating layer 13 so as to cover the via 17a and the circuit 17b as shown in FIG. May be. Then, a recess reaching the circuit 17b is formed in the insulating layer 18, and bumps for ensuring electrical connection between other electronic components and the circuit of the semiconductor package and the circuit of the other wiring layer are formed in the recess. 19 may be formed. Further, when there are two or more semiconductor elements 11, a semiconductor package may be obtained by cutting between adjacent semiconductor elements. Further, the semiconductor package obtained by cutting in this way may include one semiconductor element 11 as shown in FIG. 1G, but is not limited thereto. For example, each semiconductor package may include two or more semiconductor elements. When two or more semiconductor elements are provided, the semiconductor elements may be semiconductor elements having the same type of function or semiconductor elements having different functions.

  In addition, by forming a wiring layer having a circuit electrically connected to the circuit of the semiconductor package on the semiconductor package, a semiconductor device having a so-called multilayer structure can be obtained. That is, a semiconductor device including a semiconductor package and having one or more wiring layers having a circuit electrically connected to the circuit of the semiconductor package is obtained.

  Further, as shown in FIG. 1 (f), the circuit 17 b is formed outside the outer edge of the shape in which the semiconductor element 11 is projected in the direction orthogonal to the main surface of the semiconductor element 11 with respect to the surface of the covering insulating layer. It is preferable that That is, it is preferable that the circuit 17 b is formed wider than the width of the semiconductor element 11. By doing so, it is easy to ensure electrical connection with other electronic components, and when manufacturing a semiconductor device having a multilayer structure, it is easy to ensure electrical connection with the circuit of the wiring layer. Furthermore, the obtained semiconductor package can increase the number of input / output terminals.

  As a method for manufacturing a semiconductor package according to the present embodiment, for example, the coating step as described above is a surface on the side opposite to the surface (circuit surface) on which an electrode is formed as a coating insulating layer. The manufacturing method which is the process of forming the coating insulating layer which exposes is mentioned.

  FIG. 2 is a schematic cross-sectional view for explaining each step in the method of manufacturing a semiconductor package according to the embodiment of the present invention.

  First, as shown in FIGS. 2A to 2C, a covering insulating layer 126 is formed to cover the surface (circuit surface) on which the electrode 114a is formed of the semiconductor element 114 having the electrode 114a on the main surface. To do. This step corresponds to a coating step. This covering step will be described later.

  Next, as illustrated in FIG. 2D, a resin film 118 is formed on the surface of the covering insulating layer 126. This process corresponds to a film forming process.

  Next, as shown in FIG. 2 (e), the laser processing is performed on the coating insulating layer 126 from the outer surface side of the resin coating 118, so that the recess 119a reaching the surface of the electrode 114a and the desired shape and depth are obtained. A circuit pattern portion 119 including the circuit groove 119b is formed. As a part of the circuit groove 119b, a concave portion for forming a land portion for ensuring electrical connection with a through hole or another electronic component may be formed. The circuit pattern portion 119 defines a portion where an electroless plating film is formed by electroless plating, that is, a portion where an electric circuit is formed. The laser processing for forming the recess 119a is a drilling process that exposes the electrode 11a. Further, in the laser processing for forming the circuit groove 119b, the outer surface of the resin film 118 is used as a reference to cut beyond the thickness of the resin film 118. This step corresponds to a circuit pattern portion forming step.

  Next, as shown in FIG. 2F, a plating catalyst or its precursor 120 is deposited on the surface of the circuit pattern portion 119 and the surface of the resin film 118 where the circuit pattern portion 119 is not formed. This step corresponds to a catalyst deposition step.

  Next, as shown in FIG. 2G, the resin film 118 remaining after the circuit pattern portion 119 is formed is peeled off from the surface of the covering insulating layer 126. By doing so, the plating catalyst or its precursor 120 can remain only in the circuit pattern portion 119 of the covering insulating layer 126. That is, the plating catalyst or precursor 120a corresponding to the position can remain in the recess 119a, and the plating catalyst or precursor 120b corresponding to the position can remain in the circuit groove 119b. On the other hand, the plating catalyst or its precursor deposited on the surface of the resin film 118 is removed together with the resin film 118 while being supported on the resin film 118. This process corresponds to a film peeling process.

  Next, electroless plating is applied to the coating insulating layer 126 from which the resin film 118 has been peeled off. By doing so, an electroless plating film is formed only on the portion where the plating catalyst or its precursor 120 remains. That is, as shown in FIG. 2H, the electroless plating film 120a corresponding to the position of the recess 119a is formed, and the electroless plating film 120b corresponding to the position of the circuit groove 119b is formed. This process corresponds to a plating process.

  The electroless plating film 121b corresponding to the position of the circuit groove 119b formed by this electroless plating may be an electric circuit as it is. Further, the electroless plating film 121b may not be an electric circuit as it is. In that case, electroless plating (fill-up plating) may be further applied to form an electric circuit.

  The thickness of the electroless plating film 121b is not particularly limited. Specifically, the electroless plating film 121b may be formed so that the surface of the electroless plating film 121b is flush with the surface of the coating insulating layer 126 as shown in FIG. In addition, the surface of the electroless plating film 121b may be formed higher than the surface of the covering insulating layer 126, or may be formed only lower.

  In addition, the electroless plating film 120a corresponding to the position of the recess 119a formed by the electroless plating serves as a via that ensures electrical connection between the electroless plating film 120b and the electrode 114a of the semiconductor element 114. It does not have to be a via as it is. If a via cannot be formed as it is, it may be made a via by further applying electroless plating (fill-up plating).

  According to such a manufacturing method, a circuit is formed on the insulating layer (covering insulating layer) 126 covering the semiconductor element 114, and vias for electrically connecting the circuit and the electrode 114a of the semiconductor element 114 are formed. Formation can be performed with high accuracy.

  In addition, as shown in FIG. 2, the method for manufacturing a semiconductor package according to this embodiment may form one layer of the rewiring circuit, or may form two or more layers. Specifically, as shown in FIG. 2 (h), after the electric circuit is formed, the above-described steps may be performed again to form two or more rewiring circuits.

  Finally, after forming the via 121a and the circuit 121b, as shown in FIG. 2I, an insulating layer 122 is separately formed on the covering insulating layer 126 so as to cover the via 121a and the circuit 121b. Also good. Then, a recess reaching the circuit 121b is formed in the insulating layer 122, and a bump for securing electrical connection between another electronic component or a circuit of this semiconductor package and a circuit of another wiring layer is formed in the recess. 123 may be formed. When there are two or more semiconductor elements 114, a semiconductor package may be formed by cutting between adjacent semiconductor elements. In addition, the semiconductor package obtained by cutting in this way may include one semiconductor element 114 as shown in FIG. 2I, but is not limited thereto. For example, each semiconductor package may include two or more semiconductor elements. When two or more semiconductor elements are provided, the semiconductor elements may be semiconductor elements having the same type of function or semiconductor elements having different functions.

  In addition, by forming a wiring layer having a circuit electrically connected to the circuit of the semiconductor package on the semiconductor package, a semiconductor device having a so-called multilayer structure can be obtained. That is, a semiconductor device including a semiconductor package and having one or more wiring layers having a circuit electrically connected to the circuit of the semiconductor package is obtained.

  Further, as shown in FIG. 2I, the circuit 121b is formed outside the outer edge of the shape in which the semiconductor element 114 is projected in the direction orthogonal to the main surface of the semiconductor element 114 with respect to the surface of the covering insulating layer. It is preferable that That is, it is preferable that the circuit 121b be formed wider than the width of the semiconductor element 114. By doing so, it is easy to ensure electrical connection with other electronic components, and when manufacturing a semiconductor device having a multilayer structure, it is easy to ensure electrical connection with the circuit of the wiring layer.

  Next, the coating process of this embodiment will be described.

  Specifically, the covering step is performed so that a surface of at least one of the semiconductor elements opposite to a surface on which the electrode is formed is in contact with a predetermined position of the support. An adhesion step for adhering the semiconductor element to a body, a sealing resin coating step for covering the surface on which the electrode is formed of the semiconductor element adhered to the support with a sealing resin, and the sealing And a curing step of curing the stop resin to form a covering insulating layer.

  First, as shown in FIG. 2A, the surface of at least one semiconductor element 114 opposite to the surface on which the electrode 114a is formed is in contact with a predetermined position of the support 111. Then, the semiconductor element 114 is attached to the support 111. In addition, this process is corresponded to the sticking process. The support 111 is not particularly limited as long as it can attach a semiconductor element.

  Moreover, it is preferable that this support body 111 is not only capable of adhering a semiconductor element but also removable so that the semiconductor element can be fixed or peeled off. If the support 111 is detachable from such a semiconductor element, the support 111 can be obtained, for example, by peeling after the coating step, more specifically after the curing step of the coating step, and the like. In the semiconductor package, the surface of the semiconductor element 114 opposite to the surface on which the electrode 114a is formed is exposed. By doing so, a semiconductor package excellent in heat dissipation can be obtained. Moreover, if the timing which peels the support body 111 is after a coating process, it will not be specifically limited. Specifically, it may be after the film formation step, immediately before the plating treatment step, or after the plating treatment. From the viewpoint of reducing the influence of heat generated in each step and protecting the semiconductor element and the like, the step after the coating step is preferable.

  Specific examples of the support 111 include a support 111 as shown in FIG. The support 111 includes a base 112 and a layer 113 on which at least one surface of the base 112 can be attached and detached with a semiconductor element. The layer 113 from which the semiconductor element can be attached and detached includes, for example, a layer having adhesiveness or adhesiveness to the semiconductor element. More specifically, an adhesive layer made of a silicone-based resin, an adhesive layer made of a rubber-based adhesive, an adhesive layer made of an acrylic adhesive, an adhesive layer made of a urethane-based adhesive, and the like can be mentioned. Among these, a pressure-sensitive adhesive layer made of a silicone-based resin is preferable in terms of heat resistance, ease of attaching / detaching a semiconductor element (removability), and chemical resistance. Note that the base material 112 is not particularly limited as long as it can hold the layer 113 to which the semiconductor element can be attached and detached and can maintain the shape during the coating process. Specific examples include a glass substrate, a ceramic substrate, an organic substrate, and a metal plate such as a stainless steel (SUS) plate.

  Next, as shown in FIGS. 2B and 2C, the sealing resin 116 is coated so as to cover the surface of the semiconductor element 114 attached to the support 111 where the electrode 114a is formed. Cover with. This step corresponds to a sealing resin coating step.

  In the case of this embodiment, the insulating resin sheet of this embodiment is used as the sealing resin 116 that forms the covering insulating layer 126.

  That is, as shown in FIG. 2B, the resin sheet 115 including the sealing resin 116 and the base material 117 that supports the sealing resin 116 is covered and pressed to be attached to the support 111. A step of covering the surface of the semiconductor element 114 on which the electrode 114a is formed with the sealing resin 116 is preferably used.

  Finally, as shown in FIG. 2C, the sealing resin 116 is cured to form the covering insulating layer 126. Conditions for curing the sealing resin 116 are not particularly limited, and the above-described conditions can be used as appropriate.

  By applying such a coating process as the coating process, the coating process can be easily performed. Therefore, the semiconductor package manufacturing method according to the present embodiment can be easily performed. As shown in FIG. 2C, the covering insulating layer 126 has both a sealing layer that covers the electrodes of the semiconductor element and a wiring layer that forms wiring.

  Moreover, since the covering step including the curing step for forming the covering insulating layer is performed in a state in which the semiconductor element is attached to the support and the position of the semiconductor element is maintained, the occurrence of deviation of the semiconductor element can be suppressed. . In addition, since a coating process including a curing process for forming a coating insulating layer is performed with the semiconductor element attached to the support, a structure in which the semiconductor element is coated with the coating insulating layer due to the presence of the support. The occurrence of warping can also be suppressed.

  As a further embodiment, a semiconductor element having an electrode on a main surface, a coating insulating layer covering the surface on which the electrode is formed, and a metal formed in a groove formed by laser processing from the outer surface side of the coating insulating layer In a semiconductor package including a circuit in which a body is embedded and a sealing resin layer formed on the back surface of the semiconductor element, the insulating resin sheet of this embodiment can also be suitably used as a covering insulating layer.

  As a method for manufacturing such a semiconductor package according to the present embodiment, for example, the covering step forms a covering insulating layer having a convex portion of a predetermined shape on the electrode side surface of the semiconductor element as the covering insulating layer. The manufacturing method which is a process and a circuit pattern part formation process reaches the surface of a convex part as a circuit groove, and is a process of forming the circuit groove connected with the recessed part is mentioned. Specifically, in the method for manufacturing a semiconductor package according to the fourth embodiment of the present invention, a semiconductor element having an electrode is embedded on the main surface so as to be embedded, and a predetermined surface is formed on the electrode side surface of the semiconductor element. A coating step of forming a coating insulating layer having convex portions of the shape; a film forming step of forming a resin coating on the electrode side surface of the semiconductor element of the coating insulating layer; and an outer surface of the resin coating A circuit that forms a circuit pattern portion including a recess reaching the surface of the electrode and a circuit groove having a desired shape and depth reaching the surface of the electrode by laser processing the coating insulating layer from the side. A pattern forming step, a catalyst depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion and the surface of the resin coating, and a coating stripping step of stripping the resin coating from the coating insulating layer And said By performing electroless plating on said cover insulating layer fat coating has been peeled off, the electrode and is electrically connected, and a plating treatment step of forming a circuit extending up onto the convex portion.

  FIG. 3 is a schematic cross-sectional view for explaining each step in the method of manufacturing a semiconductor package according to the embodiment of the present invention.

  First, as shown in FIGS. 3A to 3G, a semiconductor element 213 having an electrode 213a on the main surface is covered so as to be embedded, and the surface of the semiconductor element 213 on the electrode 213a side has a predetermined shape. A covering insulating layer 222 having a convex portion 212a is formed. The covering insulating layer 222 is not particularly limited as long as the insulating layer 222 covers the semiconductor element 213 so as to be embedded and has a predetermined-shaped convex portion 212a on the surface of the semiconductor element 213 on the electrode 213a side. Specifically, as shown in FIG. 3G, the fifth insulating layer 212 includes an fifth insulating layer 212 and a sixth insulating layer 215, and the fifth insulating layer 212 is an insulating layer having a convex portion 212a having a predetermined shape. And the like. The convex portion 212a is not particularly limited. For example, as will be described later, the convex portion 212a is a base for forming a circuit 220b on the convex portion 212a and forming a solder bump 221 on the circuit 220b. Is mentioned. That is, a convex portion or the like in which the structure including the convex portion 212 a, the circuit 220 b, and the solder bump 221 serves as a bump for connecting the semiconductor element 213 can be given. This step corresponds to a coating step. This covering step will be described later.

  Next, as illustrated in FIG. 3H, a resin coating 217 is formed on the surface of the covering insulating layer 222 on the electrode 213 a side of the semiconductor element 213. The surface of the covering insulating layer 222 on the electrode 213 a side of the semiconductor element 213 is the surface of the fifth insulating layer 212 covering the electrode 213 a of the semiconductor element 213 among the surfaces of the covering insulating layer 222. This process corresponds to a film forming process. Here, the resin sheet of the present embodiment is used as the fifth insulating layer 212. Thereby, the workability of laser processing performed later is improved, and the productivity is also increased.

  Next, as shown in FIG. 3I, laser processing is performed on the coating insulating layer 222 from the outer surface side of the resin coating 217 to reach the concave portion 218a reaching the surface of the electrode 213a and the convex portion 212a. Then, the circuit pattern portion 218 including the circuit groove 218b having a desired shape and depth is formed. As a part of the circuit groove 218b, a concave portion for forming a land portion for ensuring electrical connection with a through hole or another electronic component may be formed. Further, the circuit pattern portion 218 defines a portion where an electroless plating film is formed by electroless plating, that is, a portion where an electric circuit is formed. The laser processing for forming the recess 218a is a drilling process for exposing the electrode 218a. In the laser processing for forming the circuit groove 218b, the outer surface of the resin film 217 is used as a reference to cut beyond the thickness of the resin film 217. This step corresponds to a circuit pattern portion forming step.

  Next, as shown in FIG. 3 (j), a plating catalyst or its precursor 219 is deposited on the surface of the circuit pattern portion 218 and the surface of the resin coating 217. This step corresponds to a catalyst deposition step.

  Next, as shown in FIG. 3 (k), after the circuit pattern portion 218 is formed from the surface of the covering insulating layer 222, specifically, the fifth insulating layer 212 that covers the electrode 213a of the semiconductor element 213, it remains. The resin coating 217 is peeled off. By doing so, the plating catalyst or its precursor 219 can remain only in the circuit pattern portion 218 of the fifth insulating layer 212. That is, the plating catalyst or the precursor 219a corresponding to the position can remain in the recess 218a, and the plating catalyst or the precursor 219b corresponding to the position can remain in the circuit groove 218b. On the other hand, the plating catalyst or its precursor deposited on the surface of the resin coating 217 is removed together with the resin coating 217 while being supported on the resin coating 217. This process corresponds to a film peeling process.

  Next, electroless plating is applied to the fifth insulating layer 212 of the covering insulating layer 222 from which the resin coating 217 has been peeled off. By doing so, as shown in FIG. 3L, a circuit is formed which is electrically connected to the electrode 213a of the semiconductor element 213 and reaches the convex portion 212a. That is, the electroless plating film 220a corresponding to the position of the recess 218a and the electroless plating film 220b corresponding to the position of the circuit groove 218b are formed. The electroless plating film 220b corresponding to the position of the circuit groove 218b is also formed on the convex portion 212a of the fifth insulating layer 212. This process corresponds to a plating process.

  The electroless plating film 220b formed by this electroless plating and corresponding to the position of the circuit groove 218b may be an electric circuit as it is. Further, the electroless plating film 220b may not be an electric circuit as it is. In that case, electroless plating (fill-up plating) may be further applied to form an electric circuit.

  In addition, the electroless plating film 220a corresponding to the position of the recess 218a formed by this electroless plating serves as a via that ensures electrical connection between the electroless plating film 220b and the electrode 213a of the semiconductor element 213. It does not have to be a via as it is. If a via cannot be formed as it is, it may be made a via by further applying electroless plating (fill-up plating).

  According to such a manufacturing method, the circuit 220b is formed on the fifth insulating layer 212 of the covering insulating layer 222 covering the semiconductor element 213, and the circuit 220b and the electrode 213a of the semiconductor element 213 are electrically connected. Therefore, the via can be formed with high accuracy.

  In addition, as shown in FIG. 3, the method for manufacturing a semiconductor package according to the present embodiment may form one layer of the redistribution circuit, or may form two or more layers. Specifically, as shown in FIG. 3L, after forming an electric circuit, the above-described steps may be performed again to form two or more rewiring circuits.

  Finally, when there are two or more semiconductor elements 213, a conductor package may be formed by cutting between adjacent semiconductor elements. In addition, the semiconductor package obtained by cutting in this way may include one semiconductor element, but is not limited thereto. For example, each semiconductor package may include two or more semiconductor elements. When two or more semiconductor elements are provided, the semiconductor elements may be semiconductor elements having the same type of function or semiconductor elements having different functions.

  Also, as shown in FIG. 4, it is preferable to form solder bumps 221 on a circuit 220b formed on the convex portion 212a. By doing so, vias and circuits can be formed with higher accuracy. This is considered to be because the amount of solder for securing electrical connection between the semiconductor element and other electronic components can be reduced. That is, it is considered that the electrical connection between the semiconductor element and other electronic components can be ensured even if the solder amount of the solder bump is reduced in order to reduce the pitch of the solder bump. As a result, it is considered that the occurrence of a solder bridge due to the connection of adjacent solder bumps can be suppressed, and thus the occurrence of an electrical short circuit due to this solder bridge can be suppressed. As a result, it is considered that vias and circuits can be formed with higher accuracy. FIG. 4 is a schematic cross-sectional view schematically showing a semiconductor package obtained by the semiconductor package manufacturing method according to the embodiment of the present invention. This semiconductor package has solder bumps 221 formed thereon. That is, it is as follows.

  In the obtained semiconductor package, convex portions such as resin bumps are formed on the surface side of the covering insulating layer on which the circuit is formed. That is, the convex part is formed in the rewiring layer. In the semiconductor package, rewiring is also formed on the convex portion, and a solder bump or the like is mounted on the convex portion. Regarding the mounting of the semiconductor package on an electronic component such as a circuit board, the semiconductor package is connected via bumps mounted on the convex portion. Thus, since solder bumps are formed on convex portions such as resin bumps, solder corresponding to the height of the convex portions is formed rather than forming solder bumps on the surface where the convex portions are not formed, that is, on a plane. Less bump solder is required. This makes it possible to reduce solder bumps. That is, electrical connection between the electronic component and the semiconductor package can be realized by bump connection at a narrow pitch. Therefore, it contributes to the improvement of connection reliability. Furthermore, since a circuit pattern can be formed also on the side surface of the resin bump which is a convex portion, wiring can be formed with high density.

  In addition, by forming a wiring layer having a circuit electrically connected to the circuit of the semiconductor package on the semiconductor package, a semiconductor device having a so-called multilayer structure can be obtained. That is, a semiconductor device including a semiconductor package and having one or more wiring layers having a circuit electrically connected to the circuit of the semiconductor package is obtained.

  Further, as shown in FIG. 3L, the circuit 220b has a shape in which the semiconductor element 213 is projected in a direction perpendicular to the main surface of the semiconductor element 213 with respect to the surface of the fifth insulating layer 212 of the covering insulating layer 222. It is preferable that it is formed even outside the outer edge. In other words, the circuit 220b is preferably formed wider than the width of the semiconductor element 213. By doing so, it is easy to ensure electrical connection with other electronic components, and when manufacturing a semiconductor device having a multilayer structure, it is easy to ensure electrical connection with the circuit of the wiring layer.

  Next, the coating process of this embodiment will be described.

  The covering step is a step in which the semiconductor element 213 is covered so as to be embedded, and the covering insulating layer 222 having the convex portion 212a having a predetermined shape can be formed on the surface of the semiconductor element 213 on the electrode 213a side. There is no particular limitation. Specifically, in the covering step, a fifth insulating layer forming step of forming a fifth insulating layer on the surface of the support having a concave portion corresponding to the convex portion, and the electrode of the semiconductor element are formed. An adhesion step of adhering at least one or more of the semiconductor elements to the fifth insulating layer, and an adhesive surface adhered to the fifth insulating layer so that the surface being in contact with the fifth insulating layer A sealing resin coating step of covering with a sealing resin so as to embed a semiconductor element; and a curing step of curing the sealing resin to form the sixth insulating layer by forming the sixth insulating layer. And a support peeling step of peeling the support from the covering insulating layer.

  First, as shown in FIGS. 3A and 3B, a fifth insulating layer 212 is formed on the surface of a support 211 having a recess 211a corresponding to the protrusion 212a. The formation of the fifth insulating layer 212 is not particularly limited as long as the fifth insulating layer 212 to which the shape of the concave portion 211 a of the support 211 is transferred can be formed on the support 211. This step corresponds to the fifth insulating layer forming step.

  If this support body 211 has the recessed part 211a corresponding to the convex part 212a, it will not specifically limit. For example, a metal plate such as a stainless steel (SUS) plate in which the concave portion 211a is formed by an etching process, an organic base material in which the concave portion 211a is formed, and the like can be given. Further, the support 211 may be a surface that has been subjected to a release treatment in order to enhance the releasability from the fifth insulating layer 212, and a surface that is coated with a releasable coating agent. There may be.

  Moreover, the 5th insulating layer 212 is formed with the resin sheet of this embodiment as mentioned above. Conditions for curing the fifth insulating layer 212 are not particularly limited, and the above-described conditions can be used as appropriate.

  Next, as shown in FIG. 3C, at least one or more semiconductor elements 213 are formed so that the surface of the semiconductor element 213 on which the electrode 213a is formed is in contact with the fifth insulating layer. Affixed to the insulating layer 212. In addition, this process is corresponded to the sticking process.

  Next, as shown in FIGS. 3D and 3E, the semiconductor element 213 attached to the fifth insulating layer 212 is covered with a sealing resin 215 so as to be embedded. This step corresponds to a sealing resin coating step. This sealing resin coating step may be a step of applying a sealing resin, but as shown in FIGS. 3D and 3E, the sealing resin 215 and the sealing resin 215 are supported. A step of covering with a sealing resin 215 so as to embed the semiconductor element 213 attached to the fifth insulating layer 212 by covering and pressing a resin sheet or resin film 214 made of the base material 216 to be pressed, etc. Is preferably used. When such a resin sheet or resin film 214 is used, a large area can be easily covered, so that the number of semiconductor elements that can be covered can be increased. That is, it is possible to increase the number of semiconductor packages that can be manufactured simultaneously. In addition, when the resin sheet or the resin film 214 is used, the first insulating layer to be formed is preferable from the viewpoint of ensuring the thickness accuracy in the workpiece surface, for example, when manufacturing in a large format. In addition, it does not specifically limit as sealing resin, That is, it is not restricted to such a resin sheet or resin film, For example, a powder sealing material and a liquid sealing material can be used. Moreover, this powder sealing material or liquid sealing material can be used as the sealing resin when the sealing resin coating step is performed in the step of applying the sealing resin.

  The sealing resin 215 is not particularly limited as long as the insulating layer can be formed by curing or the like after covering the semiconductor element 213 attached to the fifth insulating layer 212 so as to be embedded. Specifically, examples of the sealing resin 215 include those that can form the sixth insulating layer 215 as shown in FIG. Moreover, it is preferable that the sealing resin 215 is a resin sheet or a resin film containing a curable resin. With such a sealing resin, as described above, since a large area can be easily covered, the number of semiconductor elements that can be covered can be increased. Moreover, it is preferable that the sealing resin 215 includes not only the sealing resin but also a filler. And as this filler, if it is a filler contained in sealing resin, it will not specifically limit. Examples thereof include inorganic fillers such as inorganic fine particles, and organic fine particles. Moreover, as a filler, an inorganic filler is preferable. That is, the sealing resin 25 is more preferably a resin sheet or a resin film containing a curable resin and an inorganic filler. If it is such sealing resin, generation | occurrence | production of the curvature with the obtained insulating layer and another insulating layer, a semiconductor element, etc. can be suppressed. This is considered to be because the thermal expansion coefficient with other insulating layers and semiconductor elements can be approximated by the contained inorganic filler. From these, by using a resin sheet or resin film containing a curable resin and an inorganic filler as the sealing resin 215, from the viewpoint of heat resistance, low warpage of the molded product, and low thermal linear expansion, preferable. In addition, the curable resin included in the sealing resin 215 is, for example, heat such as epoxy resin, acrylic resin, polycarbonate resin, polyimide resin, polyphenylene sulfide resin, polyphenylene ether resin, cyanate resin, benzoxazine resin, and bismaleimide resin. Examples thereof include curable resins. Further, the inorganic filler contained in the sealing resin 15 is not particularly limited as long as it can be adjusted to match the thermal expansion coefficient with other insulating layers, semiconductor elements, and the like. Examples include inorganic fine particles. The organic fine particles contained in the sealing resin 215 are not particularly limited as long as they can relieve stress generated during heat due to the difference in coefficient of thermal expansion with other insulating layers, semiconductor elements, and the like. Examples thereof include rubber particles. The base material 216 here is not particularly limited as long as the shape can be maintained by pressing the resin sheet or the resin film 224. Specific examples include an organic substrate such as a PET substrate, a glass substrate, and a metal plate such as a SUS plate. In addition, the substrate 216 may be a surface that has been subjected to a release treatment in order to enhance the releasability from the sealing resin 215, or a surface that is coated with a releasable coating agent. May be.

  More preferably, in this embodiment, it is desirable that the sealing resin layer and the covering insulating layer are made of the same resin composition. By doing so, since the thermal expansion coefficient (CTE) of a sealing resin layer and a coating insulating layer corresponds, it is thought that the curvature in a semiconductor package can be reduced more.

  Next, the sealing resin 215 is cured to form the sixth insulating layer 215. By doing so, the covering insulating layer 222 including the fifth insulating layer 212 and the sixth insulating layer 215 is formed. Conditions for curing the sealing resin 215 are not particularly limited. If the curable resin contained in the sealing resin 215 is a thermosetting resin, it may be a heating condition that can cure the resin. This process corresponds to a curing process. Then, as shown in FIG.3 (f), you may peel the base material 216 of the resin sheet or the resin film 214. FIG. The substrate 216 may not be peeled off, and may be peeled after the support peeling step.

  Finally, as shown in FIG. 3G, the support 211 is peeled from the fifth insulating layer 212 of the covering insulating layer 222. By doing so, the covering insulating layer 222 is formed. This process corresponds to a support peeling process.

  By applying such a coating process as the coating process, the coating process can be easily performed. That is, it is possible to easily form a coating insulating layer having a predetermined convex portion. Therefore, the semiconductor package manufacturing method according to the present embodiment can be easily performed.

  In addition, in a state where the semiconductor element 213 is attached to one insulating layer constituting the covering insulating layer 222, specifically, the fifth insulating layer 212, the sixth insulating layer 215 which is the other insulating layer is formed. Since the covering insulating layer 222 is formed, the occurrence of deviation of the semiconductor element 213 can be suppressed. In addition, since the covering process is performed in a state where the semiconductor element 213 is fixed to the fifth insulating layer 212, warpage occurs in the structure in which the semiconductor element is covered with the covering insulating layer due to the presence of the fifth insulating layer 212. It can also be suppressed.

As described above, according to one aspect of the present invention, the insulating resin sheet having an insulating layer includes a solid epoxy resin having two or more epoxy groups in one molecule and a liquid epoxy resin. And the absorption coefficient of the cured resin composition is at least 300 cm ⁻¹ or more at 355 nm. With such a configuration, laser processability, particularly laser processing speed, is extremely improved. By using the resin sheet of the present invention, the productivity of circuits and semiconductor packages is greatly improved. Moreover, it is thought that the embedding property of a circuit or an electronic component improves by using together a solid epoxy resin and a liquid epoxy resin in this way.

  Furthermore, in the insulating layer, a metal body is preferably embedded in a groove formed by laser processing from the outer surface. In such an embodiment, the effects of the present invention can be more exerted.

  In the insulating resin sheet, it is preferable that the insulating layer further contains an inorganic filler. Thereby, the plating adhesion of the resin sheet is improved.

  A circuit board according to another aspect of the present invention is characterized in that a circuit is further embedded in the insulating layer of the insulating resin sheet. In such an embodiment, the effects of the present invention can be more exerted.

  A semiconductor package according to still another aspect of the present invention is characterized in that a circuit and a semiconductor element are further embedded in the insulating layer of the insulating resin sheet. In such an embodiment, the effects of the present invention can be more exerted.

  A semiconductor package according to still another aspect of the present invention is a semiconductor device having an electrode on a main surface, a coating insulating layer covering the surface on which the electrode is formed, and laser processing from the outer surface side of the coating insulating layer A semiconductor package including a circuit in which a metal body is embedded in a groove formed by this, and a sealing resin layer formed on a back surface of the semiconductor element, wherein the covering insulating layer is the insulating resin sheet described above It is characterized by. In such an embodiment, the effects of the present invention can be more exerted.

  In the semiconductor package, it is more preferable that the sealing resin layer includes a curable resin and an inorganic filler. Thereby, in addition to the above-mentioned effects, it is considered that the adhesion and the reliability of the circuit are further improved.

  Furthermore, in the semiconductor package, it is preferable that the sealing resin layer and the covering insulating layer are made of the same resin composition. Thereby, in addition to the above effects, it is considered that the warpage of the semiconductor package can be further suppressed.

  The present invention will be described more specifically with reference to examples, but the present invention is not limited to these examples.

First, the materials used in this example are as follows.
・ Solid epoxy resin: Polyfunctional epoxy resin having naphthalene skeleton, “HP4710” DIC ・ Solid epoxy resin: Triphenylmethane type polyfunctional epoxy resin, “EPPN502H” manufactured by Nippon Kayaku ・ Solid epoxy resin: Trisphenol Type polyfunctional epoxy resin, "VG3101" Printec, liquid epoxy resin: bisphenol A type liquid epoxy resin, "850S" DIC, amine curing agent: dicyandiamide, Nippon Carbide, phenol curing agent: α, α-bis (4-Hydroxyphenyl) -4- (4-hydroxy-α, α-dimethylbenzyl) -ethylbenzene, “TrisP-PA” manufactured by Honshu Chemical Co., Ltd., curing accelerator: 2-ethyl-4-methylimidazole, “2E4MZ”, Shikoku Kasei Chemical & Silane Coupling Agent: 3-Glycidoxy B pills trimethoxysilane, "KBM403" manufactured by Shin-Etsu Chemical Co., a leveling agent: fluorine-based leveling agent, "F477" manufactured by DIC Inorganic filler: spherical silica "SO-C2" Admatechs Ltd. (average particle size 0.5 [mu] m)
・ Solvent: Methyl ethyl ketone (MEK)
・ Solvent: Dimethylformamide (DMF)

[Example 1]
<Manufacture of insulating resin sheet>
The material was dissolved in a solvent with the formulation shown in Formulation Example 1 in Table 1 below to obtain a resin varnish. The obtained resin varnish was coated on a 38 μm-thick PET carrier film subjected to a release treatment with a bar coater and dried at 130 ° C. for 5 minutes to remove the solvent. The resin thickness of the obtained insulating resin sheet with a carrier was 40 μm.

  Ten cuts were made with a cutter knife at intervals of 1 mm in this resin sheet with a carrier, and when the sheet was checked for cracks / chips, there were no cracks / chips.

  Further, after curing the resin sheet at 200 ° C. for 60 minutes and peeling it from the carrier film, the resin sheet was measured for the viscoelastic behavior in the tensile mode of the “DMS6100” apparatus of SII Nanotechnology, and the glass transition temperature (Tg ) Was measured to show 220 ° C. Tg was a maximum value of 10 Hz and tan δ.

<Measurement of absorption coefficient of cured resin composition>
The resin composition before adding the filler was applied to a glass slide with a thickness of 10 μm using an applicator, and the transmittance of a sample effected at 200 ° C. for 60 minutes was measured. Was calculated.
α (cm ⁻¹ ) = − d ⁻¹ · (−ln (% T / 100))
α: absorption coefficient (cm ⁻¹ )
d: Film thickness (cm)
% T: Transmittance (%)
The absorption coefficient in Example 1 was 600 cm ⁻¹ .

<Laser workability evaluation substrate fabrication>
The obtained resin sheet was bonded to a 0.8 mm thick copper clad laminate obtained by etching away a 18 μm thick copper foil by a vacuum laminator, and the carrier film was peeled off. Cured for 60 minutes. The obtained laminated plate was used as a laser processability evaluation substrate.

<Laser workability evaluation>
Using the UV-YAG laser (manufactured by esi) having a wavelength of 355 nm, the time required to process 5 m of a groove having a depth of 15 μm was measured, and it was only 16 seconds.

[Example 2]
An insulating resin sheet with a carrier was prepared in the same manner as in Example 1 except that the formulation shown in Formulation Example 2 in Table 1 below was changed. Similarly to Example 1, the absorption coefficient, cracks / chips in the sheet, and the cured product Tg and laser processability were evaluated. As a result, the absorption coefficient was 300 cm ⁻¹ , the sheet was not cracked or chipped, and the cured product Tg was 210 ° C. The laser processing speed was 16 seconds, which was the same processing speed as in Example 1.

[Example 3]
An insulating resin sheet with a carrier was prepared in the same manner as in Example 1 except that the formulation shown in Formulation Example 3 in Table 1 below was changed. Similarly to Example 1, the absorption coefficient, cracks / chips in the sheet, and the cured product Tg and laser processability were evaluated. As a result, the absorption coefficient was 300 cm ⁻¹ , the sheet was not cracked or chipped, and the cured product Tg was 210 ° C. The laser processing speed was 16 seconds, which was the same processing speed as in Example 1.

[Comparative Example 1]
An insulating resin sheet with a carrier was prepared in the same manner as in Example 1 except that the formulation shown in Formulation Example 4 in Table 1 below was changed. Similarly to Example 1, the absorption coefficient, cracks / chips in the sheet, and the cured product Tg and laser processability were evaluated. As a result, there was no cracking or chipping of the sheet, and the cured product Tg was 218 ° C., but the absorption coefficient was 60 cm ⁻¹ , the laser processing speed was 48 seconds, and three times longer than that of Example 1. did.

表中、配合の数値はいずれも質量部である。

In the table, the numerical values of the blending are parts by mass.

  From the above results, it was shown that the laser processability (laser processing speed) can be improved by using the insulating resin sheet of the present invention. Thus, it is considered that fine circuit formation can be efficiently performed by improving the laser processability. Moreover, plating adhesion could be improved by further including an inorganic filler in the insulating layer of the resin sheet.

Claims (8)

An insulating resin sheet having an insulating layer,
The insulating layer contains a solid epoxy resin and a liquid epoxy resin having two or more epoxy groups in one molecule ,
In the insulating layer, the ratio of the content of naphthalene type polyfunctional epoxy resin to the total amount of the solid epoxy resin and liquid epoxy resin is (naphthalene type polyfunctional epoxy resin) / (solid epoxy resin and liquid epoxy resin). (Total with epoxy resin) = 25 / 89.5-20 / 62.8,
Wherein the absorption coefficient of the cured product of the resin composition is 300 cm ^-1 or more 1000 cm ^-1 or less at least a wavelength 355 nm, the insulating resin sheet for laser processing.   The insulating resin sheet for laser processing according to claim 1, wherein a metal body is embedded in a groove formed by laser processing from the outer surface of the insulating layer.   The insulating resin sheet for laser processing according to claim 1, wherein the insulating layer further contains an inorganic filler.   The circuit board by which a circuit is further embedded in the said insulating layer of the insulating resin sheet for laser processing in any one of Claims 1-3.   A semiconductor package in which a circuit and a semiconductor element are further embedded in the insulating layer of the insulating resin sheet for laser processing according to claim 1.   A semiconductor element having an electrode on a main surface, a coating insulating layer covering the surface on which the electrode is formed, and a metal body embedded in a groove formed by laser processing from the outer surface side of the coating insulating layer A semiconductor package comprising a sealing resin layer formed on a back surface of a circuit and the semiconductor element, wherein the covering insulating layer is the insulating resin sheet for laser processing according to any one of claims 1 to 3 package.   The semiconductor package according to claim 6, wherein the sealing resin layer includes a curable resin and an inorganic filler.   The semiconductor package according to claim 6 or 7, wherein the sealing resin layer and the covering insulating layer are made of the same resin composition.

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