JP2018019071A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which achieves excellent electrical connection reliability when assuming that manufacturing efficiency of the semiconductor device is improved without using a mechanical technique for exposure of a conductor post.SOLUTION: A semiconductor device manufacturing method of the present embodiment includes in the following order: a conductor part formation step of forming on a substrate 10 having a conductor pattern 20, a plurality of conductor parts 40 having the same heights from a surface of the substrate 10; a coating step of introducing a thermosetting resin composition 50 to each clearance between neighboring conductor parts 40 and covering he conductor parts 40 by a hardened material 60 of the thermosetting resin composition 50 in such a manner as to expose tops 92 of the conductor parts 40; and a multilayer wiring step of forming on the hardened material 60, a metal pattern to be electrically connected with the tops 92 without grinding a surface of the hardened material 60.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a typical conventional wiring board manufacturing process, a conductor post is formed on a substrate and then pre-molded so as to cover the entire surface of the conductor post opposite to the side on which the substrate is disposed. A part of the resin layer obtained by polishing was removed by polishing to expose the surface of the conductor post, and then a wiring pattern was formed so as to be electrically connected to the conductor post (Patent Document) 1).

  In a conventional typical rewiring process, after forming a conductor post on an electrode pad of a semiconductor chip, the periphery of the obtained structure is molded with a sealing material, and then the surface of the conductor post is exposed. A part of the sealing material is polished and removed, and then a rewiring layer is formed so as to be electrically connected to the conductor post (Patent Document 2).

International Publication No. 2010/116615 Pamphlet JP, 2006-66649, A

In the conventional manufacturing processes described in Patent Documents 1 and 2, a conductor embedded in a sealing material using a large-scale device in order to ensure electrical connectivity of a finally obtained semiconductor device It was necessary to polish and remove the sealing material so that the surface of the post was exposed.
By the way, regarding the manufacturing process of a semiconductor device, in recent years, a higher technical level is required from the viewpoint of productivity. When the conductor post is exposed by a mechanical method such as the polishing removal process described above, there is a disadvantage that the productivity of the semiconductor device is lowered. This is because high accuracy is required for polishing the sealing material.

  Accordingly, the present invention provides a method for manufacturing a semiconductor device having excellent electrical connection reliability on the premise that the manufacturing efficiency of the semiconductor device is improved by not using a mechanical technique for exposing the conductor posts.

According to the present invention, on the substrate, a conductor portion forming step of forming a plurality of conductor portions having the same height from the surface of the substrate;
A coating step of introducing a thermosetting resin composition into the gap between adjacent conductor portions and covering with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed;
A method of manufacturing a semiconductor device is provided, which includes, in this order, a multilayer wiring step of forming a metal pattern electrically connected to the top portion on the cured product without polishing the surface of the cured product.

According to the present invention, a plurality of conductor portions are formed on a semiconductor chip, and the semiconductor chip and the conductor portions are placed on the support body so that the heights of the plurality of conductor portions from the support body are the same. A conductor part forming step to be disposed on;
A covering step of introducing a thermosetting resin composition into a gap existing between the adjacent conductor portions and covering the conductor portion with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed. When,
Including, in this order, a multilayer wiring step of forming a metal pattern electrically connected to the top on the cured product without polishing the surface of the cured product,
After the covering step, there is provided a method for manufacturing a semiconductor device, further comprising a separation step of separating the support and the cured product.

According to the present invention, forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor chip on the substrate or the semiconductor chip;
On the substrate or the semiconductor chip, introducing a thermosetting resin composition in a fluidized state into a gap existing between the adjacent conductor portions;
The thermosetting resin composition in a fluidized state is cured so that substantially the entire surface of the conductor portion facing the gap is covered with a cured product obtained by curing the thermosetting resin composition. Process,
After the step of curing, without polishing the surface of the cured product, forming a metal pattern in contact with the conductor portion;
In this order,
The step of curing is a step of obtaining any structure in the following state (a) or (b):
When the structure is in the state (a) below,
In the step of forming the metal pattern, the metal pattern is formed so as to contact the top,
When the structure is in the state (b) below,
Before the step of forming the metal pattern, further comprising the step of exposing the top by removing the skin layer by means other than polishing,
In the step of forming the metal pattern, there is provided a method for manufacturing a semiconductor device, wherein the metal pattern is formed so as to be in contact with the exposed top portion.
(A) A state in which a top portion of the conductor portion located in the height direction of the conductor portion is exposed. (B) A skin layer made of the cured product on the top portion of the conductor portion located in the height direction of the conductor portion. Is attached

  Accordingly, the present invention provides a method for manufacturing a semiconductor device having excellent electrical connection reliability on the premise that the manufacturing efficiency of the semiconductor device is improved by not using a mechanical technique for exposing the conductor posts.

It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure for demonstrating an example of the manufacturing method of the semiconductor device which concerns on a reference example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

The manufacturing method of the semiconductor device according to the present embodiment includes the following four steps in this order.
The first step is a step of forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor chip on the substrate or the semiconductor chip.
The second step is a step of introducing a thermosetting resin composition that is in a fluid state into a gap that exists between adjacent conductor portions on the substrate or semiconductor chip.
In the third step, the thermosetting resin composition in a fluidized state is covered with a cured product obtained by curing the thermosetting resin composition so that substantially the entire surface of the conductor portion facing the gap is covered. Is a step of curing.
A 4th process is a process of forming the metal pattern which touches a conductor part, without grind | polishing the surface of hardened | cured material after the said hardening process.
In the method for manufacturing a semiconductor device according to the present embodiment, the third step (step of curing) is a step of obtaining one of the structures in the following state (a) or (b). In the method for manufacturing a semiconductor device according to the present embodiment, when the structure is in the following state (a), in the fourth step (step of forming a metal pattern), the top of the conductor portion is contacted. A metal pattern is formed on the substrate. On the other hand, when the structure is in the state of (b) below, the method further includes a step of removing the skin layer by means other than polishing to expose the top before the step of forming the metal pattern, In the step (step of forming the metal pattern), the metal pattern is formed so as to be in contact with the top of the conductor portion.
(A) State in which the top of the conductor portion located in the height direction of the conductor portion is exposed (b) State in which a skin layer made of a cured product adheres to the top portion of the conductor portion located in the height direction of the conductor portion

  Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment (hereinafter also referred to as the present manufacturing method) will be described with reference to the drawings.

<First Embodiment>
The semiconductor device manufacturing method according to the first embodiment includes a conductor portion forming step of forming a plurality of conductor portions having the same height from the surface of the substrate on the substrate, and a gap between the adjacent conductor portions. A coating step of covering the conductor portion with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed, and polishing the surface of the cured product And a multilayer wiring process for forming a metal pattern electrically connected to the top on the cured product in this order.
Moreover, you may include the isolation | separation process which isolate | separates a board | substrate after a multilayer wiring process.
In this manufacturing method, a plurality of conductor portions having the same height from the surface of the substrate are formed on the substrate. This manufacturing method will be described with reference to FIGS. 1 to 4 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the present embodiment.

(Conductor formation process)
In the conductor portion forming step, a plurality of conductor portions 40 having the same height from the surface of the substrate 10 are formed on the substrate 10.
First, the board | substrate 10 and the conductor part 40 are demonstrated.

<Substrate 10>
First, the substrate 10 is prepared. As the substrate 10, a known substrate can be used as long as it has characteristics such as flatness, rigidity, and heat resistance. Specific examples of the substrate 10 include a metal plate.
Specific examples of the metal plate include a copper plate, an aluminum plate, an iron plate, a steel (steel) plate, a nickel plate, a copper alloy plate, a 42 alloy plate, and a stainless plate.
The steel plate may be a cold rolled steel plate such as SPCC (Steel Plate Cold Commercial).
Note that a carrier foil made of the above-described metal plate material may be formed on the substrate 10.

The size of the substrate 10 may be such a size that only one semiconductor element can be arranged on the plane, or may be a size that can arrange a plurality of semiconductor elements on the plane. As the size of the substrate 10, for example, a size that allows a plurality of semiconductor elements to be arranged on the plane is preferable. Thereby, the same processing can be performed on a plurality of semiconductor devices. Therefore, it is convenient from the viewpoint of improving the production efficiency of the semiconductor device.
Further, the planar shape of the substrate 10 in a top view may be, for example, a rectangular shape or a circular shape. The planar shape of the substrate 10 in a top view is preferably a rectangular shape from the viewpoint of productivity, for example. Thereby, the handling of the substrate 10 in the manufacturing process of the semiconductor device is facilitated, and the productivity of the semiconductor device can be improved.
Further, the shape of the substrate 10 may be, for example, a single wafer processed into a frame shape, or a continuous body processed into a hoop shape.

<Conductor 40>
A plurality of conductor portions 40 are formed on the surface of the substrate 10. The plurality of conductor portions have the same height from the surface of the substrate 10.
The conductor portion 40 is constituted by the first conductor pattern 20 and the second conductor pattern 30.
For example, the first conductor pattern 20 is an electric circuit formed on the substrate 10.
Further, the second conductor pattern 30 is, for example, a metal pillar. With the second conductor pattern 30 that is a metal pillar, the metal pattern and the first conductor pattern 20 that are formed in a multilayer wiring process to be described later can be electrically connected to form a semiconductor device including the multilayer wiring.
The second conductor pattern may be, for example, the metal pillar 91 itself, or may be formed by forming the solder bump 90 on the metal pillar 91. A second conductor pattern 30 shown in FIG. 1B described later is formed by forming solder bumps 90 on metal pillars 91. The second conductor pattern 30 may be a metal pillar 91 itself as shown in FIG.
Further, the shape of the second conductor pattern 30 formed in this manufacturing method is the same as that of the second conductor pattern 30 shown in FIG. 1B and FIG. 4 from the viewpoint of realizing a semiconductor device corresponding to a narrow pitch. In addition, a pillar shape, that is, a columnar shape is preferable.
In addition, it does not limit as columnar shape, Specifically, it can be set as prismatic shape, cylindrical shape, etc.

Hereinafter, a method for forming a plurality of conductor portions having the same height from the surface of the substrate will be described.
First, as shown in FIG. 1A, a plurality of first conductor patterns 20 are formed on a substrate 10. Next, as shown in FIG. 1B, a second conductor pattern 30 is formed on the first conductor pattern 20.
The first conductor pattern 20 and the second conductor pattern 30 can be formed by, for example, a photolithography method. Here, the height of the conductor portion 40 from the surface of the substrate 10 is adjusted to be the same by adjusting the shapes of the first conductor pattern and the second conductor pattern. In this manufacturing method, a plurality of conductor portions 40 having the same height from the surface of the substrate 10 can be formed in this way. Hereinafter, a specific method for forming the conductor portion 40 by photolithography will be described by taking the case of forming the first conductor pattern 20 as an example.

<Photolithography method>
First, a photosensitive resin film made of a photosensitive resin composition is formed on the substrate 10.
Here, as a photosensitive resin composition, the well-known material used for a plating resist can be used. Examples of such known materials include photosensitive materials such as photoresists, resist inks, and dry films. The photosensitive resin composition may be a negative type or a positive type.
As a method for forming the photosensitive resin film, specifically, a varnish-like photosensitive resin composition is applied on the substrate 10 using a coater, a spinner, or the like, and the obtained coating film is dried. For example, a method of laminating a resin sheet made of a conductive resin composition on the substrate 10 by thermocompression bonding or the like may be used.
Next, an opening having a predetermined opening pattern is formed in the photosensitive resin film. Examples of the method for forming the opening include an exposure development method and a laser processing method.
Next, the formed opening is embedded with a metal film. Examples of the burying method include an electroless plating method and a plating method. Specific examples of the material for forming the metal film include copper, copper alloy, 42 alloy, nickel, iron, chromium, tungsten, gold, and solder. Of the above specific examples, for example, copper is preferably used as the metal film.
Next, the photosensitive resin film is removed. As a method for removing the photosensitive resin film, a method of removing the photosensitive resin film using a stripping solution, an ashing treatment, and further removing the residue of the photosensitive resin film adhering to the base with the stripping solution. The method of doing is mentioned. As a method for removing the photosensitive resin film, from the viewpoint of improving the production efficiency of the semiconductor device, it is preferable to employ a method of peeling the photosensitive resin film using a stripping solution. Specific examples of the stripping solution include organic sulfonic acid-based stripping solutions containing alkylbenzene sulfonic acid, organic amine-based stripping solutions containing organic amines such as monoethanolamine, and organic alkalis and fluorine compounds with respect to water. An aqueous resist stripping solution mixed with the above.
A metal film having a desired shape can be obtained by the photolithography method described above.

In the present embodiment, a metal film having a desired shape obtained by the photolithography method described above can be used as the first conductor pattern 20 and the second conductor pattern 30. That is, the first conductor pattern 20 and the second conductor pattern 30 can be formed by, for example, a photolithography method. By using the photolithography method, the conductor portions 40 can be formed with high accuracy so that the heights of the plurality of conductor portions 40 are the same from the surface of the substrate.
As shown in FIG. 1B, as a method of obtaining the second conductor pattern 30 formed by forming the solder bump 90 on the metal pillar 91, a metal film having a desired shape obtained by photolithography is used. That is, a method of forming the solder bump 90 on the pillar 91 by a known method can be mentioned.

(Coating process)
In the covering step, the thermosetting resin composition is introduced into the gap between the adjacent conductor portions, and the conductor portion is covered with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed. That is, a part of the conductor part is covered so that the top part of the conductor part is exposed.
Note that the state where the top portion 92 is exposed means that a step formed at the joining portion of the conductor portion 40 and the cured product 60 is buried with another insulating member before the metal pattern 160 is formed in a multilayer wiring forming process described later. The state where the top portion 92 is exposed to the extent that it does not have to be included is included.

In the covering step, first, as shown in FIG. 1C, a thermosetting resin composition 50 in a fluid state is introduced into a gap existing between adjacent conductor portions 40 on the substrate 10.
Here, specific examples of the method for introducing the thermosetting resin composition in a fluid state include a transfer molding method, a compression molding method, an injection molding method, and a lamination molding method.
Among the above specific examples, the transfer molding method, the compression molding method, or the lamination molding method is preferable from the viewpoint of forming the insulating resin layer without leaving an unfilled portion in the gap between the adjacent conductor portions 40 on the substrate 10.
In order to use the transfer molding method, the compression molding method, or the lamination molding method, the shape of the thermosetting resin composition before the fluidized state is, for example, a granule shape, a powder shape, a tablet shape, or a sheet shape. preferable.

The arrangement of the substrate 10 and the conductor part 40 when introducing the thermosetting resin composition 50 will be described.
The substrate 10 and the conductor part 40 are preferably arranged so that the surface of the cured product 60 is flush with the surface of the top part 92 of the conductor part 40. That is, the cured product 60 is preferably formed such that the surface of the cured product 60 is flush with the surface of the top portion 92 of the conductor portion 40. Thereby, the structure which does not have a level | step difference in the junction part of the hardened | cured material 60 and the conductor part 40 can be produced, in the state which the top part 92 located in the height direction of the conductor part 40 is exposed.

Moreover, when introducing the thermosetting resin composition 50, it is preferable to arrange | position the release film 100 so that it may press with respect to the top part 92 of the conductor part 40, for example, as shown in FIG.1 (d). Thereby, the top part 92 of the conductor part 40 can be protected by the release film 100. Therefore, it can suppress that the hardened | cured material 60 of a thermosetting resin composition adheres on the top part 92 of the conductor part 40, and the reliability of the electrical connection of a semiconductor device falls. The details of the release film 100 will be described later.
The timing of disposing the release film 100 may be before the introduction of the thermosetting resin composition 50 in a fluid state, or may be the same timing as the introduction of the thermosetting resin composition 50 in a fluid state. Alternatively, after introducing the thermosetting resin composition 50 in a fluid state as shown in FIG. 1 (d), it may be before the thermosetting resin composition 50 is made into a cured product 60. That is, the timing at which the release film 100 is disposed may be before the thermosetting resin composition 50 is the cured product 60.
As will be described later, the release film is removed after the thermosetting resin composition is cured to obtain a cured product 60.

<Release film 100>
It does not limit as the release film 100, What is used for mold release of a thermosetting resin composition can be used. Specific examples of the release film 100 include a fluorine-based release film and a polyester-based release film.
When the method of introducing the thermosetting resin composition in a fluidized state is a compression molding method, it is preferable to use a fluorine-based release film. Moreover, when the method of introducing the thermosetting resin composition in a fluidized state is a lamination molding method, it is preferable to use a polyester-based release film. Thereby, when a thermosetting resin composition contains an epoxy resin, the release film 100 can express suitable mold release property with respect to a thermosetting resin composition.
Specific examples of commercially available fluorine release films include Aflex (registered trademark) 50KN144NT manufactured by Asahi Glass Co., Ltd.

  About the release film 100, it is preferable that the surface pressed with respect to the top part 92 of the conductor part 40 is not embossed, in other words, is smooth. That is, the release film 100 preferably has a surface that has not been embossed, in other words, has a mirror surface. Thereby, about the surface of the hardened | cured material 60, a wave | undulation can be suppressed from a macro viewpoint and it can be made smooth. Therefore, it is possible to suppress the circuit skip of the metal pattern 160 formed in the multilayer wiring process described later, and to improve the reliability of electrical connection. Specifically, even when the circuit line width / line interval (L / S) of the metal pattern 160 is as fine as about 12/12 μm, the reliability of electrical connection can be maintained at a high level.

The lower limit value of the arithmetic average surface roughness Ra of the surface pressed against the top portion 92 of the release film 100 can be, for example, 0 μm or more, preferably 0.01 μm or more, and preferably 0.1 μm or more. It is more preferable that the thickness is 0.15 μm or more. Thereby, about the surface of the hardened | cured material 60, an unevenness | corrugation can be formed from a micro viewpoint. Therefore, in the adhesion between the metal pattern 160 formed in the multilayer wiring process described later and the cured product 60, an anchor effect is exhibited, and the adhesion strength between the metal pattern 160 and the cured product 60 can be improved.
Further, the upper limit value of the arithmetic average surface roughness Ra of the surface pressed against the top portion 92 of the release film 100 is, for example, preferably 1.5 μm or less, more preferably 0.5 μm or less, 0 It is more preferably 4 μm or less, still more preferably 0.3 μm or less, and even more preferably 0.28 μm or less.
In addition, arithmetic mean surface roughness Ra can be measured by the method based on JIS-B0601-1994, for example.

After introducing the thermosetting resin composition into the gap between the adjacent conductor portions, the thermosetting resin composition 50 is cured to obtain a cured product 60. The cured product 60 serves as an insulating resin layer.
As shown in FIG.1 (e), it is preferable that the hardened | cured material 60 is formed so that the whole surface except the top part among the surfaces of the conductor part 40 may be covered, for example. Thereby, it can suppress that the conductor part 40 contacts other than the metal pattern 160 formed in the multilayer wiring process mentioned later. Therefore, it is preferable from the viewpoint of ensuring the insulation reliability of the semiconductor device.
Here, the thermosetting resin composition is in a cured state of the B stage when introduced into the gap between adjacent conductor portions. Further, when the thermosetting resin composition 50 is cured to obtain a cured product 60, the C stage is in a cured state. That is, the cured state of the cured product is the cured state of the C stage.
The conditions for introducing the thermosetting resin composition vary depending on the molding method. When using the compression molding method, for example, the molding temperature is preferably 50 ° C. or higher and 200 ° C. or lower, and more preferably 80 ° C. or higher and 180 ° C. or lower. When using the compression molding method, the molding time is preferably 30 seconds or longer and 15 minutes or shorter, more preferably 1 minute or longer and 10 minutes or shorter. Moreover, when using the compression molding method, the molding pressure is preferably 0.5 MPa or more and 12 MPa or less, and more preferably 1 MPa or more and 10 MPa or less.
When the lamination molding method is used, for example, the pressing is performed in two stages, and the conditions for the first stage are, for example, a molding temperature of 60 ° C. or more and 130 ° C. or less, a molding time of 30 seconds or more and 10 minutes or less, and a molding pressure of 0. The press conditions for the second stage can be a molding temperature of 80 ° C. or more and 150 ° C. or less, a molding time of 30 seconds or more and 10 minutes or less, and a molding pressure of 0.2 MPa or more and 15 MPa or less.
By setting the molding temperature, pressure, and time in the above ranges at the time of molding, it is possible to prevent unfilled portions of the thermosetting resin composition 50 from occurring in the gaps between the adjacent conductor portions 40.
In the present embodiment, the B stage cured state (semi-cured state) of the thermosetting resin composition means that the reaction rate calculated by differential scanning calorimetry (DSC) measurement exceeds 0% and 70. % Or less.
In the present embodiment, the cured state of the C-stage of the thermosetting resin composition means that the reaction rate calculated by differential scanning calorimetry exceeds 70% and is 100% or less.
Here, how to obtain the reaction rate will be described. First, a temperature profile is measured by DSC measurement for the thermosetting resin composition before being introduced into the gap between the conductor portions 40. The calorific value calculated per unit mass of the exothermic peak of the curing reaction calculated from the temperature profile of the curing reaction obtained in this way is defined as A [mJ / mg]. Subsequently, also about the thermosetting resin composition which calculates a reaction rate, the emitted-heat amount B [mJ / mg] converted per unit mass of the exothermic peak of hardening reaction is calculated similarly. Using the above A and B, the reaction rate is obtained from the following equation.
(Formula) (Reaction rate) = B / A × 100 [%]
Moreover, the conditions which harden the thermosetting resin composition 50 and set it as the hardened | cured material 60 can be performed by heat-processing at 150 degreeC or more and 200 degrees C or less for 1 hour or more and 6 hours or less, for example.

  When forming an insulating resin layer made of the cured product 60 using a compression molding method as a molding method, it is preferable to perform resin sealing by reducing the pressure inside the mold, and more preferably under vacuum.

  The glass transition temperature of the cured product 60 is, for example, preferably from 100 ° C. to 250 ° C., and more preferably from 130 ° C. to 220 ° C. When the glass transition temperature of the hardened | cured material 60 is in the said numerical range, it can suppress that curvature generate | occur | produces in a semiconductor device.

In this embodiment, when the top part 92 of the conductor part 40 is protected by the release film 100, the cured product 60 of the thermosetting resin composition adheres to the top part 92, and the reliability of electrical connection is lowered to some extent. Can be suppressed. However, as a result of studying that the release film 100 is used to protect the top portion 92 of the conductor portion 40, the present inventors have used only the release film 100 to manufacture a plurality of semiconductor devices. For example, it has been found that there is a disadvantage that the thermosetting resin composition enters between the release film 100 and the conductor portion. When there is such inconvenience, a skin layer composed of a cured product 60 of the thermosetting resin composition is formed on the top portion 92 of the conductor portion 40. The skin layer has an insulating property, and when the skin layer is attached to the top portion 92, the reliability of the electrical connection of the semiconductor device is reduced.
The state where the skin layer is attached refers to a state where a film of the thermosetting resin composition is formed on the surface of the top portion 92. The thickness of the skin layer is on the order of several μm at the maximum.
In FIG. 1-4, the skin layer is not shown.

  In the conventional manufacturing method of a semiconductor device, the cured product 60 is formed so as to embed the conductor portion 40, and the cured product 60 is polished by a mechanical method such as mechanical polishing or chemical mechanical polishing, and the conductor portion 40 is then formed. It was exposed. As a result of examining the removal of the skin layer by a conventional mechanical method, the present inventors have found that there is room for improvement in terms of accuracy and production efficiency in order to remove the skin layer of the order of several μm. did. As a result of studying a method capable of removing the skin layer without reducing the productivity, the present inventors have found that it is effective to perform a chemical method such as a chemical treatment or an etching treatment. Thereby, the skin layer can be removed without reducing the productivity of the semiconductor device. Further, when the skin layer is removed by a chemical method, the cured product 60 is not greatly shaved, so that the conductor 40 can be covered with the cured product 60 of the thermosetting resin composition 50 so that the top of the conductor 40 is exposed. .

Specific examples of the chemical treatment include cleaning with an alkaline permanganate aqueous solution. Specific examples of the alkaline permanganate aqueous solution include a potassium permanganate aqueous solution and a sodium permanganate aqueous solution.
The etching process is specifically cleaning with an etching solution. Specific examples of the etchant include those containing sulfuric acid and hydrogen peroxide.

  In this manufacturing method, when the structure shown in FIG. 1 (f) is in a state in which the skin layer made of the cured product 60 is adhered on the top portion 92 described above, that is, in the state (b) described above, finally. In order to ensure the reliability of electrical connection of the obtained semiconductor device, before forming the metal pattern described later, a chemical such as an alkaline permanganate aqueous solution such as potassium permanganate or sodium permanganate, sulfuric acid Further, it is necessary to remove the skin layer by means other than polishing using an etching solution containing hydrogen peroxide and the like to expose the top portion 92. In other words, when the structure shown in FIG. 1 (f) is in the state of (b) described above, it is necessary to include a step of exposing the top portion 92 by performing a chemical treatment or an etching treatment to remove the skin layer. There is.

After the thermosetting resin composition 50 is cured to obtain a cured product 60, the release film 100 is peeled from the surface of the cured product 60 as shown in FIG.
At this time, the release film 100 may be peeled after reducing the adhesion between the release film 100 and the cured product 60. Specifically, the release layer of the release film 100 forming the adhesion site is deteriorated by, for example, performing ultraviolet irradiation or heat treatment on the adhesion site between the release film 100 and the cured product 60. It may be peeled off after reducing the adhesion. In addition, when the release film 100 is provided with sufficient release properties, ultraviolet irradiation or heat treatment may not be performed.

By forming the cured product 60 using the release film 100, the surface roughness of the cured product 60 can be controlled.
Before the multilayer wiring process described later, the lower limit value of the arithmetic average surface roughness Ra of the surface on which the top portion 92 of the cured product 60 is exposed can be set to 0.02 μm or more, for example, or 0.05 μm or more. Thereby, about the surface of the hardened | cured material 60, an unevenness | corrugation can be formed from a micro viewpoint. Therefore, the anchor effect is exhibited, and the adhesion strength between the metal pattern 160 formed in the multilayer wiring process described later and the cured product 60 can be improved.
Further, before the multilayer wiring process, the upper limit value of the arithmetic average surface roughness Ra of the surface from which the top portion 92 of the cured product 60 is exposed is preferably 0.8 μm or less, for example, 0.6 μm or less. More preferably, it is 0.2 μm or less, more preferably 0.15 μm or less.
In addition, arithmetic mean surface roughness Ra of the surface in which the top part 92 of the hardened | cured material 60 exists can be measured by the method based on JIS-B0601-1994.

In the present embodiment, the cured product 60 obtained by curing the thermosetting resin composition covers substantially the entire surface of the conductor portion 40 facing the gap existing between the adjacent conductor portions 40. The thermosetting resin composition 50 in a fluid state is cured. Thus, it is not necessary to go through a step of polishing the cured product by a mechanical method, which has been employed in a conventional semiconductor device manufacturing process, before a multilayer wiring step described later. Therefore, the productivity of the semiconductor device can be improved.
Therefore, in the present manufacturing method, the gap is taken into consideration in consideration of the size of the gap existing between the adjacent conductor portions 40 on the substrate 10 and the size of the molding space provided in the mold to be used, that is, the volume. It is important to calculate in advance the amount of the thermosetting resin composition 50 in a fluid state to be introduced and prepare an amount of the thermosetting resin composition 50 commensurate with the obtained calculation result. Moreover, it is preferable to use what has the shaping | molding space designed so that the dimension of the board | substrate 10 might be used for the metal mold | die used for this manufacturing method. By doing so, in the previous stage of curing the thermosetting resin composition 50 in a fluidized state, the thermosetting resin composition 50 flows into the side where the conductor portion 40 of the substrate 10 is not formed. As a result, it is possible to prevent the height of the obtained cured product 60 from the surface of the substrate 10 from deviating from the design value.

In the above description, the covering step has been described with reference to FIGS. 1C to 1F, but the manufacturing method is not limited to the above-described example.
In this manufacturing method, for example, a method using a mold in which the release film 100 is previously disposed in the molding space may be employed. An example will be described below.
First, the mold release film 100 is arrange | positioned in the shaping | molding space of a metal mold | die. Next, a predetermined amount of the thermosetting resin composition 50 in a fluid state is introduced onto the surface of the release film 100 disposed inside the mold. Next, the structure is placed in the mold so that the top portion 92 of the conductor portion 40 included in the structure shown in FIG. 1B is pressed against the surface of the release film 100. By doing so, the thermosetting resin composition 50 that is in a fluid state can be introduced evenly with respect to the gap that exists between the adjacent conductor portions 40 on the substrate 10. Next, the thermosetting resin composition 50 in a fluid state is cured.

In this embodiment, from the viewpoint of forming the metal pattern 160 having excellent adhesion to the cured product 60 in a multilayer wiring process described later, before the step of forming the metal pattern 160, for example, the cured product 60 is used. The surface may be roughened. Here, a chemical method or a physical method is mentioned as a method of roughening the surface of the cured product 60. Here, as a chemical method, the method of performing a chemical | medical solution process with respect to the surface of the hardened | cured material 60 is mentioned. Moreover, plasma treatment is mentioned as a physical method. Here, when the structure shown in FIG. 1F in which the skin layer made of the cured product 60 is attached on the top portion 92 described above is obtained, the skin layer is improved from the viewpoint of improving the manufacturing efficiency of the semiconductor device. And the chemical treatment performed on the surface of the cured product 60 may be simultaneously performed using the same chemical. By doing so, the surface state of the cured product 60 can be modified while exposing the top portion 92 of the conductor portion 40.
In the present manufacturing method, the chemical treatment performed on the surface of the cured product 60 is performed when the cured product 60 is formed using a thermosetting resin composition containing a mold release agent. The adhesiveness with respect to the hardened | cured material 60 of the metal pattern 160 obtained by a process can be made still better. Moreover, as a chemical | medical agent which can be used for a chemical | medical solution process, alkaline permanganate aqueous solution, such as potassium permanganate and sodium permanganate, is mentioned, for example. Thereby, about the surface of the hardened | cured material 60, an unevenness | corrugation can be formed from a micro viewpoint. Therefore, the anchor effect is exhibited, and the adhesion strength between the metal pattern 160 formed in the multilayer wiring process described later and the cured product 60 can be improved.
Moreover, as a method of physically roughening the surface of the cured product 60, a method of performing plasma treatment on the surface of the cured product 60 can be mentioned. In the present manufacturing method, the plasma treatment described above, particularly when the cured product 60 is formed using a thermosetting resin composition containing a release agent, is a cured product 60 of a metal pattern 160 obtained by a process described later. It is possible to further improve the adhesion to the. This is presumably because the surface of the cured product 60 can form irregularities from a microscopic viewpoint, and the metal pattern penetrates into the irregularities of the cured product 60 to develop the anchor effect. In such plasma processing, for example, an inert gas such as argon gas, an oxidizing gas, or a fluorine-based gas can be used as a processing gas. Examples of the oxidizing gas include O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, and NO ₂ gas.

(Multilayer wiring process)
In the multilayer wiring process, the metal pattern 160 electrically connected to the top portion 92 is formed on the cured product 60 without polishing the surface of the cured product 60. Thereby, the wiring of an electric circuit can be multilayered, suppressing that the productivity of a semiconductor device falls.
Here, polishing the surface of the cured product 60 means a mechanical method such as mechanical polishing or chemical mechanical polishing.
As shown in FIGS. 2A to 2D, the metal pattern 160 is formed on the surface of the substrate 10 on which the conductor portion 40 is formed without polishing the surface of the cured product 60. . Specifically, in the present manufacturing method, the exposed top portion 92 and the metal pattern 160 are electrically connected by the method shown in FIGS. 2 (a) to 2 (d).
Details will be described below.

  In the multilayer wiring process, before the metal pattern 160 is formed on the cured product 60, for example, as shown in FIG. 2A, the cured product 60 and the conductor part 40 on the substrate 10 are arranged. An adhesion assistant may be applied to the surface on the side, that is, the surface on which the metal pattern 160 on the cured product 60 is formed, to form the layer 80 made of the adhesion assistant. Thereby, the adhesiveness of the metal pattern 160 and the hardened | cured material 60 can further be improved.

<Adhesion aid>
The adhesion assistant is not limited, and known ones can be used.
As the adhesion assistant, for example, a silane coupling agent or a triazole compound can be used.
Specific examples of the silane coupling agent include 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldiethoxysilane, and 3-glycidoxypropyltriethoxysilane. P-styryltrimethoxysilane, 3-methacryloxypropylmethyldimethoxysilane, 3-methacryloxypropyltrimethoxysilane, 3-methacryloxypropylmethyldiethoxysilane, 3-methacryloxypropyltriethoxysilane, 3-acryloxypropyl Trimethoxysilane, N-2- (aminoethyl) -3-aminopropylmethyldimethoxysilane, N-2- (aminoethyl) -3-aminopropyltrimethoxysilane, N-2- (aminoethyl) -3-amino Propyltrie Xysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, N-phenyl-3-aminopropyltrimethoxysilane, 3-mercaptopropylmethyldimethoxysilane, 3-mercaptopropyltrimethoxysilane, bis (triethoxy Propyl) tetrasulfide, 3-isocyanatopropyltriethoxysilane and the like.
Specific examples of the triazole compound include 4-amino-1,2,4-triazole, 4H-1,2,4-triazole-3-amine, 4-amino-3,5-di-2-pyridyl- 4H-1,2,4-triazole, 3- (methylthio) -4H-1,2,4-triazole, 4-amino-3-hydrazino-5-mercapto-1,2,4-triazole, 4-methyl- 4H-1,2,4-triazole-3-thiol, 5-mercapto-4H-1,2,4-triazol-3-ol, 3-amino-5-methyl-4H-1,2,4-triazole, 4-methyl-4H-1,2,4-triazole-3-amine, 3,4-diamino-4H-1,2,4-triazole, 3,5-diamino-4H-1,2,4-triazole, 1,2,4-triazo 3,4,5-triamine, 3-pyridyl-4H-1,2,4-triazole, and the like 4H-1,2,4-triazole-3-carboxamide.

  As a commercially available product of the adhesion assistant, specifically, Aotech's Booster MR can be used.

In the multilayer wiring process, the metal pattern 160 is formed on the cured product 60 or on the layer 80 made of the adhesion assistant. Here, the metal pattern 160 is, for example, an electric circuit.
First, as shown in FIG. 2B, the surface opposite to the surface on which the substrate 10 is disposed in the layer 80 made of the adhesion assistant, that is, the surface opposite to the surface on which the cured product 60 is present. A metal film 150 is formed on the surface. Next, as shown in FIG. 2C, the formed metal film 150 is selectively removed to obtain a metal pattern 160. In this manufacturing method, the metal pattern 160 can be formed by a method similar to the method for forming the first conductor pattern 20 and the second conductor pattern 30 described above, that is, a photolithography method.

After forming the metal pattern, for example, as illustrated in FIG. 2D, a plating film 260 is formed on the surfaces of the conductor portion 40 and the metal pattern 160. The plating film 260 can be a connection portion suitable for wire bonding or soldering in the mounting process using the semiconductor device 300 in the present embodiment.
The plating film 260 is formed so as to cover the exposed conductor part 40 and the metal pattern 160. Examples of the material of the plating film 260 include a solder plating film, a tin plating film, a two-layer plating film in which a gold plating film is laminated on a nickel plating film, and an under bump metal ( UBM) membrane. Moreover, the film thickness of the plating film 260 can be, for example, 2 μm or more and 10 μm or less.

As a plating method for forming the plating film, for example, an electrolytic plating method or an electroless plating method can be employed. When the electroless plating method is used, the plating film 260 can be formed as follows. Hereinafter, an example in which the plating film 260 including two layers of nickel and gold is formed will be described, but the plating method is not limited thereto.
First, a nickel plating film is formed. When performing electroless nickel plating, the structure shown in FIG. 2C is immersed in a plating solution. By doing so, the plating film 260 can be formed on the surfaces of the conductor portion 40 and the metal pattern 160. As the plating solution, nickel lead and a reducing agent containing, for example, hypophosphite can be used. Subsequently, electroless gold plating is performed on the nickel plating film. Although the method of electroless gold plating is not particularly limited, for example, it can be performed by substitution gold plating performed by substitution of gold ions and ions of a base metal.

Moreover, this manufacturing method may have the process of performing the plasma processing with respect to the surface of the obtained plating film 260. FIG. In the plasma processing, for example, an inert gas such as argon gas, an oxidizing gas, or a fluorine-based gas can be used as a processing gas. Examples of the oxidizing gas include O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, and NO ₂ gas. The conditions for the plasma treatment in this production method are not particularly limited, but in addition to the ashing treatment, a treatment for contacting with plasma derived from an inert gas may be used.
Moreover, it is preferable that the plasma processing which concerns on this manufacturing method is the plasma processing performed without applying a bias voltage to a process target, or the plasma processing performed using non-reactive gas. The configuration in which no bias voltage is applied to the processing target is a configuration in which no bias voltage is applied to any of the conductor portion 40, the metal pattern 160, and the plating film 260 on the substrate 10 in the present embodiment. In addition, a bias voltage is not applied to a sample stage of a plasma processing apparatus for fixing the substrate 10 during the plasma processing. The plasma treatment time is preferably 30 seconds or longer, more preferably 1 minute or longer. On the other hand, the time is preferably 10 minutes or less, and more preferably 5 minutes or less. When the plasma processing time is not less than the above lower limit and not more than the upper limit, the durability of the semiconductor device 300 can be further improved.

(Separation process)
In the separation step, as shown in FIG. 3, the semiconductor device 300 according to the present embodiment is obtained by separating and selectively removing the substrate 10.
Note that the selective removal of the substrate 10 described above refers to the removal of part or all of the substrate 10. Examples of the method for removing the substrate 10 include a chemical etching method using an acidic liquid or an alkaline liquid, a physical polishing method, a physical peeling method, a plasma irradiation method, a laser ablation method, and the like. Among them, a method of chemically etching using an acidic liquid or an alkaline liquid is preferable. Specific examples of the acidic solution used at this time include mixed acids and aqueous ferric chloride solutions.

Hereinafter, the effect of this manufacturing method will be described.
Unlike the conventional manufacturing process, this manufacturing method can manufacture the semiconductor device 300 excellent in electrical connection reliability with a high yield without performing the polishing removal process for exposing the surface of the conductor post. . Therefore, according to this manufacturing method, manufacturing efficiency can be improved compared to the conventional manufacturing process in that a desired semiconductor device 300 can be manufactured with a small number of manufacturing steps.
Further, according to the present manufacturing method, the top portion 92 of the conductor portion 40 can be exposed by a simple method, and as a result, the manufacturing efficiency of the semiconductor device 300 can be improved also from the viewpoint of workability and the like. .

  Here, according to this manufacturing method, it is also possible to produce a wiring board (multilayer wiring board) having a multilayer structure in which four or more layers are laminated in the thickness direction. In this case, a multilayer wiring board is manufactured starting from the structure shown in FIG. Specifically, a cured product and a metal pattern are formed on the structure shown in FIG. 2D by the same method as described with reference to FIGS. A wiring board can be obtained.

<Second Embodiment>
In the method of manufacturing a semiconductor device according to the second embodiment, a plurality of conductor portions are formed on a semiconductor chip, and the heights of the plurality of conductor portions from the support are the same. A conductor part forming step of disposing the conductor part on the support, and introducing a thermosetting resin composition into a gap existing between the adjacent conductor parts so that the top part of the conductor part is exposed. A coating step of covering the conductor portion with a cured product of the thermosetting resin composition, and forming a metal pattern electrically connected to the top on the cured product without polishing the surface of the cured product A multilayer wiring process to be performed in this order, and further includes a separation process for separating the support and the cured product after the coating process.
This manufacturing method will be described with reference to FIGS. 5 to 7 are diagrams for explaining an example of the method for manufacturing the semiconductor device according to the present embodiment. The manufacturing method described with reference to FIGS. 5 to 7 is a process for manufacturing a fan-out type semiconductor device in which terminals are rearranged outside the region where the semiconductor chip is arranged. The method can also be applied to a process for manufacturing a fan-in type semiconductor device in which terminals are rearranged in a region where semiconductor chips are arranged.

(Conductor formation process)
In the conductor portion forming step, first, a plurality of conductor portions 420 are formed on the semiconductor chip 400, and then the plurality of the semiconductor chips and the above-described ones so that the heights of the plurality of conductor portions from the support are the same. A conductor part is arrange | positioned on the said support body.
First, the semiconductor chip 400 and the conductor part 420 will be described.

<Semiconductor chip 400>
The semiconductor chip 400 is not limited, and a known semiconductor chip can be selected according to a desired semiconductor device. Here, the semiconductor chip 400 includes electrode pads 410. The semiconductor chip 400 is electrically connected to the conductor portion 420 via the electrode pad 410.
Specific examples of the semiconductor chip 400 include an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, and a solid-state imaging device.

<Conductor part 420>
As shown in FIG. 5A, a plurality of conductor portions 420 are formed on the semiconductor chip 400. When the semiconductor chip 400 and the conductor portion 420 are arranged on the support 500 described later, the plurality of conductor portions 420 are formed so that the height from the support 500 to the plurality of conductor portions 420 is the same. Thereby, in the coating process described later, the top portion 421 of the conductor portion 420 is not embedded, and it is necessary to expose the top portion 421 by polishing the cured product 60 by a mechanical method such as mechanical polishing or chemical mechanical polishing. Not convenient.
The method for forming the conductor portion 420 is not limited, but it is preferable to use the photolithography method described in the first embodiment because the conductor portion 420 can be formed with high dimensional accuracy.

After the conductor portion 420 is formed on the semiconductor chip 400, the semiconductor chip 400 and the conductor portion 420 are disposed on the support 500. At this time, the semiconductor chip 400 is disposed on the support 500 such that the electrode pads 410 provided in the semiconductor chip 400 face the surface opposite to the surface on which the support 500 is disposed. That is, the semiconductor chip 400 and the conductor part 420 are arranged on the support 500 so that the support 500, the semiconductor chip 400, and the conductor part 420 are laminated in this order.
By controlling the height when forming the conductor part 420, when the semiconductor chip 400 and the conductor part 420 are arranged on the support body 500, the height of the plurality of conductor parts 420 from the support body 500 is increased. Can be the same.
Note that only one semiconductor chip 400 or a plurality of semiconductor chips 400 may be disposed on the support 500.

<Support 500>
As the support 500 on which the semiconductor chip 400 and the conductor part 420 are arranged, a support having a release layer on the surface of the base substrate may be used, or the release layer itself may be used as the support 500. The semiconductor chip 400 and the conductor part 420 are disposed on the release layer of the support 500. This is because a semiconductor device is manufactured by removing the support 500 in a separation step described later.
The substrate is not limited, and a substrate that can withstand the temperature and load applied during molding can be used. Specific examples of the base substrate include a wafer, a glass substrate, and a stainless plate. Moreover, you may use the metal plate which can be used as the board | substrate 10 demonstrated in 1st Embodiment.
The release layer is not limited, and for example, a layer that is foamed or deteriorated by heat treatment or ultraviolet irradiation to reduce the adhesive force between the semiconductor chip 400 and a cured product 450 described later can be used.

(Coating process)
In the covering step, the thermosetting resin composition is introduced into a gap existing between adjacent conductor parts, and the conductor part is covered with a cured product of the thermosetting resin composition so that the top part of the conductor part is exposed.
Here, as the method of the covering step, the same method as that described in the first embodiment can be used. Thereby, as shown in FIG. 5C, the conductor portion 420 is covered with the cured product 450 of the thermosetting resin composition 50 so that the top portion 421 of the conductor portion 420 is exposed. The cured product 450 is the same as the cured product 60. That is, a structure in which the top part 421 of the conductor part 420 is exposed is manufactured.

(Separation process)
After the coating step, the support 500 and the cured product 450 are separated. As a result, the structure shown in FIG. 5D is obtained.
The method of separating is not limited, and for example, the adhesion between the support 500, the cured product 450, and the semiconductor chip 400 may be reduced and then the substrate may be separated, or the substrate described in the first embodiment is selected. Alternatively, the removal method may be used.
Specific examples of the method for reducing the adhesion include a method for reducing the adhesion of the release layer of the support 500 by ultraviolet irradiation or heat treatment. Specific methods for reducing the adhesion of the release layer include, specifically, a method in which the release layer is foamed by heat treatment, a method in which the molecular bond of the release layer is decomposed by ultraviolet irradiation, and the release layer is deteriorated. Is mentioned.

  Note that the timing of performing the separation step is not limited as long as it is after the covering step, and may be, for example, after the formation of the solder bump 530 in the multilayer wiring step.

(Multilayer wiring process)
In the multilayer wiring process, a metal pattern that is electrically connected to the top portion 421 is formed on the cured product 450 without polishing the surface of the cured product 450. As the metal pattern, for example, as described in the first embodiment, a metal pattern 160 formed by a photolithography method can be used.

Below, an example of the formation method of a metal pattern is demonstrated using FIG.5 (d), FIG.6 (a)-(c), FIG.7 (a)-(c).
First, as shown in FIG. 5 (d), a photosensitive resin composition made of a photosensitive resin composition is used as shown in FIG. A first insulating resin film 460 that is a conductive resin film is formed. Here, as a photosensitive resin composition, the well-known material used for a plating resist can be used.
Next, as shown in FIG. 6B, a first opening 470 that exposes the top 421 of the conductor 420 is formed in the first insulating resin film 460. Here, as a method of forming the first opening 470, an exposure development method or a laser processing method can be used.
Note that it is preferable to perform a desmear process for removing smear generated when the first opening 470 is formed on the first opening 470. Specifically, the desmear treatment includes a wet method using an alkaline permanganate aqueous solution or a plasma treatment method using a processing gas.

Below, the wet method using alkaline permanganate aqueous solution is demonstrated.
First, the structure shown in FIG. 6B having the first insulating resin film 460 provided with the first opening 470 is immersed in a swelling liquid containing an organic solvent, and then the alkaline permanganate aqueous solution is immersed in the aqueous solution. Immerse and process. Examples of the permanganate include potassium permanganate and sodium permanganate. When potassium permanganate is used as the permanganate, the temperature of the potassium permanganate aqueous solution to be immersed is preferably 45 ° C. or higher, and preferably 95 ° C. or lower. The immersion time in the aqueous potassium permanganate solution is preferably 2 minutes or more, and preferably 20 minutes or less. Thereby, the adhesiveness of the 1st insulating resin film 460 and the hardened | cured material 450 can be improved.

Hereinafter, a plasma processing method using a processing gas will be described.
Specific examples of the plasma processing gas include argon gas, O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, NO ₂ gas, and fluorine-based gas.

  After forming the opening 470, as shown in FIG. 6C, a plating film 480 is formed so as to cover the top 421 of the exposed conductor 420 and the first insulating resin film 460. . As a method for forming the plating film, the plating method described in the multilayer wiring process of the first embodiment can be used. The plating film 480 can be a plating film having a two-layer structure in which a gold plating film is laminated on a solder plating film, a tin plating film, or a nickel plating film, for example. Moreover, the film thickness of the plating film 480 can be, for example, 2 μm or more and 10 μm or less. Examples of the plating method include an electrolytic plating method or an electroless plating method. About the obtained plating film 480, it is preferable to perform plasma processing by the method mentioned above from a viewpoint of improving the durability of the semiconductor device finally obtained.

After forming the plating film, as shown in FIG. 7A, a second insulating resin film 490, which is a photosensitive resin film made of a photosensitive resin composition, is formed on the surface of the plating film 480. Here, as a photosensitive resin composition, the well-known material used for a plating resist can be used.
Next, as shown in FIG. 7B, a second opening 510 that exposes a part of the plating film 480 is formed in the second insulating resin film 490. Here, as a method of forming the second opening 510, an exposure development method or a laser processing method can be used.
Next, as shown in FIG. 7C, solder bumps 530 are fused on the plating film 480 exposed in the second opening 510 via the UBM layer 520, and the semiconductor device 600 according to the present embodiment. Get.

Hereinafter, the structure of the thermosetting resin composition used for this manufacturing method is demonstrated.
As a thermosetting resin composition used for this manufacturing method, what contains a thermosetting resin, a hardening | curing agent, and an inorganic filler is mentioned. As the thermosetting resin, it is preferable to use an epoxy resin.

(Epoxy resin)
As the epoxy resin, it is possible to use monomers, oligomers, and polymers in general having two or more epoxy groups in one molecule regardless of the molecular weight and molecular structure. Specific examples of such an epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, hydrogenated bisphenol A type epoxy resin, bisphenol M type epoxy resin (4 , 4 ′-(1,3-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 ′-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Bisphenol type epoxy resins such as Z type epoxy resin (4,4′-cyclohexyldiene bisphenol type epoxy resin); phenol novolak type epoxy resin, brominated phenol novolak type epoxy resin, cresol novolak type epoxy resin, Novolak type epoxy resins such as laphenol group ethane type novolak type epoxy resins and novolak type epoxy resins having a condensed ring aromatic hydrocarbon structure; biphenyl type epoxy resins; aralkyl type epoxies such as xylylene type epoxy resins and biphenyl aralkyl type epoxy resins Resin; Naphthalene skeleton such as naphthylene ether type epoxy resin, naphthol type epoxy resin, naphthalene type epoxy resin, naphthalene diol type epoxy resin, bifunctional or tetrafunctional epoxy type naphthalene resin, binaphthyl type epoxy resin, naphthalene aralkyl type epoxy resin Epoxy resin; anthracene epoxy resin; phenoxy epoxy resin; dicyclopentadiene epoxy resin; norbornene epoxy resin; adamantane epoxy resin Fluorene type epoxy resin, phosphorus-containing epoxy resin, cycloaliphatic epoxy resin, aliphatic chain epoxy resin, bisphenol A novolac type epoxy resin, bixylenol type epoxy resin, triphenolmethane type epoxy resin, trihydroxyphenylmethane type epoxy resin Heterocyclic epoxy resins such as tetraphenylolethane type epoxy resin and triglycidyl isocyanurate; N, N, N ′, N′-tetraglycidylmetaxylenediamine, N, N, N ′, N′-tetraglycidylbis Glycidylamines such as aminomethylcyclohexane and N, N-diglycidylaniline, copolymers of glycidyl (meth) acrylate and compounds having an ethylenically unsaturated double bond, epoxy resins having a butadiene structure, bisphenol diglycidides It can include ether compound, diglycidyl ethers of naphthalene diol, the one or more selected from glycidyl ethers of phenols. Among these, it is more preferable to include a trihydroxyphenylmethane type epoxy resin and a biphenyl type epoxy resin from the viewpoint of improving the adhesion to the metal pattern.

  The content of the epoxy resin is, for example, preferably 3% by mass or more and more preferably 5% by mass or more with respect to the total solid content of the thermosetting resin composition. By making content of an epoxy resin more than the said lower limit, it improves the adhesiveness of the hardened | cured material 60 and the metal pattern 160 which are formed using a thermosetting resin composition, and the hardened | cured material 60 and the conductor part 40. Can contribute. On the other hand, the content of the epoxy resin is, for example, preferably 30% by mass or less, and more preferably 20% by mass or less, based on the total solid content of the thermosetting resin composition. By making content of an epoxy resin below the said upper limit, the heat resistance and moisture resistance of the hardened | cured material 60 formed using a thermosetting resin composition can be aimed at. In addition, the total solid content of a thermosetting resin composition refers to the whole component except the solvent contained in a thermosetting resin composition.

(Curing agent)
Examples of the curing agent used in the production method include linear aliphatic diamines having 2 to 20 carbon atoms such as ethylenediamine, trimethylenediamine, tetramethylenediamine, and hexamethylenediamine; metaphenylenediamine, paraphenylenediamine, paraxylenediamine, 4,4'-diaminodiphenylmethane, 4,4'-diaminodiphenylpropane, 4,4'-diaminodiphenyl ether, 4,4'-diaminodiphenyl sulfone, 4,4'-diaminodicyclohexane, bis (4-aminophenyl) Amino such as phenylmethane, 1,5-diaminonaphthalene, metaxylenediamine, paraxylenediamine, 1,1-bis (4-aminophenyl) cyclohexane, dicyanodiamide; aniline-modified resole resin, dimethyl ether resole resin, etc. Sol type phenol resin; novolak type phenol resin such as phenol novolak resin, cresol novolak resin, tert-butylphenol novolak resin, nonylphenol novolak resin; trihydroxyphenylmethane type phenol resin; triphenolmethane type phenol resin; Phenol aralkyl resins such as biphenylene skeleton-containing phenol aralkyl resins; phenol resins having a condensed polycyclic structure such as naphthalene skeleton and anthracene skeleton; polyoxystyrenes such as polyparaoxystyrene; hexahydrophthalic anhydride (HHPA), methyltetrahydroanhydride Alicyclic acid anhydrides such as phthalic acid (MTHPA), trimellitic anhydride (TMA), pyromellitic anhydride (PMDA) ), Acid anhydrides including aromatic acid anhydrides such as benzophenone tetracarboxylic acid (BTDA); polymercaptan compounds such as polysulfides, thioesters, thioethers; isocyanate compounds such as isocyanate prepolymers and blocked isocyanates; carboxylic acid-containing polyesters Examples include organic acids such as resins. These may be used alone or in combination of two or more. Of these, compounds having at least two phenolic hydroxyl groups in one molecule are preferable from the viewpoint of reliability and the like. Examples of such compounds include phenol novolak resins, cresol novolak resins, and tert-butylphenol novolak resins. Novolak type phenol resins such as nonylphenol novolac resin; resol type phenol resin; polyoxystyrene such as polyparaoxystyrene; phenylene skeleton-containing phenol aralkyl resin, biphenylene skeleton-containing phenol aralkyl resin, trihydroxyphenylmethane type phenol resin, etc. The

(Inorganic filler)
Specific examples of the inorganic filler used in this production method include fused crushed silica, fused spherical silica, crystalline silica, secondary agglomerated silica, finely divided silica, etc .; alumina, silicon nitride, aluminum nitride, boron nitride, titanium oxide Metal compounds such as silicon carbide, aluminum hydroxide, magnesium hydroxide, and titanium white; talc; clay; mica; glass fiber and the like. Among the above specific examples, fused spherical silica is preferable as the inorganic filler. Thereby, the improvement of the thermal expansion coefficient of the hardened | cured material 60 of a thermosetting resin composition can be suppressed. Therefore, the reliability of electrical connection can be improved.

  The shape of the inorganic filler is not limited, and specific examples include an indefinite shape, a scale shape, a spherical shape, a needle shape, and a fiber shape. The shape of the inorganic filler is preferably a spherical shape. Further, the particle shape is preferably infinitely spherical.

The average particle diameter d50 of the inorganic filler is not limited, but is preferably 0.1 μm or more and 20 μm or less, more preferably 0.1 μm or more and 17 μm or less, and 0.1 μm or more and 15 μm or more. Is more preferably 0.1 μm or more and 10 μm or less. Thereby, the filling property to the metal pattern in the mold cavity can be improved. Therefore, the hardened | cured material 60 can be shape | molded smoothly and it can suppress that a circuit jump arises.
As the inorganic filler, it is preferable to use two or more inorganic fillers having different average particle diameters d50 in combination. Thereby, falling of an inorganic filler can be suppressed, increasing the filling amount of an inorganic filler. Therefore, it can suppress that the conductor part 40 is exposed from the trace which the inorganic filler fell, and the reliability of electrical connection falls.
The average particle diameter d50 of the inorganic filler can be measured using, for example, a laser diffraction particle size distribution measuring apparatus (for example, LA-500 manufactured by HORIBA).

In addition, the inorganic filler used in the present production method preferably does not include coarse particles having a particle size exceeding 80 μm, and more preferably does not include coarse particles having a particle size exceeding 55 μm. More preferably, the particle diameter does not include coarse particles exceeding 25 μm. That is, the maximum particle diameter of the inorganic filler according to this embodiment is preferably less than 80 μm, more preferably less than 55 μm, and still more preferably less than 25 μm. Thereby, it can suppress that an inorganic filler falls off from the hardened | cured material 60. FIG. Thereby, it can suppress that the conductor part 40 is exposed from the trace which the inorganic filler fell, and the reliability of electrical connection falls.
In addition, the minimum value of the particle diameter of the inorganic filler concerning this embodiment can be 0.1 micrometer or more, for example.

  In addition, the inorganic filler used in the present manufacturing method is such that the ratio of particles of 10 μm or more in the particle size distribution measured by sieving using a JIS standard sieve is 20% by mass or less with respect to the entire inorganic filler. It is preferable that it is 15% by mass or less.

In addition to the above components, the thermosetting resin composition includes a curing accelerator, a release agent, a coupling agent, a leveling agent, a colorant, a low stress agent, a photosensitizer, an antifoaming agent, as necessary. You may add the 1 type, or 2 or more types of additive selected from a ultraviolet absorber, a foaming agent, antioxidant, a flame retardant, an ion-trapping agent, etc.
Hereinafter, representative components will be described.

(Curing accelerator)
The thermosetting resin composition may contain a curing accelerator. This hardening accelerator should just be what accelerates | stimulates the hardening reaction of an epoxy group and a hardening | curing agent. Specifically, as the curing accelerator, diazabicycloalkenes such as 1,8-diazabicyclo [5.4.0] undecene-7 and derivatives thereof; amine compounds such as tributylamine and benzyldimethylamine; Imidazole compounds such as methylimidazole; organic phosphines such as triphenylphosphine and methyldiphenylphosphine; tetraphenylphosphonium / tetraphenylborate, tetraphenylphosphonium / tetrabenzoic acid borate, tetraphenylphosphonium / tetranaphthoic acid borate, tetraphenylphosphonium・ Tetra-substituted phosphonium, tetra-substituted borate such as tetranaphthoyloxyborate, tetraphenylphosphonium, tetranaphthyloxyborate, etc .; Triads adducted with benzoquinone E sulfonyl phosphine, and the like. These may be used alone or in combination of two or more. More preferred are curing accelerators that have little rapid thickening after the thermosetting resin composition has melted in the mold cavity.

(Release agent)
The thermosetting resin composition may contain a release agent for the purpose of improving the releasability from the mold after forming the cured product 60. Examples of the mold release agent include natural waxes, synthetic waxes such as montanic acid esters, higher fatty acids or metal salts thereof, paraffin, polyethylene oxide and the like. As a mold release agent, it can use 1 type or in combination of 2 or more types among the said specific examples.

(Coupling agent)
As the coupling agent, for example, an epoxy silane coupling agent, a cationic silane coupling agent, an amino silane coupling agent, a γ-glycidoxypropyltrimethoxysilane coupling agent, a γ-aminopropyltriethoxysilane coupling agent, γ -Silane coupling agents such as mercaptopropyltrimethoxysilane coupling agents, phenylaminopropyltrimethoxysilane coupling agents, mercaptosilane coupling agents, titanate coupling agents, and silicone oil type coupling agents. As a coupling agent, it can use 1 type or in combination of 2 or more types among the said specific examples.

(Leveling agent)
Specific examples of the leveling agent include acrylic copolymers.

(Coloring agent)
Specific examples of the colorant include carbon black, bengara, and titanium oxide. As a coloring agent, it can be used 1 type or in combination of 2 or more types among the said specific examples.

(Low stress agent)
Specific examples of the low stress agent include acrylonitrile-butadiene rubber; silicone compounds such as silicone oil and silicone rubber. As the low stress agent, one or more of the above specific examples can be used in combination.

(Ion scavenger)
Examples of the ion scavenger include hydrotalcite, zeolite, bismuth hydroxide and the like. As the ion scavenger, one or two or more of the above specific examples can be used.

(Flame retardants)
Examples of the flame retardant include aluminum hydroxide, magnesium hydroxide, zinc borate, zinc molybdate, and phosphazene. As the flame retardant, one or more of the above specific examples can be used.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
Hereinafter, examples of the reference form will be added.
1. Forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor chip on the substrate or the semiconductor chip;
On the substrate or the semiconductor chip, introducing a thermosetting resin composition in a fluidized state into a gap existing between the adjacent conductor portions;
The thermosetting resin composition in a fluidized state is cured so that substantially the entire surface of the conductor portion facing the gap is covered with a cured product obtained by curing the thermosetting resin composition. Process,
After the step of curing, without polishing the surface of the cured product, forming a metal pattern in contact with the conductor portion;
In this order,
The step of curing is a step of obtaining any structure in the following state (a) or (b):
When the structure is in the state (a) below,
In the step of forming the metal pattern, the metal pattern is formed so as to contact the top,
When the structure is in the state (b) below,
Before the step of forming the metal pattern, further comprising the step of exposing the top by removing the skin layer by means other than polishing,
A method of manufacturing a semiconductor device, wherein in the step of forming the metal pattern, the metal pattern is formed so as to be in contact with the exposed top portion.
(A) A state in which a top portion of the conductor portion located in the height direction of the conductor portion is exposed. (B) A skin layer made of the cured product on the top portion of the conductor portion located in the height direction of the conductor portion. 1. A state in which the material adheres The means other than the polishing is chemical treatment or etching treatment. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
3. 1. electrically connecting the top portion located in the height direction of the conductor portion and the metal pattern by the step of forming the metal pattern; Or 2. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
4). Prior to the curing step, the method further includes a step of disposing a release film so as to press against the top portion of the conductor portion. To 3. A method for manufacturing a semiconductor device according to any one of the above.
5). In the step of disposing the release film, the arithmetic average surface roughness (Ra) of the surface of the release film on the side arranged to face the top of the conductor portion is 0 μm or more and 0.5 μm or less. Yes, The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
6). 1. The method further includes a step of treating the surface of the cured product with a chemical solution after the step of curing and before the step of forming the metal pattern. To 5. A method for manufacturing a semiconductor device according to any one of the above.
7). After the step of curing and before the step of forming the metal pattern, adhesion assistance is performed on the surface of the substrate or the semiconductor chip on which the cured product and the conductor portion are arranged. The method further includes the step of applying an agent. To 6. A method for manufacturing a semiconductor device according to any one of the above.
8). 1. The method further includes a step of performing a plasma treatment on the surface of the cured product after the step of curing and before the step of forming the metal pattern. To 7. A method for manufacturing a semiconductor device according to any one of the above.
9. Forming the plurality of conductor portions,
Forming a first conductor pattern on the substrate or the semiconductor chip;
Forming a second conductor pattern on the first conductor pattern so that the height from the surface of the substrate or the semiconductor chip is the same;
Including: To 8. A method for manufacturing a semiconductor device according to any one of the above.
10. Forming the metal pattern comprises:
Forming a metal film so as to be in contact with the top portion of the conductor portion;
Selectively removing the metal film to obtain the metal pattern;
Including: Thru 9. A method for manufacturing a semiconductor device according to any one of the above.
11. The thermosetting resin composition includes an epoxy resin, a curing agent, and an inorganic filler. To 10. A method for manufacturing a semiconductor device according to any one of the above.
12 10. the thermosetting resin composition further comprises a release agent; The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

  Hereinafter, although an example and a comparative example explain the present invention, the present invention is not limited to these.

  First, the thermosetting resin composition used in each example, reference example, and comparative example will be described.

First, the raw material component of a thermosetting resin composition is shown below.
・ Epoxy resin 1: Biphenyl type epoxy resin (Mitsubishi Chemical Corporation, YX4000K)
・ Epoxy resin 2: Triphenolmethane type epoxy resin (E-1032H60, manufactured by Mitsubishi Chemical Corporation)
Curing agent: Triphenolmethane type phenolic resin (Maywa Kasei Co., Ltd., MEH-7500)
Inorganic filler 1: fused spherical silica (manufactured by Nippon Steel & Sumikin Materials Co., Ltd., TS-6026, with coarse particles having a particle size exceeding 20 μm removed using a sieve, average particle size d50: 4 μm)
Inorganic filler 2: fused spherical silica (manufactured by Tatsumori Co., Ltd., MSR-SC3-TS, obtained by removing coarse particles having a particle size exceeding 55 μm using a sieve, average particle size d50: 17 μm)
Inorganic filler 3: Aluminum hydroxide (Nippon Light Metal Co., Ltd., BE043, with coarse particles having a particle size exceeding 20 μm removed using a sieve, average particle size d50: 4 μm)
Curing accelerator: A compound represented by the following formula (1) was used. The manufacturing method will be described later.

Coupling agent 1: γ-aminopropyltriethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-903)
Coupling agent 2: γ-mercaptopropyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-803)
Mold release agent: Carnauba wax (Towa Kasei Co., Ltd., TOWAX-132)
・ Ion scavenger: Hydrotalcite (manufactured by Kyowa Chemical Co., Ltd., DHT-4H)
Colorant: Carbon black (Mitsubishi Chemical Co., carbon # 5)
・ Low stress agent 1: Acrylonitrile-butadiene rubber (manufactured by Ube Industries, CTBN1008SP)
・ Low stress agent 2: Silicone oil (FZ-3730, manufactured by Toray Dow Corning)

A method for producing a curing accelerator is shown below.
First, for a separable flask equipped with a condenser and a stirrer, 12.81 g (0.080 mol) of 2,3-dihydroxynaphthalene, 16.77 g (0.040 mol) of tetraphenylphosphonium bromide, and 100 ml of methanol were added. The mixture was stirred and dissolved uniformly. Next, a sodium hydroxide solution in which 1.60 g (0.04 ml) of sodium hydroxide was dissolved in 10 mL of methanol was gradually dropped into the separable flask. The thus precipitated crystals were filtered, washed with water, and vacuum dried to obtain a curing accelerator.

<Example 1>
The semiconductor device 300 shown in FIG. 3 was fabricated as the semiconductor device of Example 1 by the procedure described with reference to FIGS. A detailed procedure will be described below.
First, a cold-rolled steel plate having a rectangular shape having a length of 240 mm and a width of 78 mm was prepared as the substrate 10. Next, an electrical circuit is formed as the first conductor pattern 20 on the substrate 10 by using a photolithography method, and then a plurality of metal pillars are formed as the second conductor pattern 30 on the first conductor pattern. Formed. Thereby, a plurality of conductor portions 40 including the first conductor pattern 20 and the second conductor pattern 30 were formed so that the top portions 92 of the plurality of conductor portions 40 were flush with each other.
In addition, the 1st conductor pattern 20 and the 2nd conductor pattern 30 were formed with copper. The shape of the second conductor pattern 30 was a cylindrical columnar shape. Photolithography was performed such that the diameter of the bottom surface and the top surface of the second conductor pattern 30 was 50 μm, and the height of the second conductor pattern 30 from the substrate 10 was the same as 150 μm.
Here, the components of the blending amounts shown in Table 1 below were mixed using a mixer at room temperature, and then biaxially kneaded at a temperature of 70 ° C. or higher and 110 ° C. or lower. Subsequently, after cooling to normal temperature, it grind | pulverized and the thermosetting resin composition 50 of the hardening state of B stage was prepared.
Next, the thermosetting resin composition 50 in a fluidized state was introduced into the gap between the adjacent conductor portions 40 using a compression molding method.
The conditions for introducing the thermosetting resin composition 50 by compression molding were a molding temperature of 175 ° C., a molding pressure of 10 MPa, and a molding time of 2 minutes. Here, the compression molding was performed by protecting the top portion 92 of the conductor portion 40 with the release film 100.
As the release film, Aflex (registered trademark) 50KN144NT manufactured by Asahi Glass Co., Ltd., which has an embossed surface and an unembossed surface each, was used. Here, the unembossed surface means a smooth surface. The thermosetting resin composition 50 was introduced by protecting the top portion 92 of the conductor portion 40 with the unembossed surface and bringing the embossed surface into contact with the mold. Thereby, the thermosetting resin composition was introduce | transduced so that the top part 92 of the some conductor part 40 might not be embedded by the thermosetting resin composition. In addition, about the unembossed surface of the release film 100, the arithmetic mean roughness (Ra) measured by the method based on JIS-B0601-1994 was 0.018 micrometer.
After introducing the thermosetting resin composition 50, the thermosetting resin composition 50 was cured by performing a heat treatment at a temperature of 175 ° C. for 4 hours to obtain a cured product 60 in a C stage cured state. Next, the release film 100 was peeled from the top portion 92 of the conductor portion. Here, the skin layer made of the cured product 60 adhered to a part of the top portion 92 of the conductor portion 40 on the order of several μm. Therefore, the skin layer was removed by chemical treatment. Specifically, the chemical treatment was performed with a potassium permanganate aqueous solution. After the chemical solution treatment, it was visually confirmed that the skin layer was completely removed, that is, the top portion 92 was exposed.
Next, on the cured product 60, Booster MR manufactured by Atotech was applied as an adhesion assistant to form a layer 80 made of the adhesion assistant. Next, the top portion 92 and a metal pattern 160 that is an electrical circuit to be electrically connected were formed by photolithography, and a plating film 260 was formed on the metal pattern 160 and the conductor portion 40. Note that the circuit line width / line interval (L / S) of the metal pattern was 12/12 μm.
Next, the substrate 10 was removed by chemical etching to obtain a multilayer wiring board as the semiconductor device of Example 1.

<Example 2>
When the thermosetting resin composition 50 in a fluidized state is introduced into the gaps between a plurality of adjacent conductor portions 40 using the compression molding method, the introduction of the thermosetting resin composition 50 depends on the embossed surface. A multilayer wiring board was obtained as a semiconductor device of Example 2 by the same method as Example 1 except that the top part 92 of the conductor part 40 was protected and the unembossed surface was brought into contact with the mold.
The embossed surface means a surface having an embossed shape.
In addition, about the embossed surface of the release film 100, the arithmetic mean roughness (Ra) measured by the method based on JIS-B0601-1994 was 1.247 micrometers.

<Example 3>
A semiconductor device of Example 3 was produced in the same manner as in Example 1 except that the composition of the thermosetting resin composition described in Table 1 was changed from inorganic filler 1 to inorganic filler 2. .
In addition, the compounding quantity of the inorganic filler 2 was 78.85 mass%.

<Example 4>
In the same manner as in Example 1, except that the chemical treatment for removing the skin layer was not performed and the adhesion assistant was not applied, that is, the layer 80 made of the adhesion assistant was not formed. 4 semiconductor devices were produced.

<Example 5>
In the method described in Example 1, chemical treatment for removing the skin layer is not performed, and further, the thermosetting resin composition 50 is cured to obtain a cured product 60 that is a cured state of the C stage, and then cured. The surface of the product 60 is subjected to plasma treatment using O ₂ gas to roughen the surface of the cured product 60, and furthermore, the adhesion assistant is not applied, that is, the layer 80 made of the adhesion assistant is formed. A semiconductor device of Example 5 was fabricated in the same manner as in Example 1 except that it was not formed.

<Reference Example 1>
The structure shown in FIG. 1 (f) (same as FIG. 8 (c)) was produced by employing the steps shown in FIGS.
First, a cold-rolled steel plate having a rectangular shape having a length of 240 mm and a width of 78 mm was prepared as the substrate 10. Next, an electrical circuit is formed as the first conductor pattern 20 on the substrate 10 by using a photolithography method, and then a plurality of metal pillars 91 are formed on the first conductor pattern on the second conductor pattern 30. Formed as. Thereby, a plurality of conductor portions 40 including the first conductor pattern 20 and the second conductor pattern 30 were formed so that the top portions 92 of the plurality of conductor portions 40 were flush with each other.
Here, the same thermosetting resin composition as that used in Example 1 was prepared.
Next, the thermosetting resin composition 50 in a fluidized state was introduced into the gap between the adjacent conductor portions 40 using a compression molding method.
The conditions for introducing the thermosetting resin composition 50 by compression molding were a molding temperature of 175 ° C., a molding pressure of 10 MPa, and a molding time of 2 minutes. Here, in the compression molding, the top 92 of the conductor 40 is not protected by the release film 100, and the thermosetting resin is formed so that the top 92 of the plurality of conductors 40 is embedded in the thermosetting resin composition 50. Composition 50 was introduced.
After introducing the thermosetting resin composition 50, the thermosetting resin composition 50 was cured by performing a heat treatment at a temperature of 175 ° C. for 4 hours to obtain a cured product 60 in a C stage cured state.
Next, the top portion 92 of the conductor portion 40 was exposed by mechanically polishing the surface of the cured product 60 using a grind apparatus.
Next, on the cured product 60, Booster MR manufactured by Atotech was applied as an adhesion assistant to form a layer 80 made of the adhesion assistant. Next, the top portion 92 and a metal pattern 160 that is an electrical circuit to be electrically connected were formed by photolithography, and a plating film 260 was formed on the metal pattern 160 and the conductor portion 40. Note that the circuit line width / line interval (L / S) of the metal pattern was 12/12 μm.
Next, the substrate 10 was removed by chemical etching to obtain a multilayer wiring board as the semiconductor device of Reference Example 1.

<Comparative Example 1>
A semiconductor device of Comparative Example 1 was manufactured in the same manner as Reference Example 1 except that the surface of the cured product 60 was polished using a chemical mechanical polishing (CMP) instead of a grinding device. .
The chemical mechanical polishing apparatus is an apparatus that performs mechanical polishing while causing a chemical reaction with an abrasive. Here, Z4U made by ANJI was used as the abrasive. The chemical mechanical polishing apparatus can obtain a high-speed and smooth polishing surface, but is not suitable for precise operations such as removing a skin layer.
In the semiconductor device of Comparative Example 1, the cured product 60 was polished at a high speed by the chemical mechanical polishing apparatus. However, the cured product 60 was dissolved and swollen by the abrasive, and the inorganic filler was dropped off. When the inorganic filler falls off, the electrical reliability of the semiconductor device may be reduced.

  As for the manufacturing method of Examples 1-5, compared with the manufacturing method of the reference example 1 and the comparative example 1, all of the resin layer which consists of the hardened | cured material of a thermosetting resin composition in the pre-process which forms a metal pattern. Since the process of polishing and removing the surface is not performed, the method is excellent in manufacturing efficiency of the semiconductor device in that the manufacturing time, manufacturing cost, and the like can be reduced.

  The following evaluation was performed on the semiconductor devices of Examples 1 to 5, Reference Example 1 and Comparative Example 1.

<Evaluation items>
Peel strength: In order to evaluate the adhesion between the cured product 60 and the metal pattern 160 provided in the semiconductor device, the peel strength of the both was measured by a method based on JIS C 6481. The unit is N / mm.

Arithmetic mean surface roughness (Ra): In the manufacturing process of the semiconductor device of each example, reference example, and comparative example, example 1-3 is treated with a chemical solution, and example 4 is a thermosetting resin composition 50. Is cured to obtain a cured product 60, Example 5 is subjected to plasma treatment, Reference Example 1 is mechanically polished with a grinder, and Comparative Example 1 is polished with a chemical mechanical polisher. The arithmetic average surface roughness (Ra) was measured for the surface on which the metal pattern was arranged. The measurement was performed by a method based on JIS B0601-2013. The unit is μm.

-Whether or not the inorganic filler is removed: The surface of the cured product 60 exposed on the surface of the semiconductor device on which the metal pattern is disposed is observed with a laser microscope, and the inorganic filler is removed from the cured product 60. We evaluated whether or not. The evaluation criteria are as follows.
A: The inorganic filler did not fall off.
○: Some inorganic fillers were confirmed to fall off, but the level was not problematic for practical use.
X: The inorganic filler dropped out to some extent in practical use.

-Presence / absence of circuit skip: In order to evaluate the reliability of electrical connection, the semiconductor device of each example, reference example, and comparative example was subjected to a thin wire appearance inspection and continuity check using a laser microscope. The evaluation criteria are as follows.
(Double-circle): There was no short circuit and wiring breakage, and it was confirmed that there is practically no problem from the viewpoints of both appearance and conductivity.
○: In terms of appearance, it was confirmed that there were some places having the possibility of affecting the conductivity, but it was confirmed that there was no practical problem in terms of conductivity.
X: It was confirmed that short-circuiting and disconnection of wiring were caused to some extent from a practical point of view in terms of both appearance and conductivity.

  The evaluation results regarding the above evaluation items are shown in Table 2 below.

  The semiconductor devices of the examples were all excellent in the reliability of electrical connection without using a mechanical method for exposing the conductor posts.

  In addition, although Example 1 has small surface roughness Ra compared with Example 3, it has expressed the peel strength comparable as Example 3. FIG. Although the detailed mechanism is not clear, it is presumed that Example 1 had less exposure of the inorganic filler having poor adhesion to the plated copper than Example 3.

Claims (20)

On the substrate, a conductor portion forming step of forming a plurality of conductor portions having the same height from the surface of the substrate;
A coating step of introducing the thermosetting resin composition into the gap between the adjacent conductor portions and covering the conductor portion with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed;
A method for manufacturing a semiconductor device, comprising: a multi-layer wiring step for forming a metal pattern electrically connected to the top on the cured product without polishing the surface of the cured product in this order. Forming a plurality of conductor portions on a semiconductor chip and forming the conductor portions on the support so that the heights of the plurality of conductor portions from the support are the same. Process,
A covering step of introducing a thermosetting resin composition into a gap existing between the adjacent conductor portions and covering the conductor portion with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed. When,
Including, in this order, a multilayer wiring step of forming a metal pattern electrically connected to the top on the cured product without polishing the surface of the cured product,
The method for manufacturing a semiconductor device, further comprising a separation step of separating the support and the cured product after the covering step. A method of manufacturing a semiconductor device according to claim 1 or 2,
In the covering step, when the thermosetting resin composition is introduced into the gap between the conductor portions, a skin layer is formed on the top portion, and the skin layer is removed by a chemical method. A method for manufacturing a semiconductor device according to any one of claims 1 to 3,
The manufacturing method of the semiconductor device which arrange | positions a release film so that it may press with respect to the said top part before making the said thermosetting resin composition into the said hardened | cured material in the said coating | coated process. A method of manufacturing a semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein an arithmetic average surface roughness Ra of a surface pressed against the top of the release film is 0 μm or more and 1.5 μm or less. A method of manufacturing a semiconductor device according to claim 4 or 5,
The method for manufacturing a semiconductor device, wherein the release film is a fluorine-based release film. A method for manufacturing a semiconductor device according to any one of claims 1 to 6,
A method for manufacturing a semiconductor device, wherein the surface of the cured product is roughened in the covering step. A method of manufacturing a semiconductor device according to claim 7,
The method of roughening treatment is a method for manufacturing a semiconductor device, which is chemical treatment or plasma treatment. A method of manufacturing a semiconductor device according to any one of claims 1 to 8,
Prior to the multilayer wiring step, the arithmetic average surface roughness Ra of the surface from which the top of the cured product is exposed is 0.02 μm or more and 0.8 μm or less. A method for manufacturing a semiconductor device according to any one of claims 1 to 9,
The method for manufacturing a semiconductor device, wherein a cured state of the cured product is a cured state of a C stage. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 10,
A manufacturing method of a semiconductor device, wherein, in the multilayer wiring step, the metal pattern is formed after an adhesion assistant is applied to the surface of the cured product. A method of manufacturing a semiconductor device according to claim 1,
In the conductor portion forming step, the conductor portion includes a first conductor pattern and a second conductor pattern,
The first conductor pattern is an electric circuit;
The method for manufacturing a semiconductor device, wherein the second conductor pattern includes a metal pillar. A method of manufacturing a semiconductor device according to claim 12,
The method for manufacturing a semiconductor device, wherein the first conductor pattern and the second conductor pattern are formed by a photolithography method. A method for manufacturing a semiconductor device according to any one of claims 1 to 13,
In the multilayer wiring process, the metal pattern is formed by a photolithography method. A method of manufacturing a semiconductor device according to claim 1,
The said thermosetting resin composition is a manufacturing method of a semiconductor device containing an epoxy resin, a hardening | curing agent, and an inorganic filler. A method of manufacturing a semiconductor device according to claim 15,
The method for manufacturing a semiconductor device, wherein the inorganic filler has a particle size of less than 80 μm. A method of manufacturing a semiconductor device according to claim 15 or 16,
The average particle diameter d50 of the inorganic filler is a method for manufacturing a semiconductor device, which is 0.1 μm or more and 20 μm or less. A method of manufacturing a semiconductor device according to any one of claims 15 to 17,
The manufacturing method of a semiconductor device which uses together 2 or more types of inorganic fillers from which an average particle diameter differs as said inorganic filler. A method of manufacturing a semiconductor device according to any one of claims 15 to 18,
The said thermosetting resin composition is a manufacturing method of the semiconductor device which further contains a mold release agent. Forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor chip on the substrate or the semiconductor chip;
On the substrate or the semiconductor chip, introducing a thermosetting resin composition in a fluidized state into a gap existing between the adjacent conductor portions;
The thermosetting resin composition in a fluidized state is cured so that substantially the entire surface of the conductor portion facing the gap is covered with a cured product obtained by curing the thermosetting resin composition. Process,
After the step of curing, without polishing the surface of the cured product, forming a metal pattern in contact with the conductor portion;
In this order,
The step of curing is a step of obtaining any structure in the following state (a) or (b):
When the structure is in the state (a) below,
In the step of forming the metal pattern, the metal pattern is formed so as to contact the top,
When the structure is in the state (b) below,
Before the step of forming the metal pattern, further comprising the step of exposing the top by removing the skin layer by means other than polishing,
A method of manufacturing a semiconductor device, wherein in the step of forming the metal pattern, the metal pattern is formed so as to be in contact with the exposed top portion.
(A) A state in which a top portion of the conductor portion located in the height direction of the conductor portion is exposed. (B) A skin layer made of the cured product on the top portion of the conductor portion located in the height direction of the conductor portion. Is attached

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