TW201812939A - Method of manufacturing semiconductor device capable of improving production efficiency with excellent reliability - Google Patents

Abstract

A method for manufacturing a semiconductor device according to the present invention sequentially includes a conductor part forming step: forming a plurality of conductor parts (40) on the substrate (10), the conductor parts having the same height from a surface of the substrate (10); a covering step: introducing a thermosetting resin composition (50) into a gap between adjacent conductor parts (40) in order to cover the conductor parts (40) with a hardening material (60) of the thermosetting resin composition (50) in a manner of exposing a top portion (92) of the conductor part (40); and a multilayer wiring step: performing no grinding on the surface of the hardening material (60) to form a metal pattern (160), which is electrically connected to the top portion (92), on the hardening material (60).

Description

   Manufacturing method of semiconductor device   

The present invention relates to a method for manufacturing a semiconductor device.

In the conventional manufacturing process of a typical wiring board, the following steps were performed: after forming a conductor post on the substrate, grinding and removing the entire surface of the conductor post opposite to the side on which one of the substrates is disposed A part of the resin layer obtained by pre-forming exposes the surface of the conductor post, and then a wiring pattern is formed so as to be electrically connected to the conductor post (Patent Document 1 and the like).

In the conventional typical redistribution process, the following steps were performed: after forming a conductive post on an electrode pad of a semiconductor wafer, molding the surroundings of the obtained structure with a sealing material, and then grinding to remove a part of the sealing material A redistribution layer is formed so that the surface of the conductive post is exposed and then electrically connected to the conductive post (Patent Document 2).

Patent Document 1: International Publication No. 2010/116615

Patent Document 2: Japanese Patent Application Laid-Open No. 2016-66649

In the conventional manufacturing process described in Patent Document 1 or 2, in order to ensure the electrical connectivity of the semiconductor device finally obtained, it is necessary to use a large-scale device to perform a grinding and removal treatment of the sealing material to expose the surface of the conductive post buried in the sealing material. .

However, regarding the manufacturing process of a semiconductor device, in recent years, in terms of productivity and the like, a higher technical level has been required than in the past. When a conductive post is exposed by a mechanical method such as the above-mentioned polishing and removal treatment, there is an inconvenience such as a reduction in productivity of a semiconductor device. This is because high precision is required in the grinding of the sealing material.

Therefore, the present invention provides a method for manufacturing a semiconductor device with excellent reliability in electrical connection on the premise that the manufacturing efficiency of the semiconductor device is improved by not using a mechanical method when the conductive posts are exposed.

According to the present invention, there is provided a method for manufacturing a semiconductor device, the method sequentially including: a conductor portion forming step: forming a plurality of conductor portions having the same height from a surface of the substrate on a substrate; and a covering step: adjoining the foregoing conductor portions Into the gap, a thermosetting resin composition is introduced and covered with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed; and a multilayer wiring step: the surface of the cured product is not polished, and A metal pattern electrically connected to the top is formed on the hardened object.

According to the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a conductor portion: forming a plurality of conductor portions on a semiconductor wafer, and forming the plurality of conductor portions at the same height from the support, The semiconductor wafer and the conductor portion are disposed on the support; a coating step: introducing a thermosetting resin composition into a gap existing between the adjacent conductor portions, and curing the portion by exposing the top of the conductor portion with the heat And a multilayer wiring step: without polishing the surface of the hardened material, forming a metal pattern on the hardened material that is electrically connected to the top, and after the coating step, the method further includes: A step of separating the support and the hardened material.

According to the present invention, there is provided a method for manufacturing a semiconductor device, which method comprises the steps of: forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor wafer on a substrate or a semiconductor wafer; A step of introducing a thermosetting resin composition in a flowing state into a gap existing between the adjacent conductor portions on the semiconductor wafer; covering the gap with a hardened material obtained by hardening the thermosetting resin composition; A method of hardening the thermosetting resin composition in a flowing state in a manner of substantially the entire area of the surface of the conductor part; and after the hardening step, the surface of the hardened material is not polished to form the conductor The step of contacting the metal pattern, and the aforementioned hardening step is a step of obtaining any one of the following structures (a) or (b). When the structure is in the following (a) state, the metal is formed as described above. In the step of patterning, the aforementioned metal pattern is formed in a manner to be in contact with the top portion. In the state (b) below, before the step of forming the metal pattern, the method further includes a step of removing the skin layer by means other than polishing to expose the top portion. In the step of forming the metal pattern, The metal pattern is formed in contact with the exposed top.

(a) A state where the top of the conductor portion located in the height direction of the conductor portion is exposed

(b) A state where a surface layer made of the hardened material is attached to the top portion of the conductor portion located in the height direction of the conductor portion.

Therefore, the present invention provides a method for manufacturing a semiconductor device with excellent reliability in electrical connection on the premise that the manufacturing efficiency of the semiconductor device is improved by not using a mechanical method when the conductive posts are exposed.

10‧‧‧ substrate

20‧‧‧ the first conductor pattern

30‧‧‧ 2nd conductor pattern

40‧‧‧Conductor

50‧‧‧ thermosetting resin composition

60‧‧‧hardened

80‧‧‧Layer composed of adhesion promoter

90‧‧‧soldering bump

91‧‧‧ metal pillar

92‧‧‧Top

100‧‧‧ release film

150‧‧‧metal film

160‧‧‧ metal pattern

260‧‧‧Coated film

300‧‧‧ semiconductor device

400‧‧‧semiconductor wafer

410‧‧‧electrode pad

420‧‧‧Conductor

421‧‧‧Top

450‧‧‧hardened

460‧‧‧The first insulating resin film

470‧‧‧The first opening

480‧‧‧plating film

490‧‧‧Second insulating resin film

500‧‧‧ support

510‧‧‧ 2nd opening

520‧‧‧UBM floor

530‧‧‧soldering bump

600‧‧‧ semiconductor device

The above-mentioned object and other objects, features, and advantages will be made clearer by a preferred embodiment described below and the following drawings attached to the embodiment.

FIG. 1 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to this embodiment.

FIG. 2 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to this embodiment.

FIG. 3 is a diagram for explaining an example of a method of manufacturing a semiconductor device according to this embodiment.

FIG. 4 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to this embodiment.

FIG. 5 is a diagram for explaining an example of a method of manufacturing a semiconductor device according to this embodiment.

FIG. 6 is a diagram for explaining an example of a method of manufacturing a semiconductor device according to this embodiment.

FIG. 7 is a diagram for explaining an example of a method of manufacturing a semiconductor device according to this embodiment.

FIG. 8 is a diagram for explaining an example of a method of manufacturing a semiconductor device according to a reference example.

Hereinafter, embodiments of the present invention will be described using drawings. In all drawings, the same constituent elements are denoted by the same reference numerals, and descriptions thereof are appropriately omitted.

The method for manufacturing a semiconductor device according to this embodiment includes the following four steps in order.

The first step is a step of forming a plurality of conductor portions having the same height from the surface of the substrate or the semiconductor wafer on a substrate or a semiconductor wafer.

The second step is a step of introducing a thermosetting resin composition in a flowing state into a gap existing between adjacent conductor portions on a substrate or a semiconductor wafer.

The third step is a step of hardening the thermosetting resin composition in a flowing state so that a hardened material obtained by hardening the thermosetting resin composition covers substantially the entire area of the surface of the conductor portion facing the gap.

The fourth step is a step of forming a metal pattern in contact with the conductor portion without polishing the surface of the hardened object after the above-mentioned hardening step.

Further, in the method of manufacturing a semiconductor device according to this embodiment, the third step (the step of curing) is a step of obtaining any one of the following structures (a) or (b). In the method of manufacturing a semiconductor device according to this embodiment, when the structure is in the following state (a), a metal is formed so as to be in contact with the top of the conductor portion in the fourth step (the step of forming a metal pattern). pattern. On the other hand, when the structure is in the following state (b), before the step of forming the metal pattern, a step of removing the surface layer by means other than polishing to expose the top is included. In the fourth step (forming In the step of metal pattern), a metal pattern is formed so as to be in contact with the top of the conductor portion.

(a) The state where the top of the conductor part located in the height direction of the conductor part is exposed

(b) A state where a surface layer made of a hardened substance is attached to the top of the conductor portion in the height direction of the conductor portion

Hereinafter, a method for manufacturing a semiconductor device according to this embodiment (hereinafter also referred to as a manufacturing method) will be described with reference to the drawings.

<First Embodiment>

The method for manufacturing a semiconductor device according to the first embodiment includes, in order, a step of forming a conductor portion: forming a plurality of conductor portions having the same height from the surface of the substrate on a substrate; and a step of covering: a gap between the adjacent conductor portions. Introducing a thermosetting resin composition, covering the conductor portion with a cured material of the thermosetting resin composition so that the top of the conductor portion is exposed; and a multilayer wiring step: without polishing the surface of the cured material, The hardened material forms a metal pattern electrically connected to the top.

In addition, after the multilayer wiring step, a separation step of separating the substrate may be included.

In this manufacturing method, a plurality of conductor portions having the same height from the surface of the substrate are formed on a substrate. This manufacturing method will be described with reference to FIGS. 1 to 4. 1 to 4 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to this embodiment.

(Conductor part forming step)

In the conductor portion forming step, a plurality of conductor portions 40 having the same height from the surface of the substrate 10 are formed on the substrate 10.

First, the substrate 10 and the conductor portion 40 will be described.

<Substrate 10>

First, the substrate 10 is prepared. As the substrate 10, any known substrate can be used as long as it is a substrate having characteristics such as flatness, rigidity, and heat resistance. Specific examples of the substrate 10 include a metal plate and the like.

Specific examples of the metal plate include a copper plate, an aluminum plate, an iron plate, a steel (steel) plate, a nickel plate, a copper alloy plate, a 42 alloy plate, and a stainless steel plate.

In addition, the steel (steel) plate may be in the form of a cold rolled steel plate such as SPCC (Steel Plate Cold Commercial).

In addition, a carrier foil based on the material of the above-mentioned metal plate may be formed on the substrate 10.

The size of the substrate 10 may be a size capable of arranging only one semiconductor element on its plane, or a size capable of arranging a plurality of semiconductor elements on its plane. As the size of the substrate 10, for example, a size in which a plurality of semiconductor elements can be arranged on the plane is preferable. Thereby, the same processing can be performed on a plurality of semiconductor devices. Therefore, it is convenient from the viewpoint of improving the production efficiency of the semiconductor device.

The planar shape when the substrate 10 is viewed from above may be, for example, a rectangular shape or a circular shape. For example, from the viewpoint of productivity, the planar shape when the substrate 10 is viewed from above is preferably a rectangular shape. Thereby, the operation of the substrate 10 in the manufacturing process of the semiconductor device is facilitated, and the productivity of the semiconductor device can be improved.

The shape of the substrate 10 may be, for example, a single-piece substrate processed into a frame shape, or a continuous body processed into a hoop shape.

<Conductor Section 40>

A plurality of conductor portions 40 are formed on the surface of the substrate 10. The plurality of conductor portions have the same height from the surface of the substrate 10.

The conductor portion 40 includes a first conductor pattern 20 and a second conductor pattern 30.

The first conductor pattern 20 is, for example, a circuit formed on the substrate 10.

The second conductor pattern 30 is, for example, a metal pillar. The second conductor pattern 30 serving as a metal pillar is electrically connected to the metal pattern and the first conductor pattern 20 formed in a multilayer wiring step described later, and a semiconductor device including multilayer wiring can be formed.

The second conductor pattern may be, for example, the metal pillar 91 itself, or may be formed by forming a solder bump 90 on the metal pillar 91. The second conductor pattern 30 shown in FIG. 1 (b) described later is formed by forming a solder bump 90 on the metal pillar 91. As shown in FIG. 4, the second conductor pattern 30 may be the metal pillar 91 itself.

In addition, from the viewpoint of realizing a semiconductor device corresponding to a narrow pitch, the shape of the second conductor pattern 30 formed in the manufacturing method is as shown in FIG. 1 (b) and the second conductor pattern 30 shown in FIG. The shape, that is, the shape of the cylinder is preferred.

In addition, the shape of the pillar is not limited, and specifically, it can be a corner pillar shape, a cylindrical shape, or the like.

A method of forming a plurality of conductor portions having the same height from the surface of the substrate will be described below.

First, as shown in FIG. 1 (a), a plurality of first conductor patterns 20 are formed on a substrate 10. Next, as shown in FIG. 1 (b), a second conductor pattern 30 is formed on the first conductor pattern 20.

The first conductor pattern 20 and the second conductor pattern 30 can be formed by, for example, a photolithography method. Here, the shapes of the first conductor pattern and the second conductor pattern are adjusted so that the height of the conductor portion 40 from the surface of the substrate 10 becomes the same. In this manufacturing method, the plurality of conductor portions 40 having the same height from the surface of the substrate 10 can be formed in this manner. Hereinafter, a case where the first conductive pattern 20 is formed will be described as an example, and a specific method of forming the conductive portion 40 by a photolithography method will be described.

<Photolithography>

First, a photosensitive resin film made of a photosensitive resin composition is formed on a substrate 10.

Here, as the photosensitive resin composition, a known material used for a plating resist can be used. Examples of such known materials include photosensitive materials such as photoresist, resist ink, and dry film. The photosensitive resin composition may be a negative type or a positive type.

As a method of forming a photosensitive resin film, the method of apply | coating a varnish-like photosensitive resin composition to the board | substrate 10 using a coater, a spinner, etc. specifically, and drying the obtained coating film are mentioned. Or a method of laminating a resin sheet made of a photosensitive resin composition on the substrate 10 by thermal compression bonding or the like.

Next, an opening portion having a predetermined opening pattern is formed on the photosensitive resin film. Examples of the method for forming the openings include an exposure development method and a laser processing method.

Next, the formed opening is buried with a metal film. Examples of the embedding method include an electroless plating method and a plating method. Specific examples of the material for forming the metal film include copper, copper alloy, 42 alloy, nickel, iron, chromium, tungsten, gold, solder, and the like. As the metal film, for example, copper is preferably used in the above specific examples.

Next, the photosensitive resin film is removed. Examples of the method for removing the photosensitive resin film include a method of peeling the photosensitive resin film using a peeling solution, or performing an ashing treatment, and further removing the residue of the photosensitive resin film adhered to the base layer by the peeling solution. Method, etc. From the viewpoint of improving the production efficiency of a semiconductor device, as a method for removing the photosensitive resin film, a method of using a peeling liquid to peel off the photosensitive resin film is preferably used. Examples of the stripping liquid include organic sulfonic acid-based stripping liquid containing alkylbenzenesulfonic acid, organic amine-based stripping liquid containing organic amines such as monoethanolamine, or an organic base or a fluorine-based liquid mixed with water. Water-based resist stripping solution for compounds and the like.

A metal film having a desired shape is obtained by the photolithography method described above.

In this embodiment, a metal film having a desired shape obtained by the above-mentioned photolithography method can be used as the first conductor pattern 20 or the second conductor pattern 30. That is, each of the first conductor pattern 20 and the second conductor pattern 30 can be formed by, for example, a photolithography method. By using the photolithography method, the conductor portion 40 can be formed with high accuracy so that the heights of the plurality of conductor portions 40 from the surface of the substrate become the same.

In addition, as shown in FIG. 1 (b), as a method of obtaining the second conductor pattern 30 in which the solder bumps 90 are formed on the metal pillars 91, a known method can be used to obtain the second conductor pattern 30 by photolithography. A method of forming a solder bump 90 from a metal film of a desired shape, that is, the pillar 91.

(Covering step)

In the coating step, a thermosetting resin composition is introduced into a gap between the adjacent conductor portions, and the conductor portion is covered with a cured product of the thermosetting resin composition so that the top of the conductor portion is exposed. That is, a part of the conductor portion is covered so that the top of the conductor portion is exposed.

In addition, the state in which the top portion 92 is exposed includes that before the metal pattern 160 is formed in a multilayer wiring formation step described later, the top portion 92 is exposed to such an extent that it can be embedded in the joint portion of the conductor portion 40 and the hardened object 60 without embedding other insulating members. status.

In the coating step, first, as shown in FIG. 1 (c), the thermosetting resin composition 50 in a flowing state is introduced into the gap existing between the adjacent conductor portions 40 on the substrate 10.

Here, as a method of introducing the thermosetting resin composition in a flowing state, specifically, a transfer molding method, a compression molding method, an injection molding method, a lamination molding method, and the like are mentioned.

Among the specific examples described above, a transfer molding method, a compression molding method, or a lamination molding method is preferred from the viewpoint of forming an insulating resin layer without leaving unfilled portions in the gap between adjacent conductor portions 40 on the substrate 10.

In order to use a transfer molding method, a compression molding method, or a lamination molding method, the shape of the thermosetting resin composition before it becomes a fluid state is preferably a particle shape, a powder shape, an ingot shape, or a sheet shape.

The arrangement of the substrate 10 and the conductor portion 40 when the thermosetting resin composition 50 is introduced will be described.

The substrate 10 and the conductor portion 40 are preferably arranged such that the surface of the hardened body 60 and the surface of the top portion 92 of the conductor portion 40 are on the same horizontal plane. That is, it is preferable that the hardened body 60 is formed so that the surface of the hardened body 60 and the surface of the top portion 92 of the conductor portion 40 are at the same level. This makes it possible to produce a structure in which the top portion 92 located in the height direction of the conductor portion 40 is exposed and there is no step difference in the joint portion between the hardened body 60 and the conductor portion 40.

When the thermosetting resin composition 50 is introduced, for example, as shown in FIG. 1 (d), it is preferable to arrange the release film 100 so as to press the top portion 92 of the conductor portion 40. Accordingly, the top portion 92 of the conductor portion 40 can be protected by the release film 100. Therefore, it is possible to prevent the cured product 60 of the thermosetting resin composition from adhering to the top portion 92 of the conductor portion 40, and it is possible to suppress a decrease in the reliability of the electrical connection of the semiconductor device. The release film 100 will be described in detail later.

The time point for disposing the release film 100 may be before the introduction of the thermosetting resin composition 50 in a flowing state, or may be the same time point as the introduction of the thermosetting resin composition 50 in a flowing state. As shown in FIG. 1 (d), after the thermosetting resin composition 50 in a flowing state is introduced, before the thermosetting resin composition 50 is made into a cured product 60. That is, the point in time at which the release film 100 is arranged may be before the thermosetting resin composition 50 is made into the cured product 60.

Although it will be described later, the release film is cured after curing the thermosetting resin composition to form a cured product 60.

<Release Film 100>

The release film 100 is not limited, and a release film for a thermosetting resin composition can be used. Specific examples of the release film 100 include a fluorine-based release film and a polyester-based release film.

When the method of introducing the thermosetting resin composition in a flowing state is a compression molding method, it is preferable to use a fluorine-based release film. When the method of introducing the thermosetting resin composition in a flowing state is a laminate molding method, it is preferable to use a polyester-based release film. Thereby, when the thermosetting resin composition contains an epoxy resin, the release film 100 can express favorable mold release property with respect to a thermosetting resin composition.

Specific examples of commercially available products of fluorine-based release films include AFLEX (registered trademark) 50KN144NT manufactured by ASAHI GLASS CO., LTD.

Regarding the release film 100, the surface on which the top portion 92 of the conductor portion 40 is pressed is preferably smooth without embossing, in other words. That is, it is preferable that the release film 100 has a surface which is not embossed, in other words, it has a mirror surface. Thereby, the surface of the hardened | cured material 60 can be made smooth by suppressing a undulation from a macro viewpoint. Therefore, the circuit jumper of the metal pattern 160 formed in the multilayer wiring step described later can be suppressed, and the reliability of the electrical connection can be improved. Specifically, even when the circuit line width / line interval (L / S) of the metal pattern 160 is as small as about 12/12 μm, the reliability of the electrical connection can be maintained at a high level.

The lower limit value of the arithmetic average surface roughness Ra of the surface of the release film 100 which presses the top portion 92 can be, for example, 0 μm or more, preferably 0.01 μm or more, more preferably 0.1 μm or more, and more preferably 0.15 μm or more. Thereby, the surface of the hardened | cured material 60 can form unevenness from a microscopic viewpoint. Therefore, the anchoring effect is exhibited in the adhesion between the metal pattern 160 and the cured object 60 formed in the multilayer wiring step described later, and the adhesion strength between the metal pattern 160 and the cured object 60 can be improved.

In addition, the upper limit value of the arithmetic average surface roughness Ra of the surface of the release film 100 on the top portion 92 is preferably 1.5 μm or less, more preferably 0.5 μm or less, more preferably 0.4 μm or less, and 0.3 μm. The following are more preferred, and particularly preferably 0.28 μm or less.

The arithmetic mean surface roughness Ra can be measured by, for example, a method in accordance with JIS-B0601-1994.

After the thermosetting resin composition is introduced into the gap between the adjacent conductor portions, the thermosetting resin composition 50 is cured, and a cured product 60 is formed. The cured product 60 functions as an insulating resin layer.

As shown in FIG. 1 (e), the hardened material 60 is preferably formed so as to cover the entire surface of the conductor portion 40 except the top portion, for example. As a result, it is possible to prevent the conductor portion 40 from contacting other than the metal pattern 160 formed in the multilayer wiring step described later. Therefore, it is preferable from the viewpoint of ensuring the insulation reliability of the semiconductor device.

Here, the thermosetting resin composition is in a B-stage cured state when a gap between adjacent conductive portions is introduced. In addition, when the thermosetting resin composition 50 is cured to form a cured product 60, it is in a C-stage cured state. That is, the hardened state of a hardened | cured material is a hardened state of a C stage.

The conditions for introducing the thermosetting resin composition differ depending on the molding method. When the compression molding method is used, the molding temperature is preferably set to, for example, 50 ° C or higher and 200 ° C or lower, and more preferably 80 ° C or higher and 180 ° C or lower. When the compression molding method is used, the molding time is preferably 30 seconds or more and 15 minutes or less, and more preferably 1 minute or more and 10 minutes or less. When the compression molding method is used, the molding pressure is preferably 0.5 MPa to 12 MPa, and more preferably 1 MPa to 10 MPa.

In addition, when the lamination molding method is used, for example, the pressure is applied in two stages, and the conditions for the first stage of pressing can be, for example, a molding temperature of 60 ° C or higher and 130 ° C or lower, and a molding time of 30 seconds or more and 10 minutes or less. The molding pressure is 0.2 MPa or more and 15 MPa or less. The conditions for the second stage of pressure can be set as follows: molding temperature is 80 ° C or more and 150 ° C or less, molding time is 30 seconds or more and 10 minutes or less, and molding pressure is 0.2 MPa or more and 15 MPa or less. the following.

By setting the molding temperature, pressure, and time during molding to the above ranges, it is possible to prevent a portion of the gap between the adjacent conductor portions 40 from being filled without the thermosetting resin composition 50.

In this embodiment, the B-stage hardened state (semi-hardened state) of the thermosetting resin composition refers to a reaction rate calculated by differential scanning calorimetry (DSC: Differential scanning calorimetry) greater than 0% and 70 %the following.

In this embodiment, the C-stage hardened state of the thermosetting resin composition refers to a reaction rate calculated by differential scanning calorimetry of greater than 70% and less than 100%.

Here, a method for determining the reaction rate will be described. First, regarding the thermosetting resin composition before the gap of the conductor portion 40 is introduced, the temperature distribution is measured by DSC measurement. The amount of heat released per unit mass of the exothermic peak of the hardening reaction calculated from the temperature distribution of the hardening reaction thus obtained was set to A [mJ / mg]. Next, regarding the thermosetting resin composition that calculates the reaction rate, the exothermic heat amount B [mJ / mg] converted from the unit mass of the exothermic peak of the curing reaction is also calculated. Using A and B, the reaction rate was determined by the following formula.

(Formula) (Reaction rate) = B / A × 100 (%)

The conditions for curing the thermosetting resin composition 50 to form a cured product 60 can be performed, for example, at a temperature of 150 ° C. or higher and 200 ° C. or lower by heat treatment for 1 hour to 6 hours.

When a compression molding method is used as the molding method to form the insulating resin layer composed of the hardened body 60, it is preferable to perform pressure reduction in a mold to perform resin sealing, and it is more preferable to perform the processing under vacuum.

The glass transition temperature of the hardened | cured material 60 is 100-250 degreeC, for example, More preferably, it is 130-220 degreeC. When the glass transition temperature of the hardened | cured material 60 exists in the said numerical range, it can suppress that a curvature generate | occur | produces in a semiconductor device.

In the present embodiment, when the top portion 92 of the conductor portion 40 is protected by the release film 100, it is possible to prevent the cured product 60 of the thermosetting resin composition from adhering to the top portion 92 to a certain extent, and the reliability of the electrical connection is reduced. However, the present inventors have studied the case where the release film 100 is used to protect the top portion 92 of the conductor portion 40. As a result, when the release film 100 is used alone, there are inconveniences in manufacturing a plurality of semiconductor devices. For example, the thermosetting resin composition is penetrated between the release film 100 and the conductor portion. When such an inconvenience exists, a surface layer made of a cured product 60 of a thermosetting resin composition is formed on the top portion 92 of the conductor portion 40. In a state where the surface layer has insulation and the top layer 92 is attached to the surface layer, the reliability of the electrical connection of the semiconductor device is reduced.

The state where the surface layer is adhered refers to a state where a film of a thermosetting resin composition is formed on the surface of the top portion 92. In addition, the maximum thickness of the surface layer is also a factor of μm.

The surface layer is not shown in FIGS. 1 to 4.

In the conventional method of manufacturing a semiconductor device, the hardened body 60 is formed by burying the conductor portion 40, and the hardened body 60 is polished by a mechanical method such as mechanical polishing or chemical mechanical polishing to expose the conductive portion 40. The inventors of the present invention have studied the situation of removing the surface layer by the conventional mechanical method, and it is clear that there is room for improvement in terms of accuracy and production efficiency when removing the surface layer of several μm order. The present inventors have studied a method capable of removing the surface layer without reducing productivity, and found that chemical methods such as chemical treatment or etching treatment are effective. Thereby, the surface layer can be removed without reducing the productivity of the semiconductor device. In addition, when the surface layer is removed by a chemical method, the hardened material 60 is not scratched too much, so the conductive portion 40 can be covered with the hardened material 60 of the thermosetting resin composition 50 so that the top of the conductive portion 40 is exposed.

Specific examples of the chemical liquid treatment include washing with an alkaline permanganate aqueous solution. Specific examples of the alkaline aqueous permanganate solution include an aqueous potassium permanganate solution and an aqueous sodium permanganate solution.

Furthermore, specifically, the etching treatment refers to cleaning with an etching solution. Specific examples of the etchant include those containing sulfuric acid and hydrogen peroxide.

In the present manufacturing method, when the structure shown in FIG. 1 (f) is in a state where the surface layer made of the hardened material 60 is attached to the top portion 92, that is, the state (b) described above, in order to ensure the finally obtained semiconductor device The reliability of the electrical connection needs to be obtained by using chemicals such as potassium permanganate, sodium permanganate and other aqueous solutions of permanganate, or an etching solution containing sulfuric acid and hydrogen peroxide, before forming a metal pattern described later. The surface layer is removed by means other than polishing to expose the top portion 92. In other words, when the structure shown in FIG. 1 (f) is in the state (b) described above, it is necessary to include a step of removing the surface layer by performing a chemical solution treatment or an etching treatment to expose the top portion 92.

After the thermosetting resin composition 50 is cured to form a cured product 60, as shown in FIG. 1 (f), the release film 100 is peeled from the surface of the cured product 60.

At this time, the release film 100 can be peeled after reducing the adhesion between the release film 100 and the cured product 60. Specifically, for the bonding portion of the mold release film 100 and the cured product 60, for example, the mold release layer of the mold release film 100 forming the bonding portion may be degraded by performing ultraviolet irradiation or heat treatment to reduce the adhesiveness and then peel. . In addition, when the release film 100 has sufficient release properties, it is not necessary to perform ultraviolet irradiation or heat treatment.

By forming the cured product 60 using the release film 100, the surface roughness of the cured product 60 can be controlled.

The lower limit value of the arithmetic average surface roughness Ra of the surface of the hardened object 60 from which the top portion 92 is exposed may be, for example, 0.02 μm or more, or 0.05 μm or more before the multilayer wiring step described later. Thereby, the surface of the hardened | cured material 60 can form unevenness from a microscopic viewpoint. Therefore, the anchoring effect can be exhibited, and the adhesion strength between the metal pattern 160 and the hardened body 60 formed in the multilayer wiring step described later can be improved.

In addition, before the multilayer wiring step, the upper limit of the arithmetic average surface roughness Ra of the surface of the hardened object 60 exposed on the top 92 is preferably set to 0.8 μm or less, more preferably 0.6 μm or less, and 0.2 μm or less. It is more preferable that it is 0.15 μm or less.

The arithmetic average surface roughness Ra of the surface of the hardened body 60 where the top portion 92 exists can be measured by a method in accordance with JIS-B0601-1994.

In this embodiment, the hardened body 60 obtained by hardening the thermosetting resin composition covers a substantially entire area of the surface of the conductor portion 40 facing the gap side existing between the adjacent conductor portions 40 so as to flow. The thermosetting resin composition 50 in the state is cured. Thereby, it is not necessary to go through the step of polishing the hardened material by a mechanical method used in the manufacturing process of the conventional semiconductor device before the multilayer wiring step described later. Therefore, the productivity of the semiconductor device can be improved.

Therefore, in this manufacturing method, it is important to consider the size of the gap existing between the adjacent conductor portions 40 on the substrate 10 and the size of the molding space provided by the mold used, that is, the volume, and calculate the amount of the gap introduced in advance. For the amount of the thermosetting resin composition 50 in the flowing state, the amount of the thermosetting resin composition 50 corresponding to the obtained calculation result is prepared. In addition, as for the mold used in this manufacturing method, it is preferable to use a mold provided with a molding space designed to conform to the size of the substrate 10. In this way, it is possible to prevent a situation in which, before the thermosetting resin composition 50 in the flowing state is cured, the thermosetting resin composition 50 flows into one side of the substrate 10 on which the conductor portion 40 is not formed. As a result, the height of the hardened object 60 from the surface of the substrate 10 deviates from the design value.

In the above, the coating steps have been described with reference to FIGS. 1 (c) to 1 (f), but the manufacturing method is not limited to the above examples.

In this manufacturing method, for example, a method using a mold in which the release film 100 is arranged in the molding space in advance can be used. An example will be described below.

First, a release film 100 is arranged in a molding space of a mold. Next, a predetermined amount of the thermosetting resin composition 50 in a flowing state is introduced onto the surface of the release film 100 disposed inside the mold. Next, the structure 92 is arranged in a mold such that the top portion 92 of the conductor portion 40 included in the structure shown in FIG. 1 (b) is pressed against the surface of the release film 100. In this way, the thermosetting resin composition 50 in a flowing state can be uniformly introduced into the gap existing between the adjacent conductor portions 40 on the substrate 10. Next, the thermosetting resin composition 50 in a flowing state is cured.

In addition, in this embodiment, in the multilayer wiring step described later, from the viewpoint of forming a metal pattern 160 having excellent adhesion to the hardened object 60, before the step of forming such a metal pattern 160, for example, The surface is roughened. Here, as a method of roughening the surface of the hardened | cured material 60, a chemical method or a physical method is mentioned. Here, as a chemical method, the method of applying a chemical | medical solution to the surface of the hardened | cured material 60 is mentioned. In addition, as a physical method, a plasma treatment is mentioned. Here, when a structure shown in FIG. 1 (f) is obtained in a state where the surface layer made of the hardened body 60 is attached to the top portion 92 described above, the same can be used from the viewpoint of improving the manufacturing efficiency of the semiconductor device The surface treatment and the chemical treatment on the surface of the hardened body 60 are performed simultaneously. In this way, it is possible to modify the surface state of the hardened object 60 while exposing the top portion 92 of the conductor portion 40.

In the present manufacturing method, in particular, when the cured product 60 is formed by using a thermosetting resin composition containing a mold release agent, a chemical liquid treatment is performed on the surface of the cured product 60, which can be obtained by a multilayer wiring step described later. The adhesion of the metal pattern 160 to the cured product 60 is further improved. In addition, examples of the medicament that can be used in the treatment of the chemical solution include alkaline permanganate aqueous solutions such as potassium permanganate and sodium permanganate. Thereby, the surface of the hardened | cured material 60 can form unevenness from a microscopic viewpoint. Therefore, the anchoring effect can be exhibited, and the adhesion strength between the metal pattern 160 and the hardened body 60 formed in the multilayer wiring step described later can be improved.

In addition, as a method of physically roughening the surface of the hardened object 60, a method of performing a plasma treatment on the surface of the hardened object 60 is mentioned. In the present manufacturing method, in particular, when the hardened body 60 is formed by using a thermosetting resin composition containing a mold release agent, the above-mentioned plasma treatment is performed, so that the metal pattern 160 obtained by the steps described later can be used to harden the hardened body 60. Adhesion becomes better. It is considered that this is because the surface of the hardened body 60 can form unevenness from a microscopic point of view, and the metal pattern penetrates into the unevenness of the hardened body 60 to exhibit an anchoring effect. In this type of plasma treatment, as the processing gas, for example, an inert gas such as argon, an oxidizing gas, or a fluorine-based gas can be used. Examples of the oxidizing gas include O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, and NO ₂ gas.

(Multilayer wiring step)

In the multilayer wiring step, the surface of the hardened object 60 is not polished, and a metal pattern 160 electrically connected to the top portion 92 is formed on the hardened object 60. Thereby, it is possible to suppress a decrease in the productivity of the semiconductor device, and it is possible to multilayer the wiring of the circuit.

The polishing of the surface of the hardened body 60 refers to a mechanical method such as mechanical polishing or chemical mechanical polishing.

As shown in FIGS. 2 (a) to 2 (d), the surface of the hardened object 60 is not polished, and a metal pattern 160 is formed on the surface of the substrate 10 on which one of the conductor portions 40 is formed. Specifically, in this manufacturing method, the top portion 92 and the metal pattern 160 in an exposed state are electrically connected by the method shown in FIGS. 2 (a) to 2 (d).

The details are described below.

In the multilayer wiring step, before the metal pattern 160 is formed on the hardened body 60, for example, as shown in FIG. 2 (a), a surface on one side of the substrate 10 on which the hardened body 60 and the conductor portion 40 are disposed may be formed. That is, a surface of the hardened object 60 on which the metal pattern 160 is formed is coated with an adhesion assistant, thereby forming a layer 80 composed of the adhesion assistant. Thereby, the adhesiveness of the metal pattern 160 and the hardened | cured material 60 can be improved further.

<Adhesion aid>

There is no restriction | limiting as a adhesion adjuvant, A well-known thing can be used.

As the adhesion aid, for example, a silane coupling agent or a triazole compound can be used.

Specific examples of the silane coupling agent include 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldiethoxysilane, and 3-glycidoxypropyl Triethoxysilane, p-styryltrimethoxysilane, 3-methacryloxypropylmethyldimethoxysilane, 3-methacryloxypropyltrimethoxysilane, 3- Methacryloxypropylmethyldiethoxysilane, 3-methacryloxypropyltriethoxysilane, 3-propenyloxypropyltrimethoxysilane, N-2- ( Aminoethyl) -3-aminopropylmethyldimethoxysilane, N-2- (aminoethyl) -3-aminopropyltrimethoxysilane, N-2- (aminoethyl) -3- Aminopropyltriethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, N-phenyl-3-aminopropyltrimethoxysilane, 3-mercaptopropyl Methyldimethoxysilane, 3-mercaptopropyltrimethoxysilane, bis (triethoxypropyl) tetrasulfide, 3-isocyanatepropyltriethoxysilane, and the like.

Specific examples of the triazole compound include 4-amino-1,2,4-triazole, 4H-1,2,4-triazole-3-amine, and 4-amino-3,5- Di-2-pyridyl-4H-1,2,4-triazole, 3- (methylthio) -4H-1,2,4-triazole, 4-amino-3-hydrazino-5-mercapto -1,2,4-triazole, 4-methyl-4H-1,2,4-triazole-3-thiol, 5-mercapto-4H-1,2,4-triazole-3-ol, 3-amino-5-methyl-4H-1,2,4-triazole, 4-methyl-4H-1,2,4-triazole-3-amine, 3,4-diamino-4H -1,2,4-triazole, 3,5-diamino-4H-1,2,4-triazole, 1,2,4-triazole-3,4,5-triamine, 3-pyridine 4H-1,2,4-triazole, 4H-1,2,4-triazole-3-carboxamide, and the like.

As a commercial item of a tackifier, specifically, Booster MR of Atotech, etc. can be used.

In the multilayer wiring step, a metal pattern 160 is formed on the hardened body 60 or on the layer 80 made of an adhesion promoter. Here, the metal pattern 160 is, for example, a circuit.

First, as shown in FIG. 2 (b), in the layer 80 made of the adhesion assistant, the surface opposite to the surface on which one of the substrates 10 is disposed, that is, the surface opposite to the surface where the hardened object 60 is present Surface to form a metal film 150. Next, as shown in FIG. 2 (c), the formed metal film 150 is selectively removed to obtain a metal pattern 160. In this manufacturing method, the method of forming the metal pattern 160 can use the same method as the method of forming the first conductor pattern 20 and the second conductor pattern 30 described above, that is, a photolithography method.

After the metal pattern is formed, for example, as shown in FIG. 2 (d), a plating film 260 is formed on the surfaces of the conductor portion 40 and the metal pattern 160. The plating film 260 can be used as a connection portion suitable for wire bonding or soldering in the mounting step using the semiconductor device 300 in this embodiment.

The plating film 260 is formed so as to cover the exposed conductor portion 40 and the metal pattern 160. As the material of the plating film 260, for example, a two-layer plating film having a gold plating film laminated on a solder plating film, a tin plating film, or a nickel plating film, and a metal under bump formed by electroless plating ( UBM, Under Bump Metallurgy) membrane. The thickness of the plating film 260 can be set to, for example, 2 μm or more and 10 μm or less.

As a plating treatment method for forming a plating film, for example, a plating method or an electroless plating method can be adopted. When the electroless plating method is used, the plating film 260 can be formed as follows. An example of forming a plating film 260 composed of two layers of nickel and gold will be described below, but the plating processing method is not limited to this.

First, a nickel plating film is formed. When electroless nickel plating is performed, the structure shown in FIG. 2 (c) is immersed in a plating solution. In this way, the plating film 260 can be formed on the surfaces of the conductor portion 40 and the metal pattern 160. As the nickel-lead and reducing agent, the plating solution can be, for example, one containing hypophosphite. Next, electroless gold plating is performed on the nickel-plated film. The method of electroless gold plating is not particularly limited, but it can be performed by, for example, replacement gold plating by replacement of gold ions with ions of the underlying metal.

In addition, the manufacturing method may further include a step of performing a plasma treatment on the surface of the obtained plating film 260. In the plasma treatment, for example, as the processing gas, an inert gas such as argon, an oxidizing gas, or a fluorine-based gas can be used. Examples of the oxidizing gas include O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, and NO ₂ gas. The conditions for the plasma treatment in this manufacturing method are not particularly limited, and in addition to the ashing treatment, the plasma treatment may be performed by contacting the plasma with an inert gas.

Moreover, as for the plasma processing of this manufacturing method, the plasma processing which does not apply a bias voltage to a process target, or the plasma processing which uses non-reactive gas is preferable. In addition, the configuration in which no bias is applied to the processing target means a configuration in which no bias is applied to any of the conductor portion 40, the metal pattern 160, and the plating film 260 on the substrate 10 in the present embodiment. In addition, no bias is applied to the sample table or the like of the plasma processing apparatus that fixes the substrate 10 during the plasma processing. The plasma treatment time is preferably 30 seconds or more, and more preferably 1 minute or more. On the other hand, this time is preferably 10 minutes or less, and more preferably 5 minutes or less. As long as the plasma processing time is greater than or equal to the above lower limit and less than the upper limit, the durability of the semiconductor device 300 can be further improved.

(Separation step)

In the separation step, as shown in FIG. 3, the substrate 10 is separated and selectively removed, thereby obtaining the semiconductor device 300 of this embodiment.

In addition, the above-mentioned selective removal of the substrate 10 means that a part or all of the substrate 10 is removed. Examples of the method for removing the substrate 10 include a method of performing chemical etching using an acid solution or an alkaline solution, a method of performing physical polishing, a method of performing physical peeling, a plasma irradiation method, and a laser ablation method. Among them, a method of performing chemical etching using an acidic solution or an alkaline solution is preferable. Moreover, as a specific example of the said acidic liquid used at this time, a mixed acid, a ferric chloride aqueous solution, etc. are mentioned.

The effect of this manufacturing method is demonstrated below.

This manufacturing method is different from the conventional manufacturing process. Without performing a polishing removal process for exposing the surface of the conductive post, a semiconductor device 300 having excellent electrical connection reliability can be manufactured with good yield. Therefore, according to this manufacturing method, a desired semiconductor device 300 can be manufactured with a small number of manufacturing steps, and the manufacturing efficiency can be improved compared with a conventional manufacturing process.

In addition, according to this manufacturing method, since the top portion 92 of the conductor portion 40 can be exposed in a simple manner, as a result, the manufacturing efficiency of the semiconductor device 300 can also be improved in terms of workability and the like.

Here, according to this manufacturing method, a wiring substrate (multilayer wiring substrate) having a multilayer structure in which four or more layers are laminated in the thickness direction can also be manufactured. In this case, a multilayer wiring board is manufactured from the structure shown in FIG. 2 (d). Specifically, on the structure shown in FIG. 2 (d), a hardened body and a metal pattern are produced by the same method as described with reference to FIGS. 1 and 2, thereby obtaining a desired multilayer. Wiring board.

<Second Embodiment>

The method of manufacturing a semiconductor device according to the second embodiment includes the steps of: forming a conductor portion: forming a plurality of conductor portions on a semiconductor wafer, and placing the semiconductor wafer and the plurality of conductor portions in the same manner as the height of the plurality of conductor portions from the support. Each of the conductor portions is arranged on the support; a coating step: introducing a thermosetting resin composition into a gap existing between the adjacent conductor portions, and using the thermosetting resin to expose the top of the conductor portions A hardened material covering the conductor portion; and a multilayer wiring step: without polishing the surface of the hardened material, forming a metal pattern electrically connected to the top portion on the hardened material, and after the covering step, further including separating the support The step of separating the body from the hardened body.

This manufacturing method will be described with reference to FIGS. 5 to 7. 5 to 7 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to this embodiment. In addition, the manufacturing method described with reference to FIGS. 5 to 7 is a manufacturing process for manufacturing a fan-out type semiconductor device in which terminals are also arranged outside a region where a semiconductor wafer is arranged, but this manufacturing method can also be applied to A process for manufacturing a fan-in semiconductor device in which terminals are arranged in a region where a semiconductor wafer is arranged.

(Conductor part forming step)

In the conductor formation step, first, a plurality of conductor portions 420 are formed on the semiconductor wafer 400, and then the plurality of semiconductor wafers and the conductor portions are arranged on the semiconductor wafer 400 so that the heights of the conductor portions from the support are the same. On the support.

First, the semiconductor wafer 400 and the conductor portion 420 will be described.

<Semiconductor wafer 400>

The semiconductor wafer 400 is not limited, and a known semiconductor wafer can be selected according to a desired semiconductor device. Here, the semiconductor wafer 400 includes an electrode pad 410. The semiconductor wafer 400 is electrically connected to the conductor portion 420 via an electrode pad 410.

Specific examples of the semiconductor wafer 400 include integrated circuits, large-scale integrated circuits, transistors, thyristors, diodes, and solid-state imaging devices.

<Conductor section 420>

As shown in FIG. 5 (a), a plurality of conductor portions 420 are formed on the semiconductor wafer 400. When the semiconductor wafer 400 and the conductor portion 420 are arranged in the support body 500 described later, the plurality of conductor portions 420 are formed so that the heights of the plurality of conductor portions 420 from the support body 500 are the same. Accordingly, in the coating step described later, the top portion 421 of the conductor portion 420 is not buried, and it is not necessary to expose the top portion 421 by polishing the hardened object 60 by a mechanical method such as mechanical polishing or chemical mechanical polishing, which is convenient.

The method of forming the conductor portion 420 is not limited, but if the photolithography method described in the first embodiment is used, the conductor portion 420 can be formed with good dimensional accuracy, which is preferable.

After the conductor portion 420 is formed on the semiconductor wafer 400, the semiconductor wafer 400 and the conductor portion 420 are arranged on a support 500. At this time, the semiconductor wafer 400 is arranged on the support body 500 such that the electrode pad 410 included in the semiconductor wafer 400 faces a surface opposite to the surface on which one side of the support body 500 is disposed. That is, the semiconductor wafer 400 and the conductor portion 420 are arranged on the support body 500 such that the support body 500, the semiconductor wafer 400, and the conductor portion 420 are laminated in this order.

The height of the conductor portion 420 is controlled in advance, so that when the semiconductor wafer 400 and the conductor portion 420 are arranged on the support 500, the heights of the plurality of conductor portions 420 from the support 500 can be made the same.

In addition, the number of semiconductor wafers 400 disposed on the support 500 may be only one, or may be plural.

<Support 500>

As the support body 500 on which the semiconductor wafer 400 and the conductor portion 420 are arranged, a release layer may be used on the surface of the base layer substrate, or the release layer itself may be used as the support body 500. The semiconductor wafer 400 and the conductor portion 420 are arranged on a release layer of the support 500. This is to manufacture a semiconductor device by removing the support 500 in a separation step described later.

The base layer substrate is not limited, and a person who can withstand the temperature and load applied during molding can be used. Specific examples of the base layer substrate include a wafer, a glass substrate, and a stainless steel plate. In addition, a metal plate that can be used as the substrate 10 described in the first embodiment may be used.

The release layer is not limited, and, for example, a foaming or deterioration caused by heat treatment or ultraviolet irradiation can be used, and the adhesive force of the semiconductor wafer 400 and the hardened material 450 described below is reduced.

(Covering step)

In the coating step, a thermosetting resin composition is introduced into a gap existing between adjacent conductor portions, and the conductor portion is covered with a cured material of the thermosetting resin composition so that the top of the conductor portion is exposed.

Here, as the method of the covering step, the same method as the method described in the first embodiment can be used. Thereby, as shown in FIG.5 (c), the conductor part 420 is covered with the hardened | cured material 450 of the thermosetting resin composition 50 so that the top part 421 of the conductor part 420 may be exposed. The cured product 450 is the same as the cured product 60. That is, a structure is produced in a state where the top portion 421 of the conductor portion 420 is exposed.

(Separation step)

After the coating step, the support body 500 and the hardened body 450 are separated. Thereby, the structure shown in FIG.5 (d) is obtained.

The method of separation is not limited. For example, the adhesion between the support 500 and the hardened body 450 and the semiconductor wafer 400 may be reduced and then peeled off. Alternatively, the method for selectively removing the substrate described in the first embodiment may be used.

As a method of reducing adhesiveness, specifically, the method of reducing the adhesiveness of the mold release layer of the support body 500 by ultraviolet irradiation, heat processing, etc. is mentioned. As a method of reducing the adhesion of the release layer, specifically, a method of foaming the release layer by heat treatment, a combination of molecules of the release layer which are decomposed by ultraviolet irradiation, and the release layer can be exemplified. Deterioration methods, etc.

In addition, the timing of performing the separation step is not limited as long as it is after the coating step, and for example, it may be after the solder bumps 530 are formed in the multilayer wiring step.

(Multilayer wiring step)

In the multilayer wiring step, the surface of the hardened object 450 is not polished, and a metal pattern electrically connected to the top portion 421 is formed on the hardened object 450. As the metal pattern, for example, as described in the first embodiment, the metal pattern 160 formed by the photolithography method can be used.

An example of a method for forming a metal pattern will be described below with reference to FIGS. 5 (d), 6 (a) to 6 (c), and 7 (a) to 7 (c).

First, as shown in FIG. 5 (d), on the side of the hardened material 450 exposed on the top portion 421 of the conductor portion 420, as shown in FIG. 6 (a), a photosensitive resin film made of a photosensitive resin composition, that is, the first Insulating resin film 460. Here, as the photosensitive resin composition, a known material used for a plating resist can be used.

Next, as shown in FIG. 6 (b), a first opening portion 470 is formed on the first insulating resin film 460 so that the top portion 421 of the conductor portion 420 is exposed. Here, as a method of forming the first opening 470, an exposure development method or a laser processing method can be used.

In addition, it is preferable to perform a desmear process on the first opening portion 470, and the aforementioned decontamination treatment is a process of removing stains generated when the first opening portion 470 is formed. Specific examples of the decontamination treatment include a wet method using an alkaline permanganate aqueous solution and a plasma treatment method using a treatment gas.

Hereinafter, a wet method using an alkaline permanganate aqueous solution will be described.

First, the structure shown in FIG. 6 (b) having the first insulating resin film 460 provided with the first opening 470 is immersed in a swelling liquid containing an organic solvent, and then in an alkaline permanganate aqueous solution. Treatment by immersion. Examples of the permanganate include potassium permanganate and sodium permanganate. When potassium permanganate is used as the permanganate, the temperature of the potassium permanganate aqueous solution for impregnation is preferably 45 ° C or higher, and more preferably 95 ° C or lower. The time of immersion in the potassium permanganate aqueous solution is preferably 2 minutes or more, and more preferably 20 minutes or less. Thereby, the adhesiveness of the 1st insulating resin film 460 and the hardened | cured material 450 can be improved.

A plasma processing method using a processing gas will be described below.

Specific examples of the processing gas for the plasma treatment include argon, O ₂ gas, O ₃ gas, CO gas, CO ₂ gas, NO gas, NO ₂ gas, and fluorine-based gas.

After the opening portion 470 is formed, as shown in FIG. 6 (c), a plating film 480 is formed so as to cover the top portion 421 of the conductive portion 420 and the first insulating resin film 460 in an exposed state. As a method for forming a plating film, the plating processing method described in the multilayer wiring step of the first embodiment can be used. The plating film 480 can be, for example, a two-layered plating film having a gold plating film laminated on a solder plating film, a tin plating film, or a nickel plating film. The thickness of the plated film 480 can be, for example, 2 μm or more and 10 μm or less. In addition, as an example of the coating treatment method, a plating method or an electroless plating method can be mentioned. From the viewpoint of improving the durability of the semiconductor device finally obtained, it is preferable to perform the plasma treatment by the above-mentioned method on the obtained plating film 480.

After the plating film is formed, as shown in FIG. 7 (a), a second insulating resin film 490 that is a photosensitive resin film made of a photosensitive resin composition is formed on the surface of the plating film 480. Here, as the photosensitive resin composition, a known material used for a plating resist can be used.

Next, as shown in FIG. 7 (b), a second opening 510 is formed in the second insulating resin film 490 to expose a part of the plating film 480. Here, as a method of forming the second opening 510, an exposure development method or a laser processing method can be used.

Next, as shown in FIG. 7 (c), the solder bump 530 is welded to the plating film 480 exposed in the second opening portion 510 through the UBM layer 520 to obtain the semiconductor device 600 of this embodiment.

The configuration of the thermosetting resin composition used in the present manufacturing method will be described below.

As a thermosetting resin composition used by this manufacturing method, the thing containing a thermosetting resin, a hardening | curing agent, and an inorganic filler is mentioned. As the thermosetting resin, an epoxy resin is preferably used.

(Epoxy resin)

As the epoxy resin, a monomer, an oligomer, and a polymer having two or more epoxy groups in one molecule can be used regardless of its molecular weight and molecular structure. As specific examples of such an epoxy resin, it can be selected from the group consisting of bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, and hydrogenated bisphenol A. Type epoxy resin, bisphenol M type epoxy resin (4,4 '-(1,3-phenylene diisopropylidene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4, 4 '-(1,4-phenylene diisopropylidene) bisphenol type epoxy resin), bisphenol Z type epoxy resin (4,4'-cyclohexadiene bisphenol type epoxy resin), etc. Bisphenol epoxy resin; phenol novolac epoxy resin, brominated phenol novolac epoxy resin, cresol novolac epoxy resin, tetraphenol ethane novolac epoxy resin, with condensation ring Novolak epoxy resins such as novolak epoxy resins with aromatic hydrocarbon structure; biphenyl epoxy resins; xylylene epoxy resins, biphenyl aralkyl epoxy resins Equal aralkyl epoxy resin; naphthyl ether epoxy resin, naphthol epoxy resin, naphthalene epoxy resin, naphthalene glycol epoxy resin, 2-functional to 4-functional epoxy naphthalene resin, Binaphthyl epoxy resin , Naphthalene aralkyl epoxy resins and other epoxy resins with a naphthalene skeleton; anthracene epoxy resin; phenoxy epoxy resin; dicyclopentadiene epoxy resin; norbornene epoxy resin; Adamantane type epoxy resin; 茀 type epoxy resin, phosphorus-containing epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, bisphenol A novolac epoxy resin, bixylenol type ring Heterocyclic rings such as oxygen resin, trisphenol methane epoxy resin, trishydroxyphenylmethane epoxy resin, tetraphenylol ethane epoxy resin, and triglycidyl isocyanate Oxygen resin; N, N, N ', N'-tetraepoxypropyl-m-xylylenediamine, N, N, N', N'-tetraepoxypropyldiamine methylcyclohexane, N, N -Glycidylamines such as diglycidyl aniline, or copolymers of glycidyl (meth) acrylate and compounds having ethylenically unsaturated double bonds, epoxy resins with butadiene structure, One or two or more kinds of diglycidyl etherate of phenol, diglycidyl etherate of naphthalene glycol, and phenolic propyllyl etherate. Among these, from the viewpoint of improving the adhesion with the metal pattern, it is more preferable to include a trihydroxyphenylmethane type epoxy resin and a biphenyl type epoxy resin.

The content of the epoxy resin is, for example, preferably 3% by mass or more, and more preferably 5% by mass or more, based on the total solid content of the thermosetting resin composition. By setting the content of the epoxy resin to the above lower limit value or more, it is possible to contribute to improving the adhesion between the hardened material 60 and the metal pattern 160 formed using the thermosetting resin composition, and the hardened material 60 and the conductor portion 40. . On the other hand, the content of the epoxy resin is, for example, 30% by mass or less with respect to the total solid content of the thermosetting resin composition, and more preferably 20% by mass or less. By setting the content of the epoxy resin to the above-mentioned upper limit value or less, it is possible to improve the heat resistance or moisture resistance of the cured product 60 formed using the thermosetting resin composition. In addition, the total solid content of a thermosetting resin composition means all components other than a solvent contained in a thermosetting resin composition.

(hardener)

Examples of the curing agent used in the present manufacturing method include linear aliphatic diamines having 2 to 20 carbon atoms, such as ethylenediamine, trimethylenediamine, tetramethylenediamine, and hexamethylenediamine. ; M-phenylenediamine, p-phenylenediamine, p-xylylenediamine, 4,4'-diaminodiphenylmethane, 4,4'-diaminodiphenylpropane, 4,4'-diamine Diphenyl ether, 4,4'-diaminodiphenylhydrazone, 4,4'-diaminodicyclohexane, bis (4-aminophenyl) phenylmethane, 1,5-diaminonaphthalene, m Xylene diamine, p-xylene diamine, 1,1-bis (4-aminephenyl) cyclohexane, dicyandiamine and other amines; aniline modified soluble phenolic resin or dimethyl ether soluble phenolic resin And other soluble phenolic resin (resole) type phenol resin; phenol novolac resin, cresol novolac resin, tertiary butyl novolac resin, nonyl phenol novolac resin and other novolac phenol resin; trihydroxyphenylmethane Phenol resins; triphenol methane phenol resins; phenol aralkyl resins containing a phenylene skeleton, phenol aralkyl resins containing a phenylene skeleton; phenol aralkyl resins such as a naphthalene skeleton or an anthracene skeleton Condensed polycyclic structure Phenol resins; polyoxystyrenes such as polyparaoxystyrene; containing alicyclic acid anhydrides such as hexahydrophthalic anhydride (HHPA) and methyltetrahydrophthalic anhydride (MTHPA); TMA), pyromite anhydride (PMDA), benzophenone tetracarboxylic dianhydride (BTDA), and other acid anhydrides; polysulfides, thioesters, thioethers, and other polythiol compounds; isocyanate prepolymers And isocyanate compounds such as block isocyanates; organic acids such as polyester resins containing carboxylic acids. These may be used individually by 1 type, and may use 2 or more types together. Among these, compounds having at least two phenolic hydroxyl groups in one molecule are preferable from the viewpoint of reliability and the like. Examples of such compounds include phenol novolac resin, cresol novolac resin, Novolac phenol resins such as tertiary butylphenol novolac resin, nonylphenol novolac resin; soluble phenol resin type phenol resin; polyoxystyrene such as poly-p-oxystyrene; phenol containing phenylene skeleton Aralkyl resins, phenol aralkyl resins containing a stretched phenyl skeleton, trihydroxyphenylmethane type phenol resins, and the like.

(Inorganic filler)

Specific examples of the inorganic filler used in this manufacturing method include fumed and crushed silica, fused spherical silica, crystalline silica, secondary agglomerated silica, and finely divided silica. Silicon; aluminum oxide, silicon nitride, aluminum nitride, boron nitride, titanium oxide, silicon carbide, aluminum hydroxide, magnesium hydroxide, titanium white and other metal compounds; talc; clay; mica; glass fiber, etc. As the inorganic filler, in the above specific examples, fused spherical silica is preferred. Thereby, the improvement of the thermal expansion coefficient of the hardened | cured material 60 of a thermosetting resin composition can be suppressed. Therefore, the reliability of the electrical connection can be improved.

The shape of the inorganic filler is not limited, and specific examples include an irregular shape, a scale shape, a spherical shape, a needle shape, and a fiber shape. The shape of the inorganic filler is preferably a spherical shape. In addition, it is preferable that the shape of the particles is nearly spherical.

The average particle diameter d50 of the inorganic filler is not limited. For example, 0.1 μm to 20 μm is preferred, 0.1 μm to 17 μm is more preferred, 0.1 μm to 15 μm is more preferred, and 0.1 μm to 10 μm is more preferred. Further preferred. Thereby, the filling property to a metal pattern in a cavity can be improved. Therefore, the cured product 60 can be smoothly formed, and the occurrence of circuit jumpers can be suppressed.

In addition, it is preferable to use two or more inorganic fillers having different average particle diameters d50 as the inorganic filler at the same time. This makes it possible to increase the filling amount of the inorganic filler and to suppress the fall of the inorganic filler. Therefore, it is possible to suppress the exposure of the conductor portion 40 from the inorganic filler, and it is possible to prevent the reliability of the electrical connection from decreasing.

The average particle diameter d50 of the inorganic filler can be measured using, for example, a laser diffraction particle size distribution measurement device (for example, LA-500 manufactured by HORIBA).

In addition, as for the inorganic filler used in this manufacturing method, for example, it is preferable that it does not contain coarse particles with a particle size larger than 80 μm, it is more preferable that it does not contain coarse particles with a particle size larger than 55 μm, and it does not include coarse particles with a particle size larger than 25 μm. Particles are further preferred. That is, the maximum value of the particle diameter of the inorganic filler in this embodiment is, for example, preferably less than 80 μm, more preferably less than 55 μm, and even more preferably less than 25 μm. This makes it possible to prevent the inorganic filler from falling out of the cured product 60. Thereby, it is possible to prevent the traces of the conductor portion 40 from falling off from the inorganic filler, and to suppress a decrease in the reliability of the electrical connection.

Moreover, the minimum value of the particle diameter of the inorganic filler of this embodiment can be made into 0.1 micrometer or more, for example.

In addition, it is preferable that the proportion of particles of 10 μm or more in the particle size distribution of the inorganic filler used in this manufacturing method with respect to the entire inorganic filler as measured by sieving using a JIS standard sieve is 20% by mass or less, 15 mass% or less is more preferable.

In addition to the above components, the thermosetting resin composition may be selected from a hardening accelerator, a release agent, a coupling agent, a leveling agent, a colorant, a low stress agent, a photosensitizer, and a defoaming agent as needed. Additives, ultraviolet absorbers, foaming agents, antioxidants, flame retardants, and ion trapping agents.

Hereinafter, representative components will be described.

(Hardening accelerator)

The thermosetting resin composition may contain a curing accelerator. The hardening accelerator may be any one that accelerates the hardening reaction between the epoxy group and the hardener. Specific examples of the hardening accelerator include diazabicyclic olefins such as 1,8-diazabicyclo [5.4.0] undecene-7 and derivatives thereof; tributylamine and benzyldimethyl Amine compounds such as amines; Imidazole compounds such as 2-methylimidazole; Organic phosphines such as triphenylphosphine, methyldiphenylphosphine; Tetraphenylphosphonium, tetraphenylmethane oxyboronic acid tetraphenylphosphonium, tetranaphthyloxyboronic acid tetraphenylphosphonium and other tetra-substituted boric acid tetra-substituted phosphonium; triphenylphosphine and the like are added to benzoquinone. These may be used individually by 1 type, and may use 2 or more types together. More preferably, a hardening accelerator which has a small viscosity increase after the thermosetting resin composition melt | dissolves in a cavity is mentioned.

(Release Agent)

The thermosetting resin composition may contain a release agent for the purpose of improving the releasability from the mold after the cured product 60 is formed. Examples of such a release agent include natural waxes, synthetic waxes such as octacosanoate, higher fatty acids or metal salts thereof, paraffin wax, and oxidized polyethylene. As a mold release agent, in the said specific example, 1 type, or 2 or more types can be used together.

(Coupling agent)

Examples of the coupling agent include an epoxy silane coupling agent, a cationic silane coupling agent, an amine silane coupling agent, a γ-glycidoxypropyltrimethoxysilane coupling agent, and a γ-aminopropyltriethoxysilane. Coupling agents, γ-mercaptopropyltrimethoxysilane coupling agents, phenylaminopropyltrimethoxysilane coupling agents, silane coupling agents such as mercaptosilane coupling agents, titanate-based coupling agents, and polysiloxane coupling agents Wait. As the coupling agent, in the above specific examples, one type or two or more types can be used in combination.

(Leveling agent)

Specific examples of the leveling agent include acrylic copolymers.

(Colorant)

Specific examples of the colorant include carbon black, hematite oxide, and titanium oxide. As a coloring agent, in the said specific example, 1 type, or 2 or more types can be used together.

(Low stress agent)

Specific examples of the low-stress agent include acrylonitrile-butadiene rubber; polysiloxanes such as silicone oil and silicone rubber. As a low-stress agent, in the said specific example, 1 type, or 2 or more types can be used together.

(Ion trapping agent)

Examples of the ion trapping agent include hydrotalcite, zeolite, and bismuth hydroxide. As the ion trapping agent, in the specific examples described above, one type or two or more types can be used in combination.

(Flame retardant)

Examples of the flame retardant include aluminum hydroxide, magnesium hydroxide, zinc borate, zinc molybdate, and phosphazene. As a flame retardant, in the said specific example, 1 type, or 2 or more types can be used together.

The embodiments of the present invention have been described with reference to the drawings, but these are examples of the present invention, and various configurations other than the above can be adopted.

In the following, examples of reference forms are added.

1. A method for manufacturing a semiconductor device includes, in order, forming a plurality of conductor portions having the same height from a surface of the substrate or the semiconductor wafer on a substrate or a semiconductor wafer; and on the substrate or the semiconductor wafer, adjoining A step of introducing a thermosetting resin composition in a flowing state into a gap existing between the conductor portions; covering the surface of the conductor portion facing the gap with a hardened material obtained by curing the thermosetting resin composition; A method for hardening the thermosetting resin composition in a flowing state over the entire area; and after the hardening step, the surface of the hardened material is not polished to form a metal pattern in contact with the conductor portion. Step, the aforementioned hardening step is a step of obtaining any of the structures in the following state (a) or (b), and when the aforementioned structure is in the state (a), in the aforementioned step of forming a metal pattern, The metal pattern is formed by the top contacting, and when the structure is in the following state (b), Before the step of forming the metal pattern, the method further includes a step of removing the surface layer by means other than polishing to expose the top portion. In the step of forming the metal pattern, the metal pattern is formed in contact with the exposed top portion.

(a) A state where the top of the conductor portion located in the height direction of the conductor portion is exposed

(b) A state where a surface layer made of the hardened material is attached to the top portion of the conductor portion located in the height direction of the conductor portion.

2. The method for manufacturing a semiconductor device according to 1, wherein the means other than the polishing is a chemical solution treatment or an etching treatment.

3． The method of manufacturing a semiconductor device according to 1 or 2, wherein the top portion located in the height direction of the conductor portion is electrically connected to the metal pattern by the step of forming the metal pattern.

4． The method for manufacturing a semiconductor device according to any one of 1 to 3, further comprising a step of arranging a release film so as to press the top of the conductor portion before the step of hardening.

5． The method for manufacturing a semiconductor device according to 4, wherein in the step of disposing the release film, an arithmetic average surface of a surface of the release film on one side is disposed so as to face the top of the conductor portion. The roughness (Ra) is 0 μm or more and 0.5 μm or less.

6. The method for manufacturing a semiconductor device according to any one of 1 to 5, further comprising a step of subjecting the surface of the hardened product to a chemical solution treatment after the step of hardening and before the step of forming a metal pattern.

7. The method for manufacturing a semiconductor device according to any one of 1 to 6, further comprising, after the step of hardening and before the step of forming a metal pattern, disposing the hardened material on the substrate or on the semiconductor wafer. A step of applying an adhesion promoter to a surface on one side of the conductor portion.

8. The method for manufacturing a semiconductor device according to any one of 1 to 7, further comprising a step of performing a plasma treatment on a surface of the hardened material after the step of hardening and before the step of forming a metal pattern.

9. The method for manufacturing a semiconductor device according to any one of 1 to 8, wherein the step of forming the plurality of conductor portions includes: a step of forming a first conductor pattern on the substrate or the semiconductor wafer; and the first conductor pattern A step of forming a second conductor pattern such that the height from the surface of the substrate or the semiconductor wafer becomes the same height.

10． The method of manufacturing a semiconductor device according to any one of 1 to 9, wherein the step of forming a metal pattern includes: a step of forming a metal film in contact with the top portion of the conductor portion; and selectively removing the metal Film to obtain the aforementioned metal pattern.

11. The method for manufacturing a semiconductor device according to any one of 1 to 10, wherein the thermosetting resin composition contains an epoxy resin, a hardener, and an inorganic filler.

12. The method for manufacturing a semiconductor device according to 11, wherein the thermosetting resin composition further contains a release agent.

Examples

Hereinafter, the present invention will be described based on examples and comparative examples, but the present invention is not limited to these.

First, the thermosetting resin composition used in each Example, a reference example, and a comparative example is demonstrated.

First, the raw material components of the thermosetting resin composition are shown below.

‧Epoxy resin 1: Biphenyl epoxy resin (manufactured by Mitsubishi Chemical Corporation, YX4000K)

‧Epoxy resin 2: Triphenol methane type epoxy resin (manufactured by Mitsubishi Chemical Corporation, E-1032H60)

‧Hardener: Triphenol methane phenol resin (MEIWA PLASTIC INDUSTRIES, LTD., MEH-7500)

‧Inorganic filler 1: Fused spherical silicon dioxide (manufactured by NIPPON STEEL & SUMIKIN MATERIALS Co., Ltd., TS-6026, using coarse sieve to remove coarse particles larger than 20 μm, average particle diameter d50: 4 μm)

‧Inorganic filler 2: Fused spherical silica (manufactured by Tatsumori Ltd., MSR-SC3-TS, those with coarse particles larger than 55 μm removed using a sieve, average particle diameter d50: 17 μm)

‧Inorganic Filling Material 3: Aluminum hydroxide (manufactured by Nippon Light Metal Co., Ltd., BE043, those with coarse particles larger than 20 μm in diameter removed by sieve, average particle diameter d50: 4 μm)

• Hardening accelerator: A compound represented by the following formula (1) is used. The manufacturing method will be described later.

‧Coupling agent 1: γ-aminopropyltriethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-903)

‧Coupling agent 2: γ-mercaptopropyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-803)

‧Releasing agent: palm wax (manufactured by TOA KASEI CO., LTD., TOWAX-132)

‧Ion trapping agent: Hydrotalcite (manufactured by Kyowa Chemical Industry Co., Ltd., DHT-4H)

‧Colorant: Carbon black (manufactured by Mitsubishi Chemical Corporation, carbon # 5)

‧Low stress agent 1: acrylonitrile-butadiene rubber (manufactured by UBE INDUSTRIES, LTD., CTBN1008SP)

‧Low stress agent 2: silicone oil (manufactured by Dow Corning Toray Co., Ltd., FZ-3730)

The manufacturing method of a hardening accelerator is shown below.

First, to a separable flask equipped with a cooling tube and a stirring device, 12.81 g (0.080 mol) of 2,3-dihydroxynaphthalene, 16.77 g (0.040 mol) of tetraphenylphosphonium bromide, and 100 ml of methanol were added, and the mixture was stirred uniformly so that Its dissolved. Next, a sodium hydroxide solution in which 1.60 g (0.04 ml) of sodium hydroxide was dissolved in 10 mL of methanol was slowly dropped into a separable flask. The precipitated crystal was filtered, washed with water, and dried under vacuum to obtain a hardening accelerator.

<Example 1>

Using the steps described in the first embodiment with reference to FIGS. 1 to 3, the semiconductor device 300 shown in FIG. 3 was manufactured as the semiconductor device of the first embodiment. The detailed steps are described below.

First, a rectangular cold-rolled steel sheet having a length of 240 mm and a width of 78 mm was prepared as the substrate 10. Next, a circuit was formed on the substrate 10 as the first conductor pattern 20 by photolithography, and then a plurality of metal pillars were formed as the second conductor pattern 30 on the first conductor pattern. Thereby, a plurality of conductor portions 40 including the first conductor pattern 20 and the second conductor pattern 30 are formed so that the top portions 92 of the plurality of conductor portions 40 are on the same horizontal plane.

The first conductor pattern 20 and the second conductor pattern 30 are formed of copper. The shape of the second conductor pattern 30 is a columnar shape. The photolithography method was performed so that the diameter of the bottom surface and the top surface of the second conductor pattern 30 was 50 μm, and the height of the second conductor pattern 30 from the substrate 10 was the same as 150 μm.

Here, the components in the amounts shown in Table 1 below were mixed using a mixer at normal temperature, and then biaxially kneaded at a temperature of 70 ° C. to 110 ° C. Next, after cooling to normal temperature, pulverization was performed to prepare a thermosetting resin composition 50 in a B-stage hardened state.

Next, using a compression molding method, the thermosetting resin composition 50 in a flowing state was introduced into the gap between the adjacent plurality of conductor portions 40.

In addition, the conditions for introducing the thermosetting resin composition 50 by a compression molding method are a molding temperature of 175 ° C, a molding pressure of 10 MPa, and a molding time of 2 minutes. Here, the top portion 92 of the conductor portion 40 is protected by the release film 100, thereby performing compression molding.

In addition, as the release film, AFLEX (registered trademark) 50KN144NT manufactured by ASAHI GLASS CO., LTD., Each having an embossed surface and an embossed surface, was used. Here, the embossed raw surface means a smooth surface. The top 92 of the conductor portion 40 is protected by embossing the unprocessed surface, and the embossing surface is brought into contact with the mold, so that the thermosetting resin composition 50 is introduced. With this, the thermosetting resin composition is introduced so that the top portions 92 of the plurality of conductor portions 40 are not buried by the thermosetting resin composition. The embossed raw surface of the release film 100 had an arithmetic average roughness (Ra) of 0.018 μm measured by a method in accordance with JIS-B0601-1994.

After the thermosetting resin composition 50 is introduced, a heat treatment is performed at a temperature of 175 ° C for 4 hours to harden the thermosetting resin composition 50, and a cured product 60 in a C-stage hardened state is prepared. Then, the release film 100 was peeled from the top part 92 of the conductor part. Here, a part of the top portion 92 of the conductor portion 40 has a surface layer made of a hardened material 60 on the order of several μm. Therefore, the surface layer was removed by performing a chemical solution treatment. Specifically, the chemical liquid treatment was performed with an aqueous potassium permanganate solution. After the chemical solution treatment, it was visually confirmed that the surface layer was completely removed, that is, the top portion 92 was exposed.

Next, a hardener 60 was coated with a Booster MR manufactured by Atotech Co., Ltd. as an adhesion aid, thereby forming a layer 80 composed of the adhesion aid. Next, a metal pattern 160 that is a circuit electrically connected to the top portion 92 is formed by a photolithography method, and a plating film 260 is formed on the metal pattern 160 and the conductor portion 40. The circuit line width / line interval (L / S) of the metal pattern was set to 12/12 μm.

Next, the substrate 10 was removed by chemical etching, and as a semiconductor device of Example 1, a multilayer wiring substrate was obtained.

<Example 2>

When a thermosetting resin composition 50 in a flowing state is introduced into a gap between a plurality of adjacent conductor portions 40 by a compression molding method, the top portion 92 of the conductor portion 40 is protected by an embossed surface, and A multilayered wiring board was obtained as the semiconductor device of Example 2 by the same method as in Example 1 except that the processed surface was brought into contact with the mold and the thermosetting resin composition 50 was introduced.

The embossed surface refers to a surface having an embossed shape.

The embossed surface of the release film 100 had an arithmetic average roughness (Ra) measured by a method in accordance with JIS-B0601-1994 of 1.247 μm.

<Example 3>

The semiconductor composition of Example 3 was produced in the same manner as in Example 1 except that the blend composition of the thermosetting resin composition described in Table 1 was changed from the inorganic filler 1 to the inorganic filler 2. Device.

The blending amount of the inorganic filler 2 was 78.85% by mass.

<Example 4>

Example 4 was produced in the same manner as in Example 1 except that the chemical liquid treatment for removing the surface layer was not performed, and the adhesion assistant was not applied, that is, the layer 80 composed of the adhesion assistant was not formed. Semiconductor device.

<Example 5>

In the method described in Example 1, the chemical liquid treatment for removing the surface layer was not performed, and the thermosetting resin composition 50 was hardened to form a hardened body 60 in a C-stage hardened state. Plasma treatment using O ₂ gas is performed to roughen the surface of the hardened material 60 without applying the adhesion assistant, that is, the layer 80 composed of the adhesion assistant is not formed. In the same manner as in Example 1, a semiconductor device of Example 5 was produced.

<Reference Example 1>

Using the steps shown in Figs. 8 (a) to 8 (b), a structure shown in Fig. 1 (f) (same as Fig. 8 (c)) was produced.

First, a rectangular cold-rolled steel sheet having a length of 240 mm and a width of 78 mm was prepared as the substrate 10. Next, a circuit was formed on the substrate 10 as the first conductor pattern 20 using a photolithography method, and then a plurality of metal pillars 91 were formed as the second conductor pattern 30 on the first conductor pattern. Thereby, a plurality of conductor portions 40 including the first conductor pattern 20 and the second conductor pattern 30 are formed so that the top portions 92 of the plurality of conductor portions 40 are on the same horizontal plane.

Here, as the thermosetting resin composition, the same one as the user in Example 1 was prepared.

Next, a compression-molding method was used to introduce a thermosetting resin composition 50 in a flowing state into the gap between the adjacent plurality of conductor portions 40.

In addition, the conditions for introducing the thermosetting resin composition 50 by a compression molding method are a molding temperature of 175 ° C, a molding pressure of 10 MPa, and a molding time of 2 minutes. Here, in the compression molding, the top portion 92 of the conductor portion 40 is not protected by the release film 100, and the top portion 92 of the plurality of conductor portions 40 is embedded in the thermosetting resin composition 50 to introduce the thermosetting property. Resin composition 50.

After the thermosetting resin composition 50 is introduced, a heat treatment is performed at a temperature of 175 ° C. for 4 hours to harden the thermosetting resin composition 50 to produce a cured product 60 in a C-stage hardened state.

Next, the surface of the hardened body 60 is mechanically polished using a polishing device, thereby exposing the top portion 92 of the conductor portion 40.

Next, the hardened body 60 was coated with a Booster MR manufactured by Atotech Corporation as an adhesion aid, thereby forming a layer 80 composed of the adhesion aid. Next, a metal pattern 160 that is a circuit electrically connected to the top portion 92 is formed by a photolithography method, and a plating film 260 is formed on the metal pattern 160 and the conductor portion 40. The circuit line width / line interval (L / S) of the metal pattern was set to 12/12 μm.

Next, the substrate 10 was removed by performing chemical etching, and as a semiconductor device of Reference Example 1, a multilayer wiring substrate was obtained.

<Comparative example 1>

Instead of the polishing device, a surface of the cured product 60 was polished using a chemical mechanical polishing device (CMP). Except for the above points, a semiconductor device of Comparative Example 1 was produced in the same manner as in Reference Example 1.

The chemical mechanical polishing device is a device that causes a chemical reaction based on an abrasive and performs mechanical polishing. Here, as the abrasive, Z4U manufactured by ANJI was used. The chemical mechanical polishing apparatus can obtain a high-speed and smooth polishing surface, but is not suitable for precise operations such as removing a surface layer.

In the semiconductor device of Comparative Example 1, the hardened material 60 was subjected to high-speed polishing by a chemical mechanical polishing device. However, the hardened material 60 was swelled due to the dissolution of the abrasive, thereby causing the inorganic filler to fall off. If the fall of the inorganic filler occurs, there is a concern that the electrical reliability of the semiconductor device may decrease.

As for the manufacturing methods of Examples 1 to 5, compared with the manufacturing methods of Reference Example 1 and Comparative Example 1, in the steps before forming the metal pattern, the resin layer composed of the cured product of the thermosetting resin composition was not passed The surface is polished and removed. Therefore, it is a method excellent in manufacturing efficiency of a semiconductor device in terms of reducing manufacturing time, manufacturing cost, and the like.

The semiconductor devices of Examples 1 to 5, Reference Example 1, and Comparative Example 1 were evaluated as follows.

<Evaluation item>

• Peel strength: In order to evaluate the adhesion between the hardened body 60 and the metal pattern 160 included in the semiconductor device, the peel strength of both was measured by a method in accordance with JIS C 6481. The unit is N / mm.

‧Arithmetic average surface roughness (Ra): In the manufacturing steps of the semiconductor device of each of the Examples, Reference Examples, and Comparative Examples, after the treatment of the chemical solution of Examples 1-3, the thermosetting resin composition of Example 4 was used. After hardening at 50 to produce a hardened product 60, after Example 5 series plasma treatment, Reference Example 1 was mechanically polished using a polishing device, and Comparative Example 1 was polished using a chemical mechanical polishing device. The surface provided with a metal pattern was measured and the arithmetic average surface roughness (Ra) was measured. The measurement was performed by a method in accordance with JIS B0601-2013. The unit is μm.

‧ Does the inorganic filler fall off? Regarding the hardened material 60 exposed on the surface on which one side of the metal pattern is arranged in the semiconductor device, the surface of the hardened material 60 is observed with a laser microscope, and whether the inorganic filler has fallen off the hardened material 60 did an evaluation. The evaluation criteria are as follows.

：: No drop of the inorganic filler.

(Circle): Although the fall of some inorganic fillers was confirmed, it is the level which is practically problem-free.

╳: The fall of the inorganic filler has occurred, and it has reached a practically problematic level.

‧ Whether there are circuit jumpers: For the semiconductor devices of each of the Examples, Reference Examples, and Comparative Examples, in order to evaluate the reliability of the electrical connection, the appearance inspection and continuity inspection of the thin wires were performed using a laser microscope. The evaluation criteria are as follows.

：: No short circuit or disconnection was confirmed, and there were no substantial problems in terms of appearance and continuity.

○: From the viewpoint of appearance, it is confirmed that there are several places that may affect the continuity. However, from the viewpoint of continuity, it is confirmed that there is no practical problem.

╳: It was confirmed that a short-circuit and a disconnection occurred, and that it was practically problematic in terms of appearance and continuity.

The evaluation results of the above evaluation items are shown in Table 2 below.

The semiconductor devices of the examples are all excellent in electrical connection reliability even if no mechanical method is used for the exposure of the conductive pillars.

In addition, Example 1 has a smaller surface roughness Ra than Example 3, but exhibits the same peel strength as Example 3. The detailed mechanism is not clear, but it is presumed that Example 1 and Example 3 have less exposure to the inorganic filler having poor adhesion to copper plating compared to Example 3.

This application claims priority based on Japanese Patent Application No. 2016-139453 filed on July 14, 2016, the entire contents of which is incorporated herein.

Claims (20)

    A method for manufacturing a semiconductor device, the method sequentially includes: forming a conductor portion: forming a plurality of conductor portions having the same height from a surface of the substrate on a substrate; and covering step: introducing thermal hardening into a gap between the adjacent conductor portions And a multilayered wiring step: the surface of the hardened material is not polished, and the hardened material is coated on the hardened material. A metal pattern is formed electrically connected to the top.         A method for manufacturing a semiconductor device, the method sequentially includes: a conductor portion forming step: forming a plurality of conductor portions on a semiconductor wafer, and using the semiconductor wafer and the semiconductor wafer in a manner that the heights of the conductor portions from a support are the same. The conductor portion is disposed on the support; a coating step: introducing a thermosetting resin composition into a gap existing between the adjacent conductor portions, and using the thermosetting resin composition so that the top of the conductor portion is exposed. A hardened object covers the conductor portion; and a multilayer wiring step: without polishing the surface of the hardened object, a metal pattern electrically connected to the top is formed on the hardened object, and after the covering step, it further includes separating the support body from the The separation step of the hardened material.         For example, in the method for manufacturing a semiconductor device according to claim 1 or 2, in the coating step, when the thermosetting resin composition is introduced into a gap between the conductor portions, a skin layer is formed on the top portion. The surface layer is removed by chemical methods.         For example, in the method for manufacturing a semiconductor device according to claim 1 or 2, in the coating step, before the thermosetting resin composition is formed into the cured product, a release film is disposed so as to press the top portion.         For example, the method for manufacturing a semiconductor device according to item 4 of the patent application, wherein the arithmetic mean surface roughness Ra of the surface of the release film pressing the top is 0 μm or more and 1.5 μm or less.         For example, the method for manufacturing a semiconductor device according to item 4 of the patent application, wherein the release film is a fluorine-based release film.         For example, in the method for manufacturing a semiconductor device according to claim 1 or claim 2, in the coating step, the surface of the cured product is roughened.         For example, the method for manufacturing a semiconductor device according to item 7 of the scope of patent application, wherein the roughening method is a chemical solution treatment or a plasma treatment.         For example, the method for manufacturing a semiconductor device according to claim 1 or 2, wherein, before the multilayer wiring step, the arithmetic average surface roughness Ra of the exposed surface of the top of the hardened object is 0.02 μm or more and 0.8 μm or less.         For example, the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the hardened state of the hardened material is a C-stage hardened state.         For example, in the method for manufacturing a semiconductor device according to claim 1 or claim 2, in the multi-layer wiring step, the surface of the hardened object is coated with an adhesion promoter, and then the metal pattern is formed.         For example, in the method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, in the step of forming the conductor portion, the conductor portion includes a first conductor pattern and a second conductor pattern, the first conductor pattern is a circuit, and the second The conductor pattern includes metal pillars.         For example, the method for manufacturing a semiconductor device according to claim 12 of the application, wherein the first conductor pattern and the second conductor pattern are formed by a photolithography method.         For example, the method for manufacturing a semiconductor device according to the first or second aspect of the patent application, wherein in the multilayer wiring step, the metal pattern is formed by a photolithography method.         For example, the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the thermosetting resin composition contains an epoxy resin, a hardener, and an inorganic filler.         For example, the method for manufacturing a semiconductor device according to item 15 of the application, wherein the particle diameter of the inorganic filler is less than 80 μm.         For example, in the method for manufacturing a semiconductor device according to claim 15, the average particle diameter d50 of the inorganic filler is 0.1 μm or more and 20 μm or less.         For example, the method for manufacturing a semiconductor device according to item 15 of the patent application, wherein two or more inorganic fillers having different average particle diameters are used simultaneously as the inorganic filler.         For example, the method for manufacturing a semiconductor device according to claim 15, wherein the thermosetting resin composition further contains a release agent.         A method for manufacturing a semiconductor device, the method sequentially includes: forming a plurality of conductor portions having the same height from a surface of the substrate or the semiconductor wafer on a substrate or a semiconductor wafer; on the substrate or the semiconductor wafer, A step of introducing a thermosetting resin composition in a flowing state into a gap existing between the adjacent conductor portions; covering the conductor portion facing the gap with a hardened material obtained by hardening the thermosetting resin composition; A method of hardening the thermosetting resin composition in a flowing state in a manner of substantially the entire area of the surface; and after the hardening step, the surface of the hardened material is not polished to form a metal contacting the conductor portion The step of patterning, the step of hardening is the step of obtaining any structure in the following state (a) or (b). When the structure is in the following state (a), in the step of forming a metal pattern, The metal pattern is formed so as to be in contact with the top. When the structure is in the following state (b), before the step of forming the metal pattern, it further includes an advantageous method. The step of removing the surface layer by means other than polishing to expose the top portion, and in the step of forming the metal pattern, the metal pattern is formed so as to be in contact with the exposed top portion, (a) is located in the height direction of the conductor A state in which the top of the conductor portion is exposed; (b) a state in which a surface layer made of the hardened substance is attached to the top of the conductor portion in the height direction of the conductor portion.