US7981963B2 - Insulation material of reactive elastomer, epoxy resin, curing agent and crosslinked rubber - Google Patents

Insulation material of reactive elastomer, epoxy resin, curing agent and crosslinked rubber Download PDF

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US7981963B2
US7981963B2 US11/733,689 US73368907A US7981963B2 US 7981963 B2 US7981963 B2 US 7981963B2 US 73368907 A US73368907 A US 73368907A US 7981963 B2 US7981963 B2 US 7981963B2
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epoxy resin
mass
insulation material
resin
layer
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US20070251721A1 (en
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Yukihiro Kiuchi
Masahiro Ishibashi
Yoshitaka Kyogoku
Masatoshi Iji
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31511—Of epoxy ether
    • Y10T428/31515—As intermediate layer
    • Y10T428/31522—Next to metal

Definitions

  • the present invention relates to an insulation material that forms a wiring board, to a wiring board that uses the insulation material, and to a semiconductor device provided with the wiring board.
  • a method has been developed in recent years whereby a plurality of solder balls is arrayed in the form of a matrix on the surface of a wiring board, and a semiconductor chip is mounted on the solder balls in order to obtain a smaller semiconductor device.
  • Examples of such a semiconductor device are FCBGA (Flip Chip Ball Grid Array) and WLCSP (Wafer Level Chip Size Package).
  • FCBGA Flexible Chip Ball Grid Array
  • WLCSP Wafer Level Chip Size Package
  • a multilayer wiring board in which a plurality of wiring-embedded resin layers is layered, a build-up wiring board with a so-called core member, and a package board includes MLTS (Multi Layer Thin Substrate) (brand name) structures.
  • MLTS Multi Layer Thin Substrate
  • Patent Document 1 a method is disclosed that uses an insulation material that has a modulus of elasticity of 10 GPa or higher as the material of the wiring board.
  • Patent Document 1 Japanese Laid-Open Patent Application No. 2002-198462
  • the above-described prior art has the problems described below.
  • the connection reliability of a semiconductor device in relation to temperature cycles is still insufficient even when the wiring board is formed from a material that has a modulus of elasticity of 10 GPa or higher, as described in Patent Document 1.
  • the base material which is the main component of the insulation material that forms the wiring board as described in Patent Document 1
  • the base material generally has low adhesiveness with the copper wiring when electroless copper plating is carried out on the surface to form the copper wiring.
  • an adhesive for improving the adhesiveness between the base material and the copper wiring is ordinarily added to the base material.
  • such adhesives have variable effect, and the effect of improving the plating adhesiveness cannot be obtained using conventional additives in combination with some base materials.
  • the present invention was contrived in view of the foregoing, and an object is to provide a wiring board that has high connection reliability in relation to temperature and has good adhesiveness between the insulation layer and the electroless copper plating, to provide an insulation material that forms the wiring board, and to provide a semiconductor device provided with the wiring board.
  • the insulation material of the present invention comprises a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent; an epoxy resin; an epoxy resin curing agent; and a crosslinked rubber having a double bond and a polar group in the structure thereof, wherein Young's modulus in a temperature range of 10 to 30° C. is 1 GPa or less.
  • the polar group may be a hydroxyl group or a carboxyl group
  • the crosslinked rubber is crosslinked styrene-butadiene rubber.
  • the value of (E ⁇ 100)/(A+B+C+E) is preferably 3 to 25%, and is more preferably 5 to 20%, wherein A mass % is the content of the reactive elastomer, B mass % is the content of the epoxy resin, C mass % is the content of the epoxy resin curing agent, and E mass % is the content of the crosslinked rubber.
  • the reactive elastomer is preferably a polyamide elastomer that does not contain a cyanate group in the structure of the elastomer, or is a flexible epoxy resin that contains an unsaturated double bond and an epoxy group in the structure of the elastomer.
  • the value of (A ⁇ 100)/(A+B+C+E) is preferably 15 to 80 mass %, and more preferably to 50 to 75 mass %.
  • the value of (B ⁇ 100)/(A+B+C+E) is preferably 20% or less. The elongation at break is thereby improved.
  • the wiring board of the present invention uses the above-described insulation material.
  • the wiring board can follow the thermal expansion of external elements when the wiring board becomes heated or cooled after semiconductor chips or other external elements have been mounted to form a semiconductor device on the wiring board, by forming the wiring board from an insulation material that has a relatively low Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. Warping of the semiconductor device can thereby be reduced, and the force applied to the connection portion between the wiring board and the external elements can be reduced. Accordingly, the connection reliability in relation to temperature cycles of the semiconductor device can be improved.
  • the adhesiveness between the insulation layer and the copper plating layer can be improved when copper plating is formed by electroless plating on an insulation layer composed of the insulation material because the insulation material contains a crosslinked rubber having a double bond and a polar group in the structure of the insulation material.
  • the semiconductor device of the present invention is provided with the above-described wiring board.
  • the wiring board can follow the thermal expansion of external elements when external elements are mounted on the wiring board, by forming the wiring board from an insulation material that has a Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. Therefore, warping of the wiring board can be reduced, fracturing of the connection portion can be prevented, and connection reliability in relation to temperature cycles can be improved.
  • the adhesiveness between the electroless copper plating layer and the insulation layer composed of the insulation material can be improved because the insulation material contains a crosslinked rubber having a double bond and a polar group in the structure of the insulation material.
  • FIG. 1 is a cross-sectional view showing the semiconductor device of the embodiments of the present invention.
  • FIG. 2 is a schematic view showing the characteristics of the semiconductor device
  • FIG. 3 is a diagram showing a schematic of the evaluation board fabricated in the test example of the present invention.
  • FIG. 4 is a top view showing the specifics of the evaluation board.
  • FIG. 5 is a partial enlarged cross-sectional view of the evaluation board.
  • FIG. 1 is a cross-sectional view showing the semiconductor device of the embodiments of the present invention
  • FIG. 2 is a schematic view showing the characteristics of the semiconductor device.
  • the semiconductor device 1 according to the present embodiment is an FCBGA semiconductor device, as shown in FIG. 1 .
  • a package board 2 is disposed in the semiconductor device 1 .
  • the package board 2 formed by layering a plurality of wiring layers, and wiring 3 composed of, e.g., copper, and vias 4 connected to the wiring 3 are formed in the wiring layers.
  • a plurality of mounting pads 5 is formed on a wiring layer 16 (see FIG. 2 ), which is the topmost layer of the package board 2 .
  • the wiring 3 , vias 4 , and mounting pads 5 may also be generically referred to as “wiring.”
  • a plurality of ball pads 6 is formed on the lower surface of the package board 2 .
  • the mounting pads 5 and ball pads 6 are each arrayed in the form of a matrix as viewed from directly above (hereinafter referred to as “plan view”) on the upper surface of the package board 2 .
  • the ball pads 6 are larger than the mounting pads 5 , and the array pitch of the ball pads 6 is greater than the array pitch of the mounting pads 5 .
  • the mounting pads 5 are connected to the ball pads 6 by way of the wiring 3 and vias 4 .
  • Solder bumps 7 are connected to the mounting pads 5
  • BGA balls 8 are connected to the ball pads 6 .
  • the BGA balls 8 are larger than the solder bumps 7 .
  • a semiconductor chip 9 is mounted on the package board 2 .
  • the semiconductor chip 9 is composed of, e.g., multilayered wiring layers (not shown) disposed on a silicon substrate (not shown), and an integrated circuit is formed on the surface of the silicon substrate and the multilayered wiring layer.
  • the surface of the multilayered wiring layer in the semiconductor chip 9 has I/O pads (not shown) disposed on the surface of the side that faces the package board 2 , and the I/O pads are connected to the solder bumps 7 .
  • the I/O pads of the semiconductor chip 9 are thereby connected to the mounting pads 5 by way of the solder bumps 7 , and are connected to the BGA balls 8 by way of the wiring 3 , vias 4 , and ball pads 6 .
  • An underfill resin 10 is filled about the periphery of the solder bumps 7 between the package board 2 and semiconductor chip 9 .
  • the semiconductor chip 9 is thereby connected and fixed to the package board 2 .
  • a stiffener 11 composed of stainless steel or copper is disposed in the area surrounding the semiconductor chip 9 on the package board 2 .
  • the stiffener 11 is bonded to the package board 2 using an adhesive layer 15 .
  • the stiffener 11 is frame-shaped in a plan view, and the semiconductor chip 9 is accommodated in the open area of the frame shape.
  • the upper surface of the stiffener 11 is substantially in the same plane as the semiconductor chip 9 .
  • a lid 12 composed of, e.g., ceramic is disposed on the semiconductor chip 9 and stiffener 11 .
  • the lid 12 is bonded to the semiconductor chip 9 using an adhesive layer 13 and to the stiffener 11 using an adhesive layer 14 .
  • the shape of the lid 12 is a shape that substantially overlaps the package board 2 in a plan view.
  • the lid 12 functions as a heat sink for the semiconductor chip 9 .
  • the semiconductor device 1 is mounted on a motherboard (not shown) or the like by way of BGA balls 8 .
  • the wiring layer 16 disposed on the topmost wiring layer of the package board 2 is formed from an insulation material that has a Young's modulus of 1 GPa or less when the temperature is between 10 and 30° C. (hereinafter referred to as “room temperature”) and that has an elongation at break of 20% or higher.
  • This insulation material contains a reactive elastomer (A) that can react with epoxy resin or an epoxy resin curing agent; an epoxy resin (B); an epoxy resin curing agent (C); and a crosslinked rubber as an additive (E) having a double bond and a polar group in the structure of the material.
  • the ratio of crosslinked rubber in the resin component i.e., the value of (E ⁇ 100)/(A+B+C+E), is 3 to 25 mass %, and may be, e.g., 5 to 20 mass %, wherein A mass % is the content of the reactive elastomer, B mass % is the content of the epoxy resin, C mass % is the content of the epoxy resin curing agent, and E mass % is the content of the crosslinked rubber.
  • the ratio of the reactive elastomer (A) in the resin component i.e., the value of (A ⁇ 100)/(A+B+C+E), is 15 to 80 mass %, and is preferably 50 to 75 mass %.
  • the ratio of the reactive elastomer (A), i.e., the value of (A ⁇ 100)/(A+B+C+E) is 50 to 75 mass %, an insulation material of high elongation and low elasticity can be obtained.
  • the ratio of the epoxy resin (B) in the resin component, i.e., the value of (B ⁇ 100)/(A+B+C+E), is 20% or less.
  • the value of (E ⁇ 100)/(A+B+C+E) is less than 3%, the bonding characteristics of the electroless copper plating are sometimes insufficient.
  • the value exceeds 25% the elongation of the insulation material may be reduced, or the physical properties of the insulation material may be otherwise insufficient. Therefore, the value of (E ⁇ 100)/(A+B+C+E) is preferably 3 to 25%, and more preferably 5 to 20%.
  • the ratio of the reactive elastomer (A) in the resin component of the insulation material i.e., the value of (A ⁇ 100)/(A+B+C+E)
  • the reactive elastomer that assures the toughness of the insulation material is insufficient, and sufficient elongation at break cannot be obtained.
  • the value exceeds 80% the curability of the insulation material becomes insufficient, and chemical resistance of the insulation material may be reduced and also electroless plating property may be degraded.
  • the value exceeds 80% the semi-hardened insulation material of the present embodiment can not be melted with sufficient fluidization.
  • the insulation material can not be added to the rough surface of the copper foil with the sufficient adhesiveness and the reliability of the connection may be degraded. Therefore, the value of (A ⁇ 100)/(A+B+C+E) is preferably 15 to 80 mass %.
  • the value of (B ⁇ 100)/(A+B+C+E) is preferably 20 mass % or less.
  • the crosslinked rubber (E) having a double bond and a polar group described above is a crosslinked styrene-butadiene rubber having a carboxylic group or a hydroxyl group as a polar group, and en example is XSK-500 (registered trade name) manufactured by JSR.
  • the double bond is contained in the butadiene moiety.
  • the reactive elastomer (A) is preferably a polyamide elastomer that does not contain a cyanate group in the structure of the elastomer.
  • the reactive elastomer (A) is a polyamide-polybutadiene copolymer that contains a phenolic hydroxyl group.
  • the phenolic hydroxyl group-containing polyamide-polybutadiene copolymer (hereinafter also referred to simply as “copolymer”) is obtained by reacting a phenolic hydroxyl group-containing dicarboxylic acid expressed by chemical formula 1 described below, a dicarboxylic acid that does not contain a phenolic hydroxyl group expressed by chemical formula 2 described below, a diamine expressed by the chemical formula 3 described below, and a polybutadiene that has a carboxylic group at the two ends expressed by the chemical formula 4 described below or a poly butadiene that has an amino group at the two ends expressed by the chemical formula 5 described below.
  • the phenolic hydroxyl group-containing polyamide-polybutadiene copolymer is expressed by the general chemical formulas 6 or 7 described below.
  • R 1 in chemical formulas 1, 6, and 7 is a bivalent aromatic compound with a carbon number of 6 to 12 having a phenolic hydroxyl group.
  • Examples of the dicarboxylic acid having phenolic hydroxyl group expressed in the above-noted chemical formula 1 include 5-hydroxyisophthalic acid, 4-hydroxyisophthalic acid, 2-hydroxyphthalic acid, 3-hydroxyhthalic acid, and 2-hydroxyterephthalic acid.
  • HOOC—R 2 —COOH [Chemical formula 2]
  • R 2 in chemical formulas 2, 6, and 7 is a bivalent aromatic compound having a carbon number of 6 to 12 that does not contain a phenolic hydroxyl group or a bivalent aliphatic compound having a carbon number of 1 to 10.
  • Examples of a dicarboxylic acid that does not contain a phenolic hydroxyl group expressed the above-noted chemical formula 2 include phthalic acid, isophthalic acid, terephthalic acid, dicarboxylic naphthalene, succinic acid, fumaric acid, glutaric acid, adipic acid, 1,3-cyclohexanedicarboxylic acid, 4,4′-diphenyl dicarboxylic acid, and 3,3′-methylenedibenzoic acid.
  • R 3 in chemical formulas 3, 6, and 7 is a bivalent aromatic compound having a carbon number of 6 to 12 or a bivalent aliphatic compound having a carbon number of 1 to 10.
  • diamines that contain a phenolic hydroxyl group among the diamines expressed by chemical formula 3 noted above include 3,3′-diamine-4,4′-dihydroxyphenylmethane, 2,2′-bis(3-amino-4-hydroxyphenyl)hexafluoropropane, 2,2′-bis(3-amino-4-hydroxyphenyl)difluoromethane, 3,4′-diamino-1,5′-benzendiol, 3,3′-dihydroxy-4,4′-diaminobisphenol, 3,3′-diamino-4,4′-dihydroxybisphenol, 2,2′-bis(3-amino-4-hydroxyphenyl)ketone, 2,2′-bis(3-amino-4-hydroxyphenyl)sulfide
  • x and y are average degrees of polymerization and are integers from 3 to 7.
  • copolymer particularly preferred among the copolymers expressed by the chemical formulas 6 and 7 is a copolymer expressed by the general chemical formulas 8 and 9 below.
  • the weight-average molecular weight (Mw) of the copolymer is 100,000 or less, sufficient fluidity can be obtained in a temperature range of 160 to 180° C. In particular, good fluidity can be obtained in a temperature range of 100 to 160° C. when the weight-average molecular weight (Mw) is 20,000 or less. Therefore, the weight-average molecular weight (Mw) of the copolymer is preferably 100,000 or less, and more preferably 20,000 or less.
  • a flexible epoxy resin that contains an unsaturated double bond and an epoxy group in the structure of the resin may be used as the reactive elastomer (A) in place of the polyamide elastomer that does not contain a cyanate group in the above-described structure.
  • R 4 in chemical formula 10 is hydrogen or a univalent substituent group having a carbon number of 1 to 3.
  • a1 is an integer from 1 to 4
  • a1′ is an integer from 1 to 3
  • X is the compound X 1 expressed by the chemical formula 12 below or is the compound X 2 expressed by the chemical formula 13 below
  • b is an integer from 1 to 10
  • c and d are both 1.
  • the resin (D) in which the distance between the functional groups is greater than that of the phenol novolac resin expressed by the chemical formula 10 has a phenolic hydroxyl group as a functional group, e.g., is ethylene oxide, and an example of the resin is an ethylene oxide compound in which the distance between the phenolic hydroxyl groups in the molecular structure is greater than the distance between the phenolic hydroxyl groups in the phenol novolac resin.
  • An example of the ethylene oxide compound is expressed by chemical formula 11 below.
  • R 4 in chemical formula 11 is hydrogen or a univalent substituent group having a carbon number of 1 to 3.
  • a2 is an integer from 1 to 4
  • a2′ is an integer from 1 to 3
  • X′ is the compound X 1 expressed by the chemical formula 12 below or is the compound X 2 expressed by the chemical formula 13 below
  • b′ is an integer from 1 to 10
  • c′ and d′ are both 1.
  • R 5 in chemical formula 12 is hydrogen or a univalent substituent group having a carbon number of 1 to 3.
  • e is an integer from 1 to 4
  • f is an integer from 0 to 9.
  • R 6 in chemical formula 13 is hydrogen or a univalent substituent group having a carbon number of 1 to 3.
  • g is an integer from 1 to 4
  • h is an integer from 0 to 9.
  • the resin expressed by the chemical formulas 10 and 11 above is configured such that the distance between the functional groups is greater than that of phenol novolac resin expressed by the chemical formula 14 below.
  • the epoxy resin (B) is not particularly limited, but is preferably an epoxy resin in which the distance between the functional groups is greater than that of phenol novolac epoxy resin.
  • the reason for this is that such an epoxy resin can efficiently form an IPN structure, and as a result, the elongation at break of the insulation material according to the present embodiment can be improved.
  • Examples of such an epoxy resin in which the distance between the functional groups is greater than that of phenol novolac epoxy resin include phenol biphenylene aralkyl epoxy resin, phenol xylene aralkyl epoxy resin, phenol diphenyl ether aralkyl epoxy resin, bifunctional biphenyl epoxy resin, anthracene-containing novolac epoxy resin, fluorene-containing novolac epoxy resin, bisphenol fluorene-containing novolac epoxy resin, phenol biphenylene triazine epoxy resin, and phenol xylene triazine epoxy resin.
  • Additional examples are phenoxy resins, which have an epoxy group at both ends and are bisphenol A, bisphenol F, bisphenol S, or bisphenol backbone-containing resins. The phenoxy resin has a weight-average molecular weight of about 20,000 to 100,000 in terms of polystyrene. Any of these epoxy resins may be used alone or in a plural mixture as the epoxy resin (B).
  • epoxy resins other than epoxy resins having a long distance between the functional groups as described above are not particularly limited.
  • examples include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol S epoxy resin, naphthalene diol epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin, bisphenol F-containing novolac epoxy resin, bisphenol A-containing novolac epoxy resin, phenol triazine epoxy resin, cresol triazine epoxy resin, tetraphenylol ethane epoxy resin, trisphenylol ethane epoxy resin, polyphenol epoxy resin, aliphatic epoxy resin, aromatic ester epoxy resin, cycloaliphatic ester epoxy resin, and ether ester epoxy resin.
  • components other than the resin (D) in which the distance between the functional groups is greater than that of the phenol novolac resin described above are not particularly limited.
  • examples of such components include bisphenol A phenolic resin, bisphenol F phenolic resin, bisphenol S phenolic resin, dihydroxy ether of a biphenyl isomer, naphthalene diol resin, phenol novolac resin, cresol novolac resin, phenol diphenyl ether aralkyl resin, naphthalene-containing novolac resin, anthracene-containing novolac resin, fluorene-containing novolac resin, bisphenol fluorene-containing novolac resin, bisphenol F-containing novolac phenolic resin, bisphenol A-containing novolac phenolic resin, phenol biphenylene triazine resin, phenol xylene triazine resin, phenol triazine resin, cresol novolac triazine
  • diamino diphenyl ethane, diethylene triamine, diaminodiphenyl sulfone, and other amine-based compounds may be contained as components of the epoxy resin curing agent (C).
  • Phenoxy resins that are bisphenol A, bisphenol F, bisphenol S, or bisphenol backbone-containing resins, and have a hydroxyl group at one or both ends may also be used.
  • the phenoxy resin has a weight-average molecular weight of about, e.g., 20,000 to 100,000 in terms of polystyrene. Any of these epoxy resins may be used alone or in a plural mixture as the epoxy resin curing agent (C).
  • the insulation material of the present embodiment may contain an inorganic filler.
  • an inorganic filler When an inorganic filler is used, the mass ratio of the inorganic filler of the total weight of the reactive elastomer (A), the epoxy resin (B), the epoxy resin curing agent (C), and the inorganic filler in the present invention is preferably 50 mass % or less. When the mass ratio of the inorganic filler exceeds 50 mass %, elongation at break may be reduced, Young's modulus may be increased, and the stress reducing characteristics may be insufficient.
  • fillers can be used as the inorganic filler, and examples include fused silica, crystal silica, alumina, zircon, calcium silicate, calcium carbonate, silicon carbide, silicon nitride, boron nitride, beryllia, talcum (talc), isinglass (mica), titanium oxide, zirconia, and other powders, or beads composed of these materials formed into spherical shapes; calcium titanate, silicon carbide, silicon nitride, boron nitride, alumina, and other monocrystalline fibers; aluminum hydroxide, magnesium hydroxide, zinc borate, and other metal hydrates, the above-noted metal hydrates that have been surface treated using epoxy resin, phenolic resin, and various other organic substances; and magnesium hydroxide and various other hydroxides in which the metal has been formed into a solid solution to improve acid resistance.
  • These fillers may be used alone, or in a combination of two or more.
  • the insulation material of the present embodiment may contain a curing acceleration catalyst.
  • a catalyst that is generally used to cure epoxy resins and curing agents may be used as the curing acceleration catalyst, but this does not impose any limitation. Examples include imidazoles, diazabicycloalkenes, diazabicycloalkene derivatives, and tertiary amines. These curing acceleration catalysts may be used alone or in a combination of two or more.
  • organosilane compounds as required in the insulation material in the present embodiment, including silicon rubber, silicone powder, acrylonitrile-butadiene rubber (NBR), indene, and other flexibility-imparting agents.
  • organosilane compounds, organic titanate compounds, and organic aluminate compounds, and other coupling agents may be appropriately added.
  • organosilanes as silane coupling agents i.e., alkoxysilanes that have reactive functional groups, are effective for improving solder heat resistance and adhesiveness of the insulation material according to the present embodiment.
  • alkoxysilanes include ⁇ -aminopropyltrimethoxysilane, N-phenyl- ⁇ -aminopropyltriethoxysilane, and other aminosilane compounds; ⁇ -glycidoxypropyltrimethoxysilane, ⁇ -glycidoxypropylmethyldiethoxysilane, and other epoxysilane compounds; ⁇ -mercaptopropyltrimethoxysilane, and other mercaptosilane compounds; and ⁇ -ureidopropyltriethoxysilane and other ureidosilane compounds.
  • components used in rust-preventive agents capable of bonding with copper surfaces may be added as adhesiveness improvers between the insulation material and the copper foil surface to the insulation material of the present embodiment.
  • triazol compounds include 1,2,3-benzotriazole and tolyltriazole.
  • mercapto compounds include 2,4,6-trimercapto-s-triazine, 2-di-n-butylamino-4,6-dimercapto-s-triazine, and 2-anilino-4,6-dimercapto-s-triazine.
  • An example of an imidazole copper complex is 2-methylimidazole copper (2) complex.
  • Flame retardants may be added as required to the insulation material of the present embodiment.
  • flame retardants include halogen flame retardants, nitrogen flame retardants, phosphorus flame retardants, and inorganic flame retardants.
  • halogen flame retardants include brominated-bisphenol A resins and epoxidated brominated-bisphenol A resins.
  • an additive compounds that are nitrogen-based flame retardants include melamine and isocyanuric acid compounds.
  • reactive compounds that are nitrogen-based flame retardants include phenol triazine curing agents and epoxy resins.
  • phosphorus flame retardants include red phosphorus, phosphate compounds, and organic phosphorus compounds.
  • inorganic flame retardants include the above-noted metal hydrates, zinc molybdate, zinc stannate, and compounds in which zinc molybdate or zinc stannate covers the surface of talc or silica. Also, when halogen flame retardants are used in combination with antimony oxide, very good flame resistance can be achieved.
  • the insulation material of the present embodiment may contain known substances other than those listed above as long as the reliability of the semiconductor device that uses the insulation material is not reduced.
  • examples of other substances that may be added include pigments, antioxidants, and organic solvents.
  • the semiconductor device 1 is wherein a semiconductor chip 9 is mounted on the topmost layer of a package board 2 by way of a plurality of solder bumps 7 , wherein a wiring layer 16 composed of a resin that has a Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. is disposed on the topmost layer of the package board, as shown in FIG. 2 . Constituent elements other than those described above are not shown in FIG. 2 .
  • FIG. 1 a method for manufacturing the semiconductor device of the present embodiment is described with reference to FIG. 1 .
  • two support boards (not shown) composed of copper or another metal material are prepared, and the two support boards are laminated together.
  • an Ni (nickel) layer, an Au (gold) layer, an Ni layer, and a Cu (copper) layer are plated in the stated order to form a multilayered film on the two sides of the laminated support boards.
  • the multilayered film is patterned by leaving only the portions in which the mounting pads 5 are to be formed, and removing the remainder.
  • a semi-cured resin film is layered so as to embed the patterned multilayered film.
  • the resin film is formed from an insulation material in which the elongation at break is 20% or higher and the Young's modulus in a temperature range of 10 to 30° C. is 1 GPa or less.
  • the film is then heated and cured to form an insulation layer.
  • holes are formed in the insulation layer using laser or the like so as to reach the multilayered film.
  • the interior of the holes is covered with a metal plating film to form vias 4 .
  • a first wiring layer in which a multilayered film and vias 5 are embedded in the insulation layer is thereby formed on the two surfaces of the two support boards.
  • a wiring layer 3 is formed on the first wiring layer so as to be connected to the vias 4 , and a semi-cured resin film is layered and heat cured so as to embed the wiring layer 3 to form an insulation layer.
  • Vias 4 are formed so as to be connected to the wiring layer 3 in the insulation layer, and a second wiring layer in which the wiring layer 3 and the vias 4 in the insulation layer are embedded is formed.
  • the third layer and other wiring layers are sequentially formed using the same process as the second wiring layer. After all the wiring layers have been formed, the ultimately formed wiring layer is chemically plated or etched to form ball pads 6 . A plurality of wiring layers is thereby layered on the two surfaces of the laminated support boards to form a package board 2 .
  • the two support boards are separated from each other.
  • An alkaline solution is used to remove the support boards.
  • An acidic solution is then used to remove the Ni layer of the multilayered film.
  • the mounting pads 5 are thereby formed in which an Au layer, an Ni layer, and a Cu layer are formed in the stated order.
  • a stiffener 11 is thereafter bonded to the surface of the side on which the mounting pads 5 are formed, by way of an adhesive layer 15 in the package board 2 to fabricate a “board having a stiffener.”
  • solder bumps 7 are joined to the I/O pads (not shown) of the semiconductor chip 9 to fabricate a “chip having solder bumps.”
  • the “chip having solder bumps” is connected to the “board having a stiffener” so that the solder bumps 7 of the “chip having solder bumps” are connected to the mounting pads 5 of the “board having a stiffener.”
  • An underfill resin 10 is subsequently filled, heated, and cured so as to embed the solder bumps 7 between the semiconductor chip 9 and the package board 2 and the vicinity thereof.
  • a lid 12 is bonded by way of adhesives 13 and 14 to the upper surface of the stiffener 11 and semiconductor chip 9 , i.e., the surface of the side opposite from the surface on which the package board 2 is bonded.
  • BGA balls 8 are then bonded to the ball pads 6 formed on the lower surface of the package board 2 to thereby manufacture a semiconductor device 1 .
  • the supporting boards When the supporting boards are removed, only the center portions are removed and the peripheral portions are left behind in the form of a frame.
  • the remaining portion of the support boards may be used as the stiffener 11 .
  • the removal of the support boards and the formation of the stiffener 11 can thereby be performed simultaneously, and the adhesive layer 15 becomes unnecessary.
  • the semiconductor device 1 is mounted on a motherboard (not shown) by way of BGA balls 8 , as shown in FIGS. 1 and 2 .
  • the motherboard is, e.g., an FR-4 board or an FR-5 board, and is a glass epoxy board in which a glass cloth has been immersed in epoxy resin, for example.
  • a power source potential and signals are inputted to the semiconductor device 1 by way of the motherboard.
  • the power source potential and signals are inputted to the semiconductor chip 9 by way of an electric current pathway composed of the following the sequence: BGA balls 8 , ball pads 6 , vias 4 and wiring layer 3 , mounting pads 5 , and solder bumps 7 .
  • the semiconductor chip 9 stores signals, performs calculations, and otherwise processes information on the basis of the inputted power source electric potential and signals, and outputs the results.
  • the outputted signals are outputted to the motherboard by way of an electric current pathway composed of the following sequence: solder bumps 7 , mounting pads 5 , vias 4 and wiring layer 3 , ball pads 6 , and BGA balls 8 ; and is then outputted to the exterior by way of the motherboard.
  • the wiring layer 16 which is the topmost layer of the package board 2 , is formed from an insulation material that has a relatively low Young's modulus of 1 GPa or less. Therefore, the wiring layer 16 can deform in accordance with the thermal expansion of the semiconductor chip 9 . As a result, the force exerted between the semiconductor chip 9 and package board 2 is reduced, and a large force is not applied to the solder bumps 7 . In a similar fashion, when the semiconductor device 1 is heated or cooled by changes in the ambient temperature, the heat stress exerted between the semiconductor chip 9 and package board 2 is reduced by the deformation of the wiring layer 16 , and an excessively large force is not applied to the solder bumps 7 . As a result, the semiconductor device 1 does not warp and the solder bumps 7 do not become fractured.
  • the topmost layer of the package board 2 i.e., the wiring layer 16 of the semiconductor chip 9 side is formed from a material that has a relatively low Young's modulus of 1 GPa or less when the temperature is 10 to 30° C. Therefore, an excessively large force is not applied to the solder bumps 7 even when a temperature cycle is applied to the semiconductor device 1 due to the operation of the semiconductor chip 9 or changes in the ambient temperature, and the solder bumps 7 can be prevented from becoming fractured. It is possible to prevent the solder bumps 7 from becoming fractured by the fatigue brought on by the repeated application of heat stress on the solder bumps 7 . Accordingly, the semiconductor device 1 has high connection reliability in relation to temperature cycles.
  • the wiring layer is conventionally formed from a material that has a Young's modulus that is as high as possible, i.e., a hard material, so as to reduce deformations caused by heat stress. For this reason, the heat stress is concentrated in the solder bumps, and the solder bumps become fractured.
  • the insulation material that forms the wiring layer 16 contains crosslinked rubber that has a double bond and a polar group in the structure of the material. Therefore, electroless copper plating properties are good, and adhesiveness between the Cu layer and the wiring layer 16 is higher when the Cu layer is formed on the wiring layer 16 using an electroless plating method.
  • the Young's modulus of the insulation material is stable and is kept at 1 GPa or less by adding the crosslinked rubber described above to the insulation material.
  • the present invention is not limited to this configuration, and the two or more wiring layers comprising the topmost layer may be formed from an insulation layer that contains the crosslinked rubber (E) and has a Young's modulus of 1 GPa or less, or all of the wiring layers of the package board 2 may be formed from this insulation material.
  • E crosslinked rubber
  • the entire package board 2 can thereby deform, and the effect of reducing heat stress can be further enhanced.
  • the wiring bottommost wiring layer of the package board 2 i.e., the wiring layer facing the motherboard (not shown) in the package board 2
  • the bottommost wiring layer of the package board 2 can thereby deform in accordance with the thermal expansion of the motherboard, and the thermal stress applied to the BGA balls 8 can be reduced. As a result, warping of the semiconductor device 1 and fatigue fracturing of the BGA balls 8 can be prevented and the connection reliability in relation to temperature cycles can be improved.
  • the amount of elongation at break of the insulation material that forms the bottommost wiring layer of the package board 2 described above is preferably 50% or higher.
  • Ball pads 6 and BGA balls 8 may be disposed on the surface of the side on which the semiconductor chip 9 are mounted of the package board 2 , and the BGA balls 8 may be connected to the motherboard.
  • a solder paste may be disposed instead of solder bumps 7 .
  • the insulation material described in the embodiment above was actually fabricated; a laminate film, a single-sided copper laminate sheet, an FCBGA semiconductor device, and other sample materials were fabricated using the resin material; and the results were evaluated. Described first are the components that form the resin material of the examples and comparative examples. TABLE 1 shows each of these components, i.e., the reactive elastomers (A), the epoxy resin (B), and the epoxy resin curing agent (C).
  • the resin (D) in which the distance between the functional groups is greater than that of phenol novolac resin is one type of the epoxy resin curing agent (C).
  • TABLE 2 shows the additives (E) that are added to the resin materials.
  • the flexible epoxy resin (A3) is Epofriend AT501 (registered trade name) manufactured by Daicel Chemical Industries, and the styrene percentage content is 40 mass %.
  • the flexible epoxy resin (A4) is Epofriend AT504 (registered trade name) manufactured by Daicel Chemical Industries, and the styrene percentage content is 70 mass %.
  • the styrene-butadiene rubber (E1) is a crosslinked styrene-butadiene rubber having an OH group, a COOH group, or other polar functional groups.
  • the rubber may be XSK-500 (registered trade name) manufactured by JSR, and an L711ST/MEK solution can be used.
  • the solid concentration is 20 mass %, and the viscosity is 460 mPas.
  • the epoxy-containing polybutadiene rubber (E2) is Epolead PB3600 (registered trade name) manufactured by Daicel Chemical Industries, has a molecular weight of 5,900, and has an epoxy equivalent of 200 g/eq.
  • the end-epoxidated polybutadiene rubber (E3) is Denarex R-45EPT (registered trade name) manufactured by Nagase Chemtex, and the epoxy equivalent is 1,570 g/eq.
  • the core-shell acrylic rubber particles (E4) is Metablen KW-4426 (registered trade name) manufactured by Mitsubishi Rayon.
  • the calcium carbonate (E5) is Caltex 5 (registered trade name) manufactured by Maruo Calcium.
  • TABLES 4 to 6 A number of components were selected from among the components described above, as shown in TABLES 4 to 6, and were dissolved and dispersed in an organic solution together with a curing acceleration catalyst.
  • TABLE 3 shows the curing acceleration catalyst and organic solutions used in this case. For example, No.
  • TABLE 4 was prepared as a mixture by adding 0.05 mass % of the imidazole catalyst shown in TABLE 3 as the curing acceleration catalyst to a resin material containing 67.5 mass % of a polyamide elastomer which does not contain a cyanate (CN) group (A1) as the reactive elastomer (A), 16.84 mass % of a phenol biphenylene aralkyl epoxy resin (B1) as the epoxy resin (B), 5.66 mass % of a p-cresol novolac resin (C1) as the epoxy resin curing agent (C), and 10 mass % of a styrene-butadiene rubber (E1) as the additive (E), wherein the mass ((A)+(B)+(C)+(E)) of the resin material was 100 mass %.
  • CN cyanate
  • This mixture was dissolved and dispersed in an organic solvent (N,N-dimethylformamide: DMF) to prepare a varnish solution in which the total amount of the non-volatile components, i.e., the components other than the organic solvent, was 30 mass %.
  • an organic solvent N,N-dimethylformamide: DMF
  • the numerical values noted in the rows corresponding to the components indicate the mass ratios of the components in the resin component.
  • the mass ratio of the reactive elastomer A1 in relation to the entire resin component i.e., the value of (A1 ⁇ 100)/(A+B+C+E)
  • the mass ratio of the reactive elastomer A1 in relation to the entire resin component i.e., the value of (A1 ⁇ 100)/(A+B+C+E)
  • the mass ratio of the reactive elastomer A1 in relation to the entire resin component i.e., the value of (A1 ⁇ 100)/(A+B+C+E)
  • the A1 mass % is the content of the reactive elastomer A1.
  • the abbreviation “phr” refers to “per hundred resin” and expresses the
  • the above-described varnish solution was uniformly coated onto a polyethylene terephthalate (PET) film on which a release agent had been coated, using a coating machine so as to obtain a target thickness.
  • the film was thereafter dried for 5 minutes at a temperature of 100° C. to volatilize the solution at a constant rate.
  • the resin surface was covered using a PET film having a release agent and a three-layer laminate film; i.e., a laminate film having the configuration “release PET layer/resin layer/release PET layer” was fabricated.
  • the resin layer (including the remaining solution) in the laminate film was in an uncured state.
  • the above-described laminate film was layered onto the copper foil of the two sided copper-layered plate in which copper foil had been layered on both sides of the resin board, and the film was then cured.
  • the curing was carried out for 30 minutes under a pressure of 1.5 MPa at a temperature of 120° C., and thereafter carried out for 120 minutes under a pressure of 3 MPa at a temperature of 180° C.
  • a board having a laminate film was thereby fabricated.
  • the laminate film was subsequently desmeared.
  • the desmear treatment was carried out by using the dip method in which a series of steps was performed three times, i.e., the board was immersed for 1 minute in a desmearing solution, neutralized, and then washed. This method is generally carried out by board manufacturers, although the treatment times may vary slightly.
  • the board was subjected to electroless copper plating to form a copper-plated layer on the laminate film.
  • the adhesiveness of the copper-plated layer was evaluated by observing the external appearance and employing a simple peeling test using tape. Cases in which the adhesiveness of the copped-plated layer was excellent were marked with “ ⁇ ,” cases in which the adhesiveness was sufficient for practical purposes were marked with “ ⁇ ,” and cases in which adhesiveness was poor were marked with “X.” The evaluation results are shown in TABLES 4 to 6.
  • the laminate film was placed under a pressure of 3 MPa for one hour at a temperature of 160° C., held for two hours without the application of pressure at a temperature of 180° C., and then press molded to fabricate a cured film having a thickness of 50 ⁇ m for tensile testing.
  • the cured film was then cut into strips having a width of 10 mm and a length of 80 mm, and the tensile test was performed.
  • the conditions of the tensile test were set to be a distance of 60 mm between supports that support the cured film and an elastic stress velocity of 5 mm/minute.
  • the tensile test was used to calculate the elongation at break and Young's modulus.
  • a release PET on one side was peeled away from the laminate film (release PET layer/resin layer/release PET layer), and the resin layer was exposed.
  • a conventional three-layer CCL i.e., a conventional three-layer CCL having a three-layer structure composed of “PEN layer/resin layer (ABF-GX (registered trade name) manufactured by Ajinomoto Fine-Techno)/copper foil,” was prepared, and a line-and-space pattern simulating a copper wiring circuit was formed on the surface of the copper foil. The widths of the lines and spaces in the pattern were 100 ⁇ m.
  • the three-layer CCL copper foil surface was superimposed on the resin layer of the laminate film, and a mirror wafer was mounted on the three-layer CCL.
  • Samples were thereby fabricated having the following layers in the following order: release PET layer/resin layer (resin layer of example or comparative example)/copper foil-conventional resin layer-PEN layer-mirror wafer).
  • the samples were subjected to a pressure of 1 MPa for 30 minutes at a temperature of 180° C., and the resin layer of the laminate film and the patterned copper foil were made to bond.
  • the samples were observed using a microscope, the extent to which the patterns in the copper foil were embedded in the resin layer was observed, and the quality of the circuit embedding properties was evaluated.
  • the varnish solution was uniformly coated onto the roughened surface (also referred to a matted surface) of the copper foil using a coating machine so as to obtain a target thickness.
  • the film was thereafter dried for 5 minutes at a temperature of 100° C. to volatilize the solution at a constant rate.
  • the resin surface was covered using a PET film having a release agent, and a single-sided copper-plated prepreg material having a three-layer structure (release PET layer/resin portion/copper foil) was fabricated.
  • the resin layer (also including the remaining solution) in the prepreg material was in an uncured state.
  • Wiring was formed on the copper foil of the single-sided copper-plated prepreg material described above.
  • a plurality of layers of the single-sided copper-plated prepreg material was layered using the build-up method to fabricate a package board.
  • a semiconductor chip was mounted on the package board, a frame-shaped stiffener was provided about the periphery of the semiconductor chip, and a lid (heat sink) was bonded to the semiconductor chip and reinforcing plate.
  • the FCBGA semiconductor device shown in FIG. 1 was fabricated thereby.
  • FCBGA semiconductor devices were prepared for the each of the resin materials, and the semiconductor devices were subjected to a temperature cycle test.
  • the temperature cycle test was started from room temperature, hand the temperature was reduced to ⁇ 40° C. and held at ⁇ 40° C. for 15 minutes. The temperature was then increased to 125° C. and held at 125° C. for 15 minutes to complete a single cycle. The heating and cooling times were constant at 15 minutes. Cases in which cracks were generated in the connection parts (solder bumps) between the semiconductor chip and package board comprising the FCBGA semiconductor device were determined to be defective cases when the temperature cycle test was carried out for 1,000 cycles. The number of cases in which defects occurred (defect generation count) was used as an index of the connection reliability.
  • connection reliability was determined to be more excellent for FCBGA semiconductor devices that have a fewer number of defects.
  • the evaluation results are shown in TABLES 4 to 8.
  • the entries in the row titled “Connection reliability” in TABLES 4 to 8 were obtained by carrying out the temperature cycle test described above, and the entries indicate the number of semiconductor devices among the thirty-eight FCBGA semiconductor devices that produced defects in each sample.
  • FIG. 3 is a diagram showing a schematic of the evaluation board.
  • FIG. 4 is a top view showing the specifics of the evaluation board.
  • FIG. 5 is a partial enlarged cross-sectional view of the evaluation board. Also shown in FIG. 5 is the flat shape of the wiring 45 .
  • the board for evaluation had two pectinate wirings 41 disposed so as to be inter-nested, as shown in FIG. 3 . Specifically, the two pectinate wirings 41 were disposed so that the teeth of one pectinate wiring 41 were positioned between the teeth of the other pectinate wiring 41 , and the pectinate wirings did not make contact with each other. The pectinate wirings were connected to square electrodes 42 .
  • a FR-4 board 44 as a core was disposed on the evaluation board 43 , as shown in FIG. 4 .
  • the external dimensions of the board 44 were 24.4 mm in the lengthwise direction, 8.0 mm in the crosswise direction, and a thickness of 0.8 mm.
  • Two electrodes 42 were disposed on the surface of the board 44 at a distance from each other in the lengthwise direction of the board 44 . As viewed from above, the length of one side of the electrode 42 was 5.2 mm.
  • the two pectinate wirings 41 were disposed so as to be interested in the area between the electrodes 42 .
  • Wiring 45 having 10 wires as the teeth was disposed in each of the pectinate wirings 41 . The length of each wiring 45 was 8.7 mm.
  • a Cu pattern 47 composed of Cu was intermittently disposed on the surface of the board 44 along the direction in which the wiring 45 extended, as shown in FIG. 5 .
  • a build-up resin layer 48 having a thickness of 50 ⁇ m was disposed so as to cover the Cu pattern 47 .
  • the build-up resin layer 48 was formed from any of the resins shown in TABLES 1 to 3.
  • a Cu pattern 49 composed of CI was intermittently disposed on the surface of the build-up resin layer 48 along the direction in which the wiring 45 extended.
  • the Cu patterns 47 and 49 as viewed from above, had two 150- ⁇ m diameter circular portions and a single rectangular portion connecting the circular portions. The thickness of the rectangular portion was 18 ⁇ m.
  • the rectangular portions of the Cu pattern 49 were positioned directly above the areas between the Cu patterns 47 , and the circular portions of the Cu patterns 49 were positioned directly above the circular portions of the Cu pattern 47 .
  • One via 46 was disposed between each of the circular portions of the Cu pattern 47 and the circular portions of the Cu pattern 49 in the build-up resin layer 48 , and the vias 46 connected the Cu pattern 47 and Cu pattern 49 to each other.
  • the shape of the vias 46 was a conic trapezoid, the diameter of the upper portion was 100 ⁇ m, and the diameter of the lower portion was 75 ⁇ m.
  • the distance between two vias connected to the same Cu pattern 47 and Cu pattern 49 was 300 ⁇ m, as described above.
  • a solder resist 50 having a thickness of 35 ⁇ m was disposed on the build-up resin layer 48 so as to cover the Cu pattern 49 .
  • a Cu pattern 51 having a thickness of 18 ⁇ m was disposed on the entire surface of the reverse surface of the board 44 .
  • the build-up resin layer 48 and solder resist 50 are not depicted in FIG. 4 .
  • a HAST Highly Accelerated temperature humidity Stress Test was performed using the evaluation board 43 fabricated in the manner described above.
  • the test conditions were a temperature of 130° C., a humidity of 85 RH %, and a voltage of 5 V applied between the electrodes.
  • the time required for the resistance between the electrodes 42 to decrease to 1 ⁇ 10 9 ⁇ or less was measured and used as an index of the insulation reliability. The longer this time was measured to be, the better the insulation reliability was.
  • the test was carried out for a maximum of 500 hours.
  • the test results are shown in TABLES 4 to 8. The entry “over 500 hours” in TABLES 4 to 8 indicates that the resistance between the electrodes did not decrease to 1 ⁇ 10 9 ⁇ or less, even when the test was continued for 500 hours.
  • Nos. 2 to 5, No. 7, No. 9, No. 14 to 20, No. 22 and No. 23 shown in TABLES 4 to 8 are examples of the present invention.
  • a crosslinked styrene-butadiene rubber (E1) having a double bond and a polar group had been added as the additive (E) used with the insulation material, and the content of the Reactive elastomer (A) is 15 to 80 mass %, and the adhesiveness of the copper-plating layer formed using electroless plating on the laminate film was therefore high. In other words, the electroless copper plating properties were good.
  • Nos. 1, 6, 8, 10 to 13, 21 and 24 shown in TABLES 4 to 6 and 8 are comparative examples. In these comparative examples Nos.
  • the content of the Reactive elastomer (A) is over 80 mass %, the hardening of the insulation material is insufficient and therefore the chemical resistance of the insulation material was reduced and also electroless plating property was degraded.
  • the toughness, circuit embedding properties, connection reliability, and insulation reliability was good for both the examples and comparative examples described above except the Nos. 21 and 24.
  • the present invention can be advantageously used in FCBGA, WLCP, and other semiconductor devices in which a semiconductor chip is mounted on a wiring board by way of solder bumps.

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Abstract

In a semiconductor device, the topmost wiring layer of the package board is formed from an insulation material in which the elongation at break is 20% or higher and Young's modulus is 1 GPa or less when the temperature is 10 to 30° C. This insulation material contains a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent; an epoxy resin; an epoxy resin curing agent; and a crosslinked styrene-butadiene rubber having a double bond and a hydroxyl group, a carboxylic group, or another polar group. It is therefore possible to provide a semiconductor device that has a wiring board in which the connection reliability in relation to temperature cycles is high and the adhesiveness between the insulation layer and the electroless copper plating layer is also high.

Description

This application claims priority from PCT Application No. PCT/JP2006/312161 filed Jun. 16, 2006, and from Japanese Patent Application Nos. 2005-218220 filed Jul. 28, 2005, 2006-203881, filed Jul. 26, 2006, which applications are incorporated herein by reference.
TECHNICAL FIELD
The present invention relates to an insulation material that forms a wiring board, to a wiring board that uses the insulation material, and to a semiconductor device provided with the wiring board.
BACKGROUND ART
A method has been developed in recent years whereby a plurality of solder balls is arrayed in the form of a matrix on the surface of a wiring board, and a semiconductor chip is mounted on the solder balls in order to obtain a smaller semiconductor device. Examples of such a semiconductor device are FCBGA (Flip Chip Ball Grid Array) and WLCSP (Wafer Level Chip Size Package). Also known is a multilayer wiring board in which a plurality of wiring-embedded resin layers is layered, a build-up wiring board with a so-called core member, and a package board includes MLTS (Multi Layer Thin Substrate) (brand name) structures.
Nevertheless, conventional methods have the problems described below. In other words, silicon, which is the material of the semiconductor chip, and the resin that forms the wiring board have mutually different coefficients of thermal expansion. For this reason, warping is generated in the semiconductor device, and force is applied to the solder balls because the shrinkage of the semiconductor chip and the shrinkage of the wiring board are mutually different when the semiconductor device is cooled to room temperature, even when the semiconductor chip is mounted on the wiring board so that force is not applied during mounting. Also, the solder balls may experience fatigue fracturing and become disconnected when the semiconductor device repeatedly undergoes heating and cooling cycles due to heat generated by the operation of the semiconductor chip and changes in the outside temperature.
Conventionally, attempts have been made to avoid this problem and improve the connection reliability of a semiconductor device by forming the wiring board from a resin that is as rigid as possible. This is intended to minimize warping of the semiconductor device and deformations of the wiring board by increasing the rigidity of the wiring board. In Patent Document 1, for example, a method is disclosed that uses an insulation material that has a modulus of elasticity of 10 GPa or higher as the material of the wiring board.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2002-198462
DISCLOSURE OF THE INVENTION The Problem to be Solved by the Invention
However, the above-described prior art has the problems described below. In other words, the connection reliability of a semiconductor device in relation to temperature cycles is still insufficient even when the wiring board is formed from a material that has a modulus of elasticity of 10 GPa or higher, as described in Patent Document 1. There is a problem in that the base material, which is the main component of the insulation material that forms the wiring board as described in Patent Document 1, generally has low adhesiveness with the copper wiring when electroless copper plating is carried out on the surface to form the copper wiring. In view of this fact, an adhesive for improving the adhesiveness between the base material and the copper wiring is ordinarily added to the base material. However, depending on the type of base material, such adhesives have variable effect, and the effect of improving the plating adhesiveness cannot be obtained using conventional additives in combination with some base materials.
The present invention was contrived in view of the foregoing, and an object is to provide a wiring board that has high connection reliability in relation to temperature and has good adhesiveness between the insulation layer and the electroless copper plating, to provide an insulation material that forms the wiring board, and to provide a semiconductor device provided with the wiring board.
Means for Solving the Problem
The insulation material of the present invention comprises a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent; an epoxy resin; an epoxy resin curing agent; and a crosslinked rubber having a double bond and a polar group in the structure thereof, wherein Young's modulus in a temperature range of 10 to 30° C. is 1 GPa or less.
The polar group may be a hydroxyl group or a carboxyl group, and the crosslinked rubber is crosslinked styrene-butadiene rubber.
The value of (E×100)/(A+B+C+E) is preferably 3 to 25%, and is more preferably 5 to 20%, wherein A mass % is the content of the reactive elastomer, B mass % is the content of the epoxy resin, C mass % is the content of the epoxy resin curing agent, and E mass % is the content of the crosslinked rubber.
The reactive elastomer is preferably a polyamide elastomer that does not contain a cyanate group in the structure of the elastomer, or is a flexible epoxy resin that contains an unsaturated double bond and an epoxy group in the structure of the elastomer.
The value of (A×100)/(A+B+C+E) is preferably 15 to 80 mass %, and more preferably to 50 to 75 mass %.
The value of (B×100)/(A+B+C+E) is preferably 20% or less. The elongation at break is thereby improved.
The wiring board of the present invention uses the above-described insulation material.
In the present invention, the wiring board can follow the thermal expansion of external elements when the wiring board becomes heated or cooled after semiconductor chips or other external elements have been mounted to form a semiconductor device on the wiring board, by forming the wiring board from an insulation material that has a relatively low Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. Warping of the semiconductor device can thereby be reduced, and the force applied to the connection portion between the wiring board and the external elements can be reduced. Accordingly, the connection reliability in relation to temperature cycles of the semiconductor device can be improved. The adhesiveness between the insulation layer and the copper plating layer can be improved when copper plating is formed by electroless plating on an insulation layer composed of the insulation material because the insulation material contains a crosslinked rubber having a double bond and a polar group in the structure of the insulation material.
The semiconductor device of the present invention is provided with the above-described wiring board.
Effect of the Invention
In accordance with the present invention, the wiring board can follow the thermal expansion of external elements when external elements are mounted on the wiring board, by forming the wiring board from an insulation material that has a Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. Therefore, warping of the wiring board can be reduced, fracturing of the connection portion can be prevented, and connection reliability in relation to temperature cycles can be improved. The adhesiveness between the electroless copper plating layer and the insulation layer composed of the insulation material can be improved because the insulation material contains a crosslinked rubber having a double bond and a polar group in the structure of the insulation material.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view showing the semiconductor device of the embodiments of the present invention;
FIG. 2 is a schematic view showing the characteristics of the semiconductor device;
FIG. 3 is a diagram showing a schematic of the evaluation board fabricated in the test example of the present invention;
FIG. 4 is a top view showing the specifics of the evaluation board; and
FIG. 5 is a partial enlarged cross-sectional view of the evaluation board.
 KEY
    • 1: Semiconductor device
    • 2: Package board
    • 3: Wiring
    • 4: Via
    • 5: Mounting pad
    • 6: Ball pad
    • 7: Solder bump
    • 8: BGA ball
    • 9: Semiconductor chip
    • 10: Underfill resin
    • 11: Stiffener
    • 12: Lid
    • 13, 14, 15: Adhesive layers
    • 16: Wiring layers
    • 41: Pectinate wiring
    • 42: Electrode
    • 43: Evaluation board
    • 44: FR-4 board
    • 45: Wiring
    • 46: Via
    • 47, 49, 51: Cu patterns
    • 48: Build-up resin layer
    • 50: Solder resist
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention are described in detail below with reference to the attached diagrams. FIG. 1 is a cross-sectional view showing the semiconductor device of the embodiments of the present invention, and FIG. 2 is a schematic view showing the characteristics of the semiconductor device. The semiconductor device 1 according to the present embodiment is an FCBGA semiconductor device, as shown in FIG. 1. A package board 2 is disposed in the semiconductor device 1. The package board 2 formed by layering a plurality of wiring layers, and wiring 3 composed of, e.g., copper, and vias 4 connected to the wiring 3 are formed in the wiring layers. A plurality of mounting pads 5 is formed on a wiring layer 16 (see FIG. 2), which is the topmost layer of the package board 2. The wiring 3, vias 4, and mounting pads 5 may also be generically referred to as “wiring.” A plurality of ball pads 6 is formed on the lower surface of the package board 2. The mounting pads 5 and ball pads 6 are each arrayed in the form of a matrix as viewed from directly above (hereinafter referred to as “plan view”) on the upper surface of the package board 2.
In a plan view, the ball pads 6 are larger than the mounting pads 5, and the array pitch of the ball pads 6 is greater than the array pitch of the mounting pads 5. The mounting pads 5 are connected to the ball pads 6 by way of the wiring 3 and vias 4. Solder bumps 7 are connected to the mounting pads 5, and BGA balls 8 are connected to the ball pads 6. The BGA balls 8 are larger than the solder bumps 7.
A semiconductor chip 9 is mounted on the package board 2. The semiconductor chip 9 is composed of, e.g., multilayered wiring layers (not shown) disposed on a silicon substrate (not shown), and an integrated circuit is formed on the surface of the silicon substrate and the multilayered wiring layer. The surface of the multilayered wiring layer in the semiconductor chip 9 has I/O pads (not shown) disposed on the surface of the side that faces the package board 2, and the I/O pads are connected to the solder bumps 7. The I/O pads of the semiconductor chip 9 are thereby connected to the mounting pads 5 by way of the solder bumps 7, and are connected to the BGA balls 8 by way of the wiring 3, vias 4, and ball pads 6. An underfill resin 10 is filled about the periphery of the solder bumps 7 between the package board 2 and semiconductor chip 9. The semiconductor chip 9 is thereby connected and fixed to the package board 2.
A stiffener 11 composed of stainless steel or copper is disposed in the area surrounding the semiconductor chip 9 on the package board 2. The stiffener 11 is bonded to the package board 2 using an adhesive layer 15. The stiffener 11 is frame-shaped in a plan view, and the semiconductor chip 9 is accommodated in the open area of the frame shape. The upper surface of the stiffener 11 is substantially in the same plane as the semiconductor chip 9.
A lid 12 composed of, e.g., ceramic is disposed on the semiconductor chip 9 and stiffener 11. The lid 12 is bonded to the semiconductor chip 9 using an adhesive layer 13 and to the stiffener 11 using an adhesive layer 14. The shape of the lid 12 is a shape that substantially overlaps the package board 2 in a plan view. The lid 12 functions as a heat sink for the semiconductor chip 9. The semiconductor device 1 is mounted on a motherboard (not shown) or the like by way of BGA balls 8.
The wiring layer 16 disposed on the topmost wiring layer of the package board 2, i.e., on the surface that faces the semiconductor chip 9 and on which the mounting pads 5 are formed (see FIG. 2), is formed from an insulation material that has a Young's modulus of 1 GPa or less when the temperature is between 10 and 30° C. (hereinafter referred to as “room temperature”) and that has an elongation at break of 20% or higher. This insulation material contains a reactive elastomer (A) that can react with epoxy resin or an epoxy resin curing agent; an epoxy resin (B); an epoxy resin curing agent (C); and a crosslinked rubber as an additive (E) having a double bond and a polar group in the structure of the material.
The ratio of crosslinked rubber in the resin component, i.e., the value of (E×100)/(A+B+C+E), is 3 to 25 mass %, and may be, e.g., 5 to 20 mass %, wherein A mass % is the content of the reactive elastomer, B mass % is the content of the epoxy resin, C mass % is the content of the epoxy resin curing agent, and E mass % is the content of the crosslinked rubber. The ratio of the reactive elastomer (A) in the resin component, i.e., the value of (A×100)/(A+B+C+E), is 15 to 80 mass %, and is preferably 50 to 75 mass %. In the case, the ratio of the reactive elastomer (A), i.e., the value of (A×100)/(A+B+C+E) is 50 to 75 mass %, an insulation material of high elongation and low elasticity can be obtained. The ratio of the epoxy resin (B) in the resin component, i.e., the value of (B×100)/(A+B+C+E), is 20% or less. The reasons for the above-described numerical limits are described below.
Value of (E×100)/(A+B+C+E): 3 to 25 mass %
When the ratio of crosslinked rubber in the resin component of the insulation material, i.e., the value of (E×100)/(A+B+C+E), is less than 3%, the bonding characteristics of the electroless copper plating are sometimes insufficient. When the value exceeds 25%, the elongation of the insulation material may be reduced, or the physical properties of the insulation material may be otherwise insufficient. Therefore, the value of (E×100)/(A+B+C+E) is preferably 3 to 25%, and more preferably 5 to 20%.
Value of (A×100)/(A+B+C+E): 15 to 80 mass %
When the ratio of the reactive elastomer (A) in the resin component of the insulation material, i.e., the value of (A×100)/(A+B+C+E), is less than 15%, the reactive elastomer that assures the toughness of the insulation material is insufficient, and sufficient elongation at break cannot be obtained. If the value exceeds 80%, the curability of the insulation material becomes insufficient, and chemical resistance of the insulation material may be reduced and also electroless plating property may be degraded. Also, if the value exceeds 80%, the semi-hardened insulation material of the present embodiment can not be melted with sufficient fluidization. Therefore, the insulation material can not be added to the rough surface of the copper foil with the sufficient adhesiveness and the reliability of the connection may be degraded. Therefore, the value of (A×100)/(A+B+C+E) is preferably 15 to 80 mass %.
Value of (B×100)/(A+B+C+E): 20 mass % or less
When the ratio of the epoxy resin (B) in the resin component, i.e., the value of (B×100)/(A+B+C+E) exceeds 20 mass %, elongation at break may be insufficient. Therefore, the value of (B×100)/(A+B+C+E) is preferably 20 mass % or less.
The crosslinked rubber (E) having a double bond and a polar group described above is a crosslinked styrene-butadiene rubber having a carboxylic group or a hydroxyl group as a polar group, and en example is XSK-500 (registered trade name) manufactured by JSR. In this case, the double bond is contained in the butadiene moiety.
The reactive elastomer (A) is preferably a polyamide elastomer that does not contain a cyanate group in the structure of the elastomer. The reactive elastomer (A) is a polyamide-polybutadiene copolymer that contains a phenolic hydroxyl group. The phenolic hydroxyl group-containing polyamide-polybutadiene copolymer (hereinafter also referred to simply as “copolymer”) is obtained by reacting a phenolic hydroxyl group-containing dicarboxylic acid expressed by chemical formula 1 described below, a dicarboxylic acid that does not contain a phenolic hydroxyl group expressed by chemical formula 2 described below, a diamine expressed by the chemical formula 3 described below, and a polybutadiene that has a carboxylic group at the two ends expressed by the chemical formula 4 described below or a poly butadiene that has an amino group at the two ends expressed by the chemical formula 5 described below. The phenolic hydroxyl group-containing polyamide-polybutadiene copolymer is expressed by the general chemical formulas 6 or 7 described below.
HOOC—R1—COOH  [Chemical Formula 1]
The term R1 in chemical formulas 1, 6, and 7 is a bivalent aromatic compound with a carbon number of 6 to 12 having a phenolic hydroxyl group. Examples of the dicarboxylic acid having phenolic hydroxyl group expressed in the above-noted chemical formula 1 include 5-hydroxyisophthalic acid, 4-hydroxyisophthalic acid, 2-hydroxyphthalic acid, 3-hydroxyhthalic acid, and 2-hydroxyterephthalic acid.
HOOC—R2—COOH  [Chemical formula 2]
The term R2 in chemical formulas 2, 6, and 7 is a bivalent aromatic compound having a carbon number of 6 to 12 that does not contain a phenolic hydroxyl group or a bivalent aliphatic compound having a carbon number of 1 to 10. Examples of a dicarboxylic acid that does not contain a phenolic hydroxyl group expressed the above-noted chemical formula 2 include phthalic acid, isophthalic acid, terephthalic acid, dicarboxylic naphthalene, succinic acid, fumaric acid, glutaric acid, adipic acid, 1,3-cyclohexanedicarboxylic acid, 4,4′-diphenyl dicarboxylic acid, and 3,3′-methylenedibenzoic acid.
H2N—R3—NH2  [Chemical formula 3]
The term R3 in chemical formulas 3, 6, and 7 is a bivalent aromatic compound having a carbon number of 6 to 12 or a bivalent aliphatic compound having a carbon number of 1 to 10. Examples of diamines that contain a phenolic hydroxyl group among the diamines expressed by chemical formula 3 noted above include 3,3′-diamine-4,4′-dihydroxyphenylmethane, 2,2′-bis(3-amino-4-hydroxyphenyl)hexafluoropropane, 2,2′-bis(3-amino-4-hydroxyphenyl)difluoromethane, 3,4′-diamino-1,5′-benzendiol, 3,3′-dihydroxy-4,4′-diaminobisphenol, 3,3′-diamino-4,4′-dihydroxybisphenol, 2,2′-bis(3-amino-4-hydroxyphenyl)ketone, 2,2′-bis(3-amino-4-hydroxyphenyl)sulfide, 2,2′-bis(3-amino-4-hydroxyphenyl)ether, 2,2′-bis(3-amino-4-hydroxyphenyl)sulfone, 2,2′-bis(3-amino-4-hydroxyphenyl)propane, 2,2′-bis(3-amino-4-aminophenyl)propane, and 2,2′-bis(3-amino-4-aminophenyl)methane; and diamines that do not have a phenolic hydroxyl group include 3,3′-diaminodiphenyl ether, 3,4′-diaminodiphenyl ether, 4,4′-diaminodiphenyl ether, diamino naphthalene, piperazine, hexamethylenediamine, tetramethylenediamine, m-xylenediamine, 4,4′-diaminodiphenyl methane, 4,4′-diaminobenzophenone, 2,2′-bis(4-aminophenyl)propane, 3,3′-diaminodiphenyl sulfone, and 3,3′-diaminodiphenyl. The diamine is not limited, but particularly preferred is 3,4′-diaminodiphenyl ether.
Figure US07981963-20110719-C00001
In chemical formulas 4 and 5 above, and in chemical formulas 6 and 7 below, x and y are average degrees of polymerization and are integers from 3 to 7.
Figure US07981963-20110719-C00002
In chemical formulas 5 and 7 above, and in chemical formulas 8 and 9 below, z, l (lower case L), m, and n are average degrees of polymerization, wherein z is an integer from 5 to 15, n=l+m, n is an integer from 2 to 200, and l (lower case L) and m satisfy the relationship m/(l+m)≧0.04.
The copolymer particularly preferred among the copolymers expressed by the chemical formulas 6 and 7 is a copolymer expressed by the general chemical formulas 8 and 9 below.
Figure US07981963-20110719-C00003
When the weight-average molecular weight (Mw) of the copolymer is 100,000 or less, sufficient fluidity can be obtained in a temperature range of 160 to 180° C. In particular, good fluidity can be obtained in a temperature range of 100 to 160° C. when the weight-average molecular weight (Mw) is 20,000 or less. Therefore, the weight-average molecular weight (Mw) of the copolymer is preferably 100,000 or less, and more preferably 20,000 or less.
A flexible epoxy resin that contains an unsaturated double bond and an epoxy group in the structure of the resin may be used as the reactive elastomer (A) in place of the polyamide elastomer that does not contain a cyanate group in the above-described structure.
An example of the resin (D) in which the distance between the functional groups is greater than that of the phenol novolac resin contained in the epoxy resin curing agent (C) is expressed by chemical formula 10 below.
Figure US07981963-20110719-C00004
The term R4 in chemical formula 10 is hydrogen or a univalent substituent group having a carbon number of 1 to 3. In the formula, a1 is an integer from 1 to 4, a1′ is an integer from 1 to 3, X is the compound X1 expressed by the chemical formula 12 below or is the compound X2 expressed by the chemical formula 13 below, b is an integer from 1 to 10, and c and d are both 1.
The resin (D) in which the distance between the functional groups is greater than that of the phenol novolac resin expressed by the chemical formula 10 has a phenolic hydroxyl group as a functional group, e.g., is ethylene oxide, and an example of the resin is an ethylene oxide compound in which the distance between the phenolic hydroxyl groups in the molecular structure is greater than the distance between the phenolic hydroxyl groups in the phenol novolac resin. An example of the ethylene oxide compound is expressed by chemical formula 11 below.
Figure US07981963-20110719-C00005
The term R4 in chemical formula 11 is hydrogen or a univalent substituent group having a carbon number of 1 to 3. In the formula, a2 is an integer from 1 to 4, a2′ is an integer from 1 to 3, X′ is the compound X1 expressed by the chemical formula 12 below or is the compound X2 expressed by the chemical formula 13 below, b′ is an integer from 1 to 10, and c′ and d′ are both 1.
Figure US07981963-20110719-C00006
The term R5 in chemical formula 12 is hydrogen or a univalent substituent group having a carbon number of 1 to 3. In the formula, e is an integer from 1 to 4, and f is an integer from 0 to 9.
Figure US07981963-20110719-C00007
The term R6 in chemical formula 13 is hydrogen or a univalent substituent group having a carbon number of 1 to 3. In the formula, g is an integer from 1 to 4, and h is an integer from 0 to 9.
The resin expressed by the chemical formulas 10 and 11 above is configured such that the distance between the functional groups is greater than that of phenol novolac resin expressed by the chemical formula 14 below.
Figure US07981963-20110719-C00008
In the present embodiment, the epoxy resin (B) is not particularly limited, but is preferably an epoxy resin in which the distance between the functional groups is greater than that of phenol novolac epoxy resin. The reason for this is that such an epoxy resin can efficiently form an IPN structure, and as a result, the elongation at break of the insulation material according to the present embodiment can be improved. Examples of such an epoxy resin in which the distance between the functional groups is greater than that of phenol novolac epoxy resin include phenol biphenylene aralkyl epoxy resin, phenol xylene aralkyl epoxy resin, phenol diphenyl ether aralkyl epoxy resin, bifunctional biphenyl epoxy resin, anthracene-containing novolac epoxy resin, fluorene-containing novolac epoxy resin, bisphenol fluorene-containing novolac epoxy resin, phenol biphenylene triazine epoxy resin, and phenol xylene triazine epoxy resin. Additional examples are phenoxy resins, which have an epoxy group at both ends and are bisphenol A, bisphenol F, bisphenol S, or bisphenol backbone-containing resins. The phenoxy resin has a weight-average molecular weight of about 20,000 to 100,000 in terms of polystyrene. Any of these epoxy resins may be used alone or in a plural mixture as the epoxy resin (B).
Among the epoxy resins (B) contained in the insulation material of the present embodiment, epoxy resins other than epoxy resins having a long distance between the functional groups as described above are not particularly limited. Examples include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol S epoxy resin, naphthalene diol epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin, bisphenol F-containing novolac epoxy resin, bisphenol A-containing novolac epoxy resin, phenol triazine epoxy resin, cresol triazine epoxy resin, tetraphenylol ethane epoxy resin, trisphenylol ethane epoxy resin, polyphenol epoxy resin, aliphatic epoxy resin, aromatic ester epoxy resin, cycloaliphatic ester epoxy resin, and ether ester epoxy resin. It is also possible use glycidyls of diaminodiphenyl methane, diethylene triamine, diamino diphenyl sulfone, and other amine compounds. These epoxy resins may be used alone or may be used in a plural mixture.
Among the epoxy resin curing agents (C) in the insulation material of the present embodiment, components other than the resin (D) in which the distance between the functional groups is greater than that of the phenol novolac resin described above are not particularly limited. Examples of such components include bisphenol A phenolic resin, bisphenol F phenolic resin, bisphenol S phenolic resin, dihydroxy ether of a biphenyl isomer, naphthalene diol resin, phenol novolac resin, cresol novolac resin, phenol diphenyl ether aralkyl resin, naphthalene-containing novolac resin, anthracene-containing novolac resin, fluorene-containing novolac resin, bisphenol fluorene-containing novolac resin, bisphenol F-containing novolac phenolic resin, bisphenol A-containing novolac phenolic resin, phenol biphenylene triazine resin, phenol xylene triazine resin, phenol triazine resin, cresol novolac triazine resin, tetraphenylol ethane resin, trisphenylol ethane resin, polyphenol resin, aromatic ester phenolic resin, cycloaliphatic ester phenolic resin, and ether ester phenolic resin.
Other than the resins described above, diamino diphenyl ethane, diethylene triamine, diaminodiphenyl sulfone, and other amine-based compounds may be contained as components of the epoxy resin curing agent (C). Phenoxy resins that are bisphenol A, bisphenol F, bisphenol S, or bisphenol backbone-containing resins, and have a hydroxyl group at one or both ends may also be used. The phenoxy resin has a weight-average molecular weight of about, e.g., 20,000 to 100,000 in terms of polystyrene. Any of these epoxy resins may be used alone or in a plural mixture as the epoxy resin curing agent (C).
The insulation material of the present embodiment may contain an inorganic filler. When an inorganic filler is used, the mass ratio of the inorganic filler of the total weight of the reactive elastomer (A), the epoxy resin (B), the epoxy resin curing agent (C), and the inorganic filler in the present invention is preferably 50 mass % or less. When the mass ratio of the inorganic filler exceeds 50 mass %, elongation at break may be reduced, Young's modulus may be increased, and the stress reducing characteristics may be insufficient.
Known fillers can be used as the inorganic filler, and examples include fused silica, crystal silica, alumina, zircon, calcium silicate, calcium carbonate, silicon carbide, silicon nitride, boron nitride, beryllia, talcum (talc), isinglass (mica), titanium oxide, zirconia, and other powders, or beads composed of these materials formed into spherical shapes; calcium titanate, silicon carbide, silicon nitride, boron nitride, alumina, and other monocrystalline fibers; aluminum hydroxide, magnesium hydroxide, zinc borate, and other metal hydrates, the above-noted metal hydrates that have been surface treated using epoxy resin, phenolic resin, and various other organic substances; and magnesium hydroxide and various other hydroxides in which the metal has been formed into a solid solution to improve acid resistance. These fillers may be used alone, or in a combination of two or more.
The insulation material of the present embodiment may contain a curing acceleration catalyst. A catalyst that is generally used to cure epoxy resins and curing agents may be used as the curing acceleration catalyst, but this does not impose any limitation. Examples include imidazoles, diazabicycloalkenes, diazabicycloalkene derivatives, and tertiary amines. These curing acceleration catalysts may be used alone or in a combination of two or more.
Other additives may be used as required in the insulation material in the present embodiment, including silicon rubber, silicone powder, acrylonitrile-butadiene rubber (NBR), indene, and other flexibility-imparting agents. Also, organosilane compounds, organic titanate compounds, and organic aluminate compounds, and other coupling agents may be appropriately added. In particular, organosilanes as silane coupling agents, i.e., alkoxysilanes that have reactive functional groups, are effective for improving solder heat resistance and adhesiveness of the insulation material according to the present embodiment. Specific examples of alkoxysilanes include γ-aminopropyltrimethoxysilane, N-phenyl-γ-aminopropyltriethoxysilane, and other aminosilane compounds; γ-glycidoxypropyltrimethoxysilane, γ-glycidoxypropylmethyldiethoxysilane, and other epoxysilane compounds; γ-mercaptopropyltrimethoxysilane, and other mercaptosilane compounds; and γ-ureidopropyltriethoxysilane and other ureidosilane compounds.
Also, components used in rust-preventive agents capable of bonding with copper surfaces, i.e., triazole compounds, mercapto compounds other than mercaptosilane compounds, and imidazole copper complexes, may be added as adhesiveness improvers between the insulation material and the copper foil surface to the insulation material of the present embodiment. Examples of triazol compounds include 1,2,3-benzotriazole and tolyltriazole. Examples of mercapto compounds include 2,4,6-trimercapto-s-triazine, 2-di-n-butylamino-4,6-dimercapto-s-triazine, and 2-anilino-4,6-dimercapto-s-triazine. An example of an imidazole copper complex is 2-methylimidazole copper (2) complex. These components may be used alone or in a combination of two or more components.
Flame retardants may be added as required to the insulation material of the present embodiment. Examples of such flame retardants include halogen flame retardants, nitrogen flame retardants, phosphorus flame retardants, and inorganic flame retardants. Examples of halogen flame retardants include brominated-bisphenol A resins and epoxidated brominated-bisphenol A resins. Examples of an additive compounds that are nitrogen-based flame retardants include melamine and isocyanuric acid compounds. Examples of reactive compounds that are nitrogen-based flame retardants include phenol triazine curing agents and epoxy resins. Examples of phosphorus flame retardants include red phosphorus, phosphate compounds, and organic phosphorus compounds. Examples of inorganic flame retardants include the above-noted metal hydrates, zinc molybdate, zinc stannate, and compounds in which zinc molybdate or zinc stannate covers the surface of talc or silica. Also, when halogen flame retardants are used in combination with antimony oxide, very good flame resistance can be achieved.
The insulation material of the present embodiment may contain known substances other than those listed above as long as the reliability of the semiconductor device that uses the insulation material is not reduced. Examples of other substances that may be added include pigments, antioxidants, and organic solvents.
The semiconductor device 1 according to the present embodiment is wherein a semiconductor chip 9 is mounted on the topmost layer of a package board 2 by way of a plurality of solder bumps 7, wherein a wiring layer 16 composed of a resin that has a Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C. is disposed on the topmost layer of the package board, as shown in FIG. 2. Constituent elements other than those described above are not shown in FIG. 2.
Next, a method for manufacturing the semiconductor device of the present embodiment is described with reference to FIG. 1. First, two support boards (not shown) composed of copper or another metal material are prepared, and the two support boards are laminated together. Next, an Ni (nickel) layer, an Au (gold) layer, an Ni layer, and a Cu (copper) layer are plated in the stated order to form a multilayered film on the two sides of the laminated support boards. The multilayered film is patterned by leaving only the portions in which the mounting pads 5 are to be formed, and removing the remainder. A semi-cured resin film is layered so as to embed the patterned multilayered film. The resin film is formed from an insulation material in which the elongation at break is 20% or higher and the Young's modulus in a temperature range of 10 to 30° C. is 1 GPa or less. The film is then heated and cured to form an insulation layer. Next, holes are formed in the insulation layer using laser or the like so as to reach the multilayered film. The interior of the holes is covered with a metal plating film to form vias 4. A first wiring layer in which a multilayered film and vias 5 are embedded in the insulation layer is thereby formed on the two surfaces of the two support boards.
Next, a wiring layer 3 is formed on the first wiring layer so as to be connected to the vias 4, and a semi-cured resin film is layered and heat cured so as to embed the wiring layer 3 to form an insulation layer. Vias 4 are formed so as to be connected to the wiring layer 3 in the insulation layer, and a second wiring layer in which the wiring layer 3 and the vias 4 in the insulation layer are embedded is formed. Next, the third layer and other wiring layers are sequentially formed using the same process as the second wiring layer. After all the wiring layers have been formed, the ultimately formed wiring layer is chemically plated or etched to form ball pads 6. A plurality of wiring layers is thereby layered on the two surfaces of the laminated support boards to form a package board 2.
Next, the two support boards are separated from each other. An alkaline solution is used to remove the support boards. An acidic solution is then used to remove the Ni layer of the multilayered film. The mounting pads 5 are thereby formed in which an Au layer, an Ni layer, and a Cu layer are formed in the stated order. A stiffener 11 is thereafter bonded to the surface of the side on which the mounting pads 5 are formed, by way of an adhesive layer 15 in the package board 2 to fabricate a “board having a stiffener.”
Apart from the process for manufacturing the “board having a stiffener,” solder bumps 7 are joined to the I/O pads (not shown) of the semiconductor chip 9 to fabricate a “chip having solder bumps.” Next, the “chip having solder bumps” is connected to the “board having a stiffener” so that the solder bumps 7 of the “chip having solder bumps” are connected to the mounting pads 5 of the “board having a stiffener.” An underfill resin 10 is subsequently filled, heated, and cured so as to embed the solder bumps 7 between the semiconductor chip 9 and the package board 2 and the vicinity thereof.
Next, a lid 12 is bonded by way of adhesives 13 and 14 to the upper surface of the stiffener 11 and semiconductor chip 9, i.e., the surface of the side opposite from the surface on which the package board 2 is bonded. BGA balls 8 are then bonded to the ball pads 6 formed on the lower surface of the package board 2 to thereby manufacture a semiconductor device 1.
When the supporting boards are removed, only the center portions are removed and the peripheral portions are left behind in the form of a frame. The remaining portion of the support boards may be used as the stiffener 11. The removal of the support boards and the formation of the stiffener 11 can thereby be performed simultaneously, and the adhesive layer 15 becomes unnecessary.
The operation of the embodiment configured in the manner described above is described next. The semiconductor device 1 is mounted on a motherboard (not shown) by way of BGA balls 8, as shown in FIGS. 1 and 2. The motherboard is, e.g., an FR-4 board or an FR-5 board, and is a glass epoxy board in which a glass cloth has been immersed in epoxy resin, for example.
A power source potential and signals are inputted to the semiconductor device 1 by way of the motherboard. In this case, the power source potential and signals are inputted to the semiconductor chip 9 by way of an electric current pathway composed of the following the sequence: BGA balls 8, ball pads 6, vias 4 and wiring layer 3, mounting pads 5, and solder bumps 7. The semiconductor chip 9 stores signals, performs calculations, and otherwise processes information on the basis of the inputted power source electric potential and signals, and outputs the results. The outputted signals are outputted to the motherboard by way of an electric current pathway composed of the following sequence: solder bumps 7, mounting pads 5, vias 4 and wiring layer 3, ball pads 6, and BGA balls 8; and is then outputted to the exterior by way of the motherboard.
At this point, operation of the semiconductor chip 9 causes heat to evolve. Some of the heat is absorbed by the lid 12, but the heat capacitance of the lid 12 is limited. Therefore, some of the heat is conducted to the package board 2 by way of the solder bumps 7, and the remainder of the heat accumulates in the semiconductor chip 9. As a result, the temperature of the semiconductor chip 9, solder bumps 7, and package board 2 unavoidably increases. Therefore, the semiconductor chip 9 and package board 2 thermally expand. Since the coefficient of thermal expansion of the silicon that forms the substrate of the semiconductor chip 9, and the coefficient of thermal expansion of the insulation material that primarily forms the package board 2 are mutually different, the amounts of thermal expansion are mutually different. As a result, a mutual shearing force is applied between the semiconductor chip 9 and package board 2 by way of the solder bumps 7.
In this case, in the present embodiment, the wiring layer 16, which is the topmost layer of the package board 2, is formed from an insulation material that has a relatively low Young's modulus of 1 GPa or less. Therefore, the wiring layer 16 can deform in accordance with the thermal expansion of the semiconductor chip 9. As a result, the force exerted between the semiconductor chip 9 and package board 2 is reduced, and a large force is not applied to the solder bumps 7. In a similar fashion, when the semiconductor device 1 is heated or cooled by changes in the ambient temperature, the heat stress exerted between the semiconductor chip 9 and package board 2 is reduced by the deformation of the wiring layer 16, and an excessively large force is not applied to the solder bumps 7. As a result, the semiconductor device 1 does not warp and the solder bumps 7 do not become fractured.
As described above, in the present embodiment, the topmost layer of the package board 2, i.e., the wiring layer 16 of the semiconductor chip 9 side is formed from a material that has a relatively low Young's modulus of 1 GPa or less when the temperature is 10 to 30° C. Therefore, an excessively large force is not applied to the solder bumps 7 even when a temperature cycle is applied to the semiconductor device 1 due to the operation of the semiconductor chip 9 or changes in the ambient temperature, and the solder bumps 7 can be prevented from becoming fractured. It is possible to prevent the solder bumps 7 from becoming fractured by the fatigue brought on by the repeated application of heat stress on the solder bumps 7. Accordingly, the semiconductor device 1 has high connection reliability in relation to temperature cycles. In contrast, the wiring layer is conventionally formed from a material that has a Young's modulus that is as high as possible, i.e., a hard material, so as to reduce deformations caused by heat stress. For this reason, the heat stress is concentrated in the solder bumps, and the solder bumps become fractured.
Since the elongation at break of the material that forms the wiring layer 16 is 20% or higher, cracks and other defects are not generated in the wiring layer 16 even when the wiring layer 16 deforms in accordance with the thermal expansion of the semiconductor chip 9, and the reliability of the semiconductor device 1 is high.
In the present embodiment, the insulation material that forms the wiring layer 16 contains crosslinked rubber that has a double bond and a polar group in the structure of the material. Therefore, electroless copper plating properties are good, and adhesiveness between the Cu layer and the wiring layer 16 is higher when the Cu layer is formed on the wiring layer 16 using an electroless plating method. The Young's modulus of the insulation material is stable and is kept at 1 GPa or less by adding the crosslinked rubber described above to the insulation material.
An example was shown in the embodiment described above in which only the wiring layer 16, which is the topmost layer of the package board 2, is formed from a resin that has a Young's modulus of 1 GPa or less at room temperature, but the present invention is not limited to this configuration, and the two or more wiring layers comprising the topmost layer may be formed from an insulation layer that contains the crosslinked rubber (E) and has a Young's modulus of 1 GPa or less, or all of the wiring layers of the package board 2 may be formed from this insulation material. The entire package board 2 can thereby deform, and the effect of reducing heat stress can be further enhanced.
In addition to the topmost layer of the package board 2, the wiring bottommost wiring layer of the package board 2, i.e., the wiring layer facing the motherboard (not shown) in the package board 2, is also preferably formed from the insulation material described above. The bottommost wiring layer of the package board 2 can thereby deform in accordance with the thermal expansion of the motherboard, and the thermal stress applied to the BGA balls 8 can be reduced. As a result, warping of the semiconductor device 1 and fatigue fracturing of the BGA balls 8 can be prevented and the connection reliability in relation to temperature cycles can be improved. The amount of elongation at break of the insulation material that forms the bottommost wiring layer of the package board 2 described above is preferably 50% or higher.
Ball pads 6 and BGA balls 8 may be disposed on the surface of the side on which the semiconductor chip 9 are mounted of the package board 2, and the BGA balls 8 may be connected to the motherboard. A solder paste may be disposed instead of solder bumps 7.
EXAMPLES
The effects of the embodiments of the present invention are described in detail below by making a comparison with comparative examples that do not fall within the scope of the claims. In the present example, the insulation material described in the embodiment above was actually fabricated; a laminate film, a single-sided copper laminate sheet, an FCBGA semiconductor device, and other sample materials were fabricated using the resin material; and the results were evaluated. Described first are the components that form the resin material of the examples and comparative examples. TABLE 1 shows each of these components, i.e., the reactive elastomers (A), the epoxy resin (B), and the epoxy resin curing agent (C). The resin (D) in which the distance between the functional groups is greater than that of phenol novolac resin is one type of the epoxy resin curing agent (C). TABLE 2 shows the additives (E) that are added to the resin materials.
TABLE 1
Molecular Hydroxyl group Epoxy
Component Type weight equivalent equivalent
Symbol Substance Symbol Substance (Mw) (g/eq) (g/eq)
A Reactive A1 Polyamide 20,000 5,000 —
elastomer elastomer
without CN
A2 Polyamide 20,000 2,500 —
elastomer
without CN
A3 Flexible — — 1,070
epoxy resin
A4 Flexible — — 1,800
epoxy resin
A5 Polyamide 50,000 5,000 —
elastomer
without CN
A6 Polyamide 100,000 5,000 —
elastomer
without CN
A7 Polyamide 150,000 5,000 —
elastomer
without CN
A8 Polyamide 200,000 5,000 —
elastomer
without CN
B Epoxy resin B1 Phenol  1,780 —   274
biphenylene
aralkyl
epoxy resin
B2 Cresol 600(solid) —   190
novolac
epoxy resin
C Epoxy C1 p-Cresol 1,200   118 —
resin novolac
curing resin
agent C2 Phenol 500(solid)   100 —
novolac
resin
D D1 Phenol 1,100   169 —
xylene
resin
Among the reactive elastomers (A) shown in TABLE 1, the flexible epoxy resin (A3) is Epofriend AT501 (registered trade name) manufactured by Daicel Chemical Industries, and the styrene percentage content is 40 mass %. The flexible epoxy resin (A4) is Epofriend AT504 (registered trade name) manufactured by Daicel Chemical Industries, and the styrene percentage content is 70 mass %.
TABLE 2
Component Type
Symbol Substance Symbol Substance
E Additive E1 Crosslinked styrene-
butadiene rubber having a
double bond and a polar
group
E2 Epoxy-containing
polybutadiene rubber
E3 End-epoxidated
polybutadiene
E4 Core-shell acrylic rubber
particles
E5 Calcium carbonate
Among the additives (E) shown in TABLE 2, the styrene-butadiene rubber (E1) is a crosslinked styrene-butadiene rubber having an OH group, a COOH group, or other polar functional groups. Specifically, the rubber may be XSK-500 (registered trade name) manufactured by JSR, and an L711ST/MEK solution can be used. The solid concentration is 20 mass %, and the viscosity is 460 mPas. The epoxy-containing polybutadiene rubber (E2) is Epolead PB3600 (registered trade name) manufactured by Daicel Chemical Industries, has a molecular weight of 5,900, and has an epoxy equivalent of 200 g/eq. The end-epoxidated polybutadiene rubber (E3) is Denarex R-45EPT (registered trade name) manufactured by Nagase Chemtex, and the epoxy equivalent is 1,570 g/eq. The core-shell acrylic rubber particles (E4) is Metablen KW-4426 (registered trade name) manufactured by Mitsubishi Rayon. The calcium carbonate (E5) is Caltex 5 (registered trade name) manufactured by Maruo Calcium.
(1) Method for Preparing a Varnish Solution
A number of components were selected from among the components described above, as shown in TABLES 4 to 6, and were dissolved and dispersed in an organic solution together with a curing acceleration catalyst. TABLE 3 shows the curing acceleration catalyst and organic solutions used in this case. For example, No. 2 (an example) shown in TABLE 4 was prepared as a mixture by adding 0.05 mass % of the imidazole catalyst shown in TABLE 3 as the curing acceleration catalyst to a resin material containing 67.5 mass % of a polyamide elastomer which does not contain a cyanate (CN) group (A1) as the reactive elastomer (A), 16.84 mass % of a phenol biphenylene aralkyl epoxy resin (B1) as the epoxy resin (B), 5.66 mass % of a p-cresol novolac resin (C1) as the epoxy resin curing agent (C), and 10 mass % of a styrene-butadiene rubber (E1) as the additive (E), wherein the mass ((A)+(B)+(C)+(E)) of the resin material was 100 mass %. This mixture was dissolved and dispersed in an organic solvent (N,N-dimethylformamide: DMF) to prepare a varnish solution in which the total amount of the non-volatile components, i.e., the components other than the organic solvent, was 30 mass %.
In TABLES 4 to 6, the numerical values noted in the rows corresponding to the components indicate the mass ratios of the components in the resin component. For example, in No. 2 (an example) shown in TABLE 4, the mass ratio of the reactive elastomer A1 in relation to the entire resin component, i.e., the value of (A1×100)/(A+B+C+E), is 67.50%, wherein the A1 mass % is the content of the reactive elastomer A1. Also, A=A1+A2+A3+A4, B=B1, C=C1+D1, and E=E1+E2+E3+E4+E5. The abbreviation “phr” refers to “per hundred resin” and expresses the mass ratio (mass %) of the curing acceleration catalyst when the mass of the resin is 100.
TABLE 3
Material Type
Curing acceleration Imidazole catalyst “1B2PZ”
catalyst manufactured by Shikoku Chemicals
Corp.
Additive Cyclopentanone manufactured by
Zeon Corp.
N-dimethylformamide manufactured
by Kanto Chemical Co.
TABLE 4
No.
1
Comparative 2 3 4 5
example Example Example Example Example
Reactive 75.00 67.50 — 71.25 60.00
elastomer A1
Reactive — — 67.50 — —
elastomer A2
Reactive — — — — —
elastomer A3
Reactive — — — — —
elastomer A4
Epoxy resin B1 18.71 16.84 16.84 17.78 14.97
Epoxy resin 6.29 5.66 5.66 5.97 5.03
curing agent C1
Epoxy resin — — — — —
curing agent D1
Inorganic — — — — —
filler
Curing 0.05 0.05 0.05 0.05 0.05
acceleration
catalyst (phr)
Additive E1 — 10 10 5 20
Additive E2 — — — — —
Additive E3 — — — — —
Additive E4 — — — — —
Additive E5 — — — — —
Electroless Cu X ⊚ ⊚ ⊚ ⊚
plating
properties
Toughness Elongation
50 33 55 36 30
at
break
(%)
Young's 0.64 0.39 0.50 0.62 0.35
modulus
(GPa)
Circuit ⊚ ⊚ ⊚ ⊚ ⊚
embedding
properties
Connection 0/38 0/38 0/38 0/38 0/38
reliability
Insulation Over 500 Over 500 Over Over Over
reliability 500 500 500
(hours)
TABLE 5
No.
6 8 9
Comparative 7 Comparative Exam-
example Example example ple
Reactive elastomer — — — —
A1
Reactive elastomer — — — —
A2
Reactive elastomer 39.00 32.50 12.87 12.87
A3
Reactive elastomer — — 26.13 26.13
A4
Epoxy resin B1 14.00 11.67 14.00 14.00
Epoxy resin curing — — — —
agent C1
Epoxy resin curing 7.00 5.83 7.00 7.00
agent D1
Inorganic filler 40 40 40 40
Curing 0.05 0.05 0.05 0.05
acceleration
catalyst (phr)
Additive E1 — 10 — 10
Additive E2 — — — —
Additive E3 — — — —
Additive E4 — — — —
Additive E5 — — — —
Electroless Cu X ◯ X ◯
plating properties
Toughness Elongation 120 84 70 52
at break
(%)
Young's 0.30 0.40 0.27 0.60
modulus
(GPa)
Circuit embedding ⊚ ⊚ ⊚ ⊚
properties
Connection 0/38 0/38 0/38 0/38
reliability
Insulation Over 500 Over 500 Over 500 Over
reliability 500
(hours)
TABLE 6
No.
10 11 12 13
2 Comparative Comparative Comparative Comparative
Example example example example example
Reactive 67.50 67.50 67.50 67.50 67.50
elastomer A1
Reactive — — — — —
elastomer A2
Reactive — — — — —
elastomer A3
Reactive — — — — —
elastomer A4
Epoxy resin B1 16.84 16.84 16.84 16.84 16.84
Epoxy resin 5.66 5.66 5.66 5.66 5.66
curing agent C1
Epoxy resin — — — — —
curing agent D1
Inorganic filler — — — — —
Curing 0.05 0.05 0.05 0.05 0.05
acceleration
catalyst (phr)
Additive E1 10 — — — —
Additive E2 — 10 — — —
Additive E3 — — 10 — —
Additive E4 — — — 10 —
Additive E5 — — — — 10
Electroless Cu ⊚ X X X X
plating
properties
Toughness Elongation 33 32 36 41 20
at
break (%)
Young's 0.39 0.67 0.49 0.80 0.88
modulus
(GPa)
Circuit ⊚ ⊚ ⊚ ⊚ ⊚
embedding
properties
Connection 0/38 0/38 0/38 0/38 0/38
reliability
Insulation Over Over 500 Over 500 Over 500 Over 500
reliability 500
(hours)
(2) Fabrication of Laminate Film
The above-described varnish solution was uniformly coated onto a polyethylene terephthalate (PET) film on which a release agent had been coated, using a coating machine so as to obtain a target thickness. The film was thereafter dried for 5 minutes at a temperature of 100° C. to volatilize the solution at a constant rate. The resin surface was covered using a PET film having a release agent and a three-layer laminate film; i.e., a laminate film having the configuration “release PET layer/resin layer/release PET layer” was fabricated. The resin layer (including the remaining solution) in the laminate film was in an uncured state.
(3) Evaluation of the Electroless Copper Plating Properties
The above-described laminate film was layered onto the copper foil of the two sided copper-layered plate in which copper foil had been layered on both sides of the resin board, and the film was then cured. The curing was carried out for 30 minutes under a pressure of 1.5 MPa at a temperature of 120° C., and thereafter carried out for 120 minutes under a pressure of 3 MPa at a temperature of 180° C. A board having a laminate film was thereby fabricated. The laminate film was subsequently desmeared. The desmear treatment was carried out by using the dip method in which a series of steps was performed three times, i.e., the board was immersed for 1 minute in a desmearing solution, neutralized, and then washed. This method is generally carried out by board manufacturers, although the treatment times may vary slightly.
Next, the board was subjected to electroless copper plating to form a copper-plated layer on the laminate film. The adhesiveness of the copper-plated layer was evaluated by observing the external appearance and employing a simple peeling test using tape. Cases in which the adhesiveness of the copped-plated layer was excellent were marked with “⊚,” cases in which the adhesiveness was sufficient for practical purposes were marked with “◯,” and cases in which adhesiveness was poor were marked with “X.” The evaluation results are shown in TABLES 4 to 6.
(4) Toughness Evaluation
The laminate film was placed under a pressure of 3 MPa for one hour at a temperature of 160° C., held for two hours without the application of pressure at a temperature of 180° C., and then press molded to fabricate a cured film having a thickness of 50 μm for tensile testing. The cured film was then cut into strips having a width of 10 mm and a length of 80 mm, and the tensile test was performed. The conditions of the tensile test were set to be a distance of 60 mm between supports that support the cured film and an elastic stress velocity of 5 mm/minute. The tensile test was used to calculate the elongation at break and Young's modulus.
(5) Evaluation of Circuit Embedding Properties
A release PET on one side was peeled away from the laminate film (release PET layer/resin layer/release PET layer), and the resin layer was exposed. A conventional three-layer CCL, i.e., a conventional three-layer CCL having a three-layer structure composed of “PEN layer/resin layer (ABF-GX (registered trade name) manufactured by Ajinomoto Fine-Techno)/copper foil,” was prepared, and a line-and-space pattern simulating a copper wiring circuit was formed on the surface of the copper foil. The widths of the lines and spaces in the pattern were 100 μm. The three-layer CCL copper foil surface was superimposed on the resin layer of the laminate film, and a mirror wafer was mounted on the three-layer CCL.
Samples were thereby fabricated having the following layers in the following order: release PET layer/resin layer (resin layer of example or comparative example)/copper foil-conventional resin layer-PEN layer-mirror wafer). The samples were subjected to a pressure of 1 MPa for 30 minutes at a temperature of 180° C., and the resin layer of the laminate film and the patterned copper foil were made to bond. Next, the samples were observed using a microscope, the extent to which the patterns in the copper foil were embedded in the resin layer was observed, and the quality of the circuit embedding properties was evaluated. Cases in which the circuit embedding properties were excellent were marked with “⊚”, cases in which the circuit embedding properties have no practical problem were marked with “◯” and cases in which the circuit embedding properties have some practical problem were marked with “Δ”. The evaluation results are shown in TABLES 4 to 8.
TABLE 7
No.
15
14 Comparative 16 17 18 19
Example example Example Example Example Example
Reactive — — — — — —
elastomer A1
Reactive — — — — 37 —
elastomer A5
Reactive 60 60 15 37 — —
elastomer A6
Reactive — — — — — 37
elastomer A7
Reactive — — — — — —
elastomer A8
Epoxy resin B1 14.97 — — — — —
Epoxy resin B2 — 13 43 28 28 28
Epoxy resin 5.03 — — — — —
curing agent
C1
Epoxy resin — 7 22 15 15 15
curing agent
C2
Additive E1 20 20 20 20 20 20
Curing 0.05 0.05 0.05 0.05 0.05 0.05
acceleration
catalyst (phr)
Electroless Cu ⊚ ⊚ ⊚ ⊚ ⊚ ⊚
plating
properties
Toughness Elongation 55 50 21 38 30 42
at break
(%)
Young's 0.70 0.75 1.00 0.85 0.65 0.90
modulus
(GPa)
Circuit ◯ ◯ ⊚ ⊚ ⊚ ◯
embedding
properties
180° C., 30 min.
Connection 0/38 0/38 0/38 0/38 0/38 0/38
reliability
Insulation Over 500 Over 500 Over 500 Over 500 Over 500 Over 500
reliability
(hours)
TABLE 8
No.
21 24
20 Comparative 22 23 Comparative
Example example Example Example example
Reactive — — — — —
elastomer A1
Reactive — — — — —
elastomer A5
Reactive — 5 60 75 85
elastomer A6
Reactive — — — — —
elastomer A7
Reactive 37 — — — —
elastomer A8
Epoxy resin B1 — — — — —
Epoxy resin B2 28 59 23 13 7
Epoxy resin — — — — —
curing agent C1
Epoxy resin
15 31 12 7 3
curing agent C2
Additive E1 20 5 5 5 5
Curing 0.05 0.05 0.05 0.05 0.05
acceleration
catalyst (phr)
Electroless Cu ⊚ ⊚ ⊚ ⊚ X
plating
properties
Toughness Elongation
45 12 40 60 70
at break
(%)
Young's 0.92 2.10 1.00 0.80 0.70
modulus
(GPa)
Circuit ◯ ⊚ ◯ ◯ Δ
embedding
properties
180° C., 30 min.
Connection 0/38 10/38 0/38 0/38 2/38
reliability
Insulation Over Over 500 Over 500 Over 500 Over 500
reliability 500
(hours)
(6) Fabrication of a Single-Sided Copper-Plated Prepreg Material
The varnish solution was uniformly coated onto the roughened surface (also referred to a matted surface) of the copper foil using a coating machine so as to obtain a target thickness. The film was thereafter dried for 5 minutes at a temperature of 100° C. to volatilize the solution at a constant rate. The resin surface was covered using a PET film having a release agent, and a single-sided copper-plated prepreg material having a three-layer structure (release PET layer/resin portion/copper foil) was fabricated. The resin layer (also including the remaining solution) in the prepreg material was in an uncured state.
(7) Fabrication of an FCBGA Semiconductor Device
Wiring was formed on the copper foil of the single-sided copper-plated prepreg material described above. A plurality of layers of the single-sided copper-plated prepreg material was layered using the build-up method to fabricate a package board. A semiconductor chip was mounted on the package board, a frame-shaped stiffener was provided about the periphery of the semiconductor chip, and a lid (heat sink) was bonded to the semiconductor chip and reinforcing plate. The FCBGA semiconductor device shown in FIG. 1 was fabricated thereby.
(8) Evaluation of Connection Reliability
Thirty-eight FCBGA semiconductor devices were prepared for the each of the resin materials, and the semiconductor devices were subjected to a temperature cycle test. The temperature cycle test was started from room temperature, hand the temperature was reduced to −40° C. and held at −40° C. for 15 minutes. The temperature was then increased to 125° C. and held at 125° C. for 15 minutes to complete a single cycle. The heating and cooling times were constant at 15 minutes. Cases in which cracks were generated in the connection parts (solder bumps) between the semiconductor chip and package board comprising the FCBGA semiconductor device were determined to be defective cases when the temperature cycle test was carried out for 1,000 cycles. The number of cases in which defects occurred (defect generation count) was used as an index of the connection reliability. In other words, the connection reliability was determined to be more excellent for FCBGA semiconductor devices that have a fewer number of defects. The evaluation results are shown in TABLES 4 to 8. The entries in the row titled “Connection reliability” in TABLES 4 to 8 were obtained by carrying out the temperature cycle test described above, and the entries indicate the number of semiconductor devices among the thirty-eight FCBGA semiconductor devices that produced defects in each sample.
(9) Evaluation of Insulation Reliability
A board for evaluating insulation reliability was fabricated using the varnish solution described above. FIG. 3 is a diagram showing a schematic of the evaluation board. FIG. 4 is a top view showing the specifics of the evaluation board. FIG. 5 is a partial enlarged cross-sectional view of the evaluation board. Also shown in FIG. 5 is the flat shape of the wiring 45. The board for evaluation had two pectinate wirings 41 disposed so as to be inter-nested, as shown in FIG. 3. Specifically, the two pectinate wirings 41 were disposed so that the teeth of one pectinate wiring 41 were positioned between the teeth of the other pectinate wiring 41, and the pectinate wirings did not make contact with each other. The pectinate wirings were connected to square electrodes 42.
A FR-4 board 44 as a core was disposed on the evaluation board 43, as shown in FIG. 4. The external dimensions of the board 44 were 24.4 mm in the lengthwise direction, 8.0 mm in the crosswise direction, and a thickness of 0.8 mm. Two electrodes 42 were disposed on the surface of the board 44 at a distance from each other in the lengthwise direction of the board 44. As viewed from above, the length of one side of the electrode 42 was 5.2 mm. The two pectinate wirings 41 were disposed so as to be interested in the area between the electrodes 42. Wiring 45 having 10 wires as the teeth was disposed in each of the pectinate wirings 41. The length of each wiring 45 was 8.7 mm. Thirty vias 46 were formed in each of the wires 45. Specifically, the total number of vias disposed in the evaluation board 43 was 2×10×30=600. These 600 vias 46 were arrayed in the form of a matrix (20×30). The array pitch of the vias was 300 μm in both directions.
A Cu pattern 47 composed of Cu was intermittently disposed on the surface of the board 44 along the direction in which the wiring 45 extended, as shown in FIG. 5. A build-up resin layer 48 having a thickness of 50 μm was disposed so as to cover the Cu pattern 47. The build-up resin layer 48 was formed from any of the resins shown in TABLES 1 to 3. A Cu pattern 49 composed of CI was intermittently disposed on the surface of the build-up resin layer 48 along the direction in which the wiring 45 extended. The Cu patterns 47 and 49, as viewed from above, had two 150-μm diameter circular portions and a single rectangular portion connecting the circular portions. The thickness of the rectangular portion was 18 μm. The rectangular portions of the Cu pattern 49 were positioned directly above the areas between the Cu patterns 47, and the circular portions of the Cu patterns 49 were positioned directly above the circular portions of the Cu pattern 47.
One via 46 was disposed between each of the circular portions of the Cu pattern 47 and the circular portions of the Cu pattern 49 in the build-up resin layer 48, and the vias 46 connected the Cu pattern 47 and Cu pattern 49 to each other. The shape of the vias 46 was a conic trapezoid, the diameter of the upper portion was 100 μm, and the diameter of the lower portion was 75 μm. The distance between two vias connected to the same Cu pattern 47 and Cu pattern 49 was 300 μm, as described above. A solder resist 50 having a thickness of 35 μm was disposed on the build-up resin layer 48 so as to cover the Cu pattern 49. A Cu pattern 51 having a thickness of 18 μm was disposed on the entire surface of the reverse surface of the board 44. For the sake of convenience, the build-up resin layer 48 and solder resist 50 are not depicted in FIG. 4.
A HAST (Highly Accelerated temperature humidity Stress Test) was performed using the evaluation board 43 fabricated in the manner described above. The test conditions were a temperature of 130° C., a humidity of 85 RH %, and a voltage of 5 V applied between the electrodes. The time required for the resistance between the electrodes 42 to decrease to 1×109Ω or less was measured and used as an index of the insulation reliability. The longer this time was measured to be, the better the insulation reliability was. The test was carried out for a maximum of 500 hours. The test results are shown in TABLES 4 to 8. The entry “over 500 hours” in TABLES 4 to 8 indicates that the resistance between the electrodes did not decrease to 1×109Ω or less, even when the test was continued for 500 hours.
(10) Evaluation Results
Nos. 2 to 5, No. 7, No. 9, No. 14 to 20, No. 22 and No. 23 shown in TABLES 4 to 8 are examples of the present invention. In these examples, a crosslinked styrene-butadiene rubber (E1) having a double bond and a polar group had been added as the additive (E) used with the insulation material, and the content of the Reactive elastomer (A) is 15 to 80 mass %, and the adhesiveness of the copper-plating layer formed using electroless plating on the laminate film was therefore high. In other words, the electroless copper plating properties were good. In contrast, Nos. 1, 6, 8, 10 to 13, 21 and 24 shown in TABLES 4 to 6 and 8 are comparative examples. In these comparative examples Nos. 1, 6, 8, 10 to 13, a crosslinked styrene-butadiene rubber (E1) having a double bond and a polar group in the insulation material was not added, and the electroless copper plating properties were therefore poor. Also, in the comparative example No. 21, the content of the Reactive elastomer (A) is less than 15 mass %, the elongation of the insulation material is therefore insufficient. In the comparative example No. 21, the Young's modulus is over 1 GPa and the connection reliability is therefore degraded in comparison to the examples. Furthermore, in the comparative example No. 24, the content of the Reactive elastomer (A) is over 80 mass %, the hardening of the insulation material is insufficient and therefore the chemical resistance of the insulation material was reduced and also electroless plating property was degraded. The toughness, circuit embedding properties, connection reliability, and insulation reliability was good for both the examples and comparative examples described above except the Nos. 21 and 24.
INDUSTRIAL APPLICABILITY
The present invention can be advantageously used in FCBGA, WLCP, and other semiconductor devices in which a semiconductor chip is mounted on a wiring board by way of solder bumps.

Claims (8)

1. An insulation material having a Young's modulus of 1 GPa or less in a temperature range of 10 to 30° C., comprising:
(A) a reactive elastomer that reacts with epoxy resin or an epoxy resin curing agent and comprises a polyamide elastomer containing a phenolic hydroxyl group as represented by one of the following formulae that does not contain a cyanate group in the structure thereof,
Figure US07981963-20110719-C00009
wherein R1 is a bivalent aromatic compound with a carbon number of from 6 to 12 having a phenolic hydroxyl group, R2 is a bivalent aromatic compound having a carbon number of from 6 to 12 that does not contain a phenolic hydroxyl group, or a bivalent aromatic compound having a carbon number of from 1 to 10, and R3 is a bivalent aromatic compound having a carbon number of from 6 to 12, or a bivalent aromatic compound having a carbon number of from 1 to 10, x and y are each independently an integer from 3 to 7, z is an integer from 5 to 15, n=1+m, n is an integer from 2 to 200, and 1 and m satisfy the relationship m/(1+m)≧0.04;
(B) an epoxy resin;
(C) an epoxy resin curing agent; and
(D) a crosslinked rubber having a double bond and a polar group in the structure thereof and comprising a crosslinked styrene-butadiene rubber having a hydroxyl group or a carboxyl group as the polar group.
2. The insulation material according to claim 1, wherein the value of (E×100)/(A+B+C+E) is 3 to 25%, wherein A mass % is the content of said reactive elastomer, B mass % is the content of said epoxy resin, C mass % is the content of said epoxy resin curing agent, and E mass % is the content of said crosslinked rubber.
3. The insulation material according to claim 2, wherein said value of (E×100)/(A+B+C+E) is 5 to 20%.
4. The insulation material according to claim 1, wherein the value of (A×100)/(A+B+C+E) is 15 to 80 mass %, wherein A mass % is the content of said reactive elastomer, B mass % is the content of said epoxy resin, C mass % is the content of said epoxy resin curing agent, and E mass % is the content of said crosslinked rubber.
5. The insulation material according to claim 4, wherein the value of (A×100)/(A+B+C+E) is 50 to 75 mass %.
6. The insulation material according to claim 1, wherein the value of (B×100)/(A+B+C+E) is 20% or less, wherein A mass % is the content of said reactive elastomer, B mass % is the content of said epoxy resin, C mass % is the content of said epoxy resin curing agent, and E mass % is the content of said crosslinked rubber.
7. A wiring board using the insulation material according to claim 1.
8. A semiconductor device being provided with the wiring board according to claim 7.
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