JP2016018806A - 配線基板、配線基板の製造方法 - Google Patents

配線基板、配線基板の製造方法 Download PDF

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Publication number
JP2016018806A
JP2016018806A JP2014138731A JP2014138731A JP2016018806A JP 2016018806 A JP2016018806 A JP 2016018806A JP 2014138731 A JP2014138731 A JP 2014138731A JP 2014138731 A JP2014138731 A JP 2014138731A JP 2016018806 A JP2016018806 A JP 2016018806A
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JP
Japan
Prior art keywords
layer
wiring
metal post
metal
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014138731A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016018806A5 (enExample
Inventor
貴博 六川
Takahiro Mutsukawa
貴博 六川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2014138731A priority Critical patent/JP2016018806A/ja
Priority to US14/753,203 priority patent/US9431333B2/en
Priority to KR1020150093345A priority patent/KR20160004939A/ko
Priority to TW104121259A priority patent/TWI680701B/zh
Priority to CN201510378393.4A priority patent/CN105246247A/zh
Publication of JP2016018806A publication Critical patent/JP2016018806A/ja
Publication of JP2016018806A5 publication Critical patent/JP2016018806A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2014138731A 2014-07-04 2014-07-04 配線基板、配線基板の製造方法 Pending JP2016018806A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2014138731A JP2016018806A (ja) 2014-07-04 2014-07-04 配線基板、配線基板の製造方法
US14/753,203 US9431333B2 (en) 2014-07-04 2015-06-29 Wiring substrate
KR1020150093345A KR20160004939A (ko) 2014-07-04 2015-06-30 배선 기판 및 배선 기판 제조 방법
TW104121259A TWI680701B (zh) 2014-07-04 2015-07-01 配線基板及其製造方法
CN201510378393.4A CN105246247A (zh) 2014-07-04 2015-07-01 布线基板、布线基板的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014138731A JP2016018806A (ja) 2014-07-04 2014-07-04 配線基板、配線基板の製造方法

Publications (2)

Publication Number Publication Date
JP2016018806A true JP2016018806A (ja) 2016-02-01
JP2016018806A5 JP2016018806A5 (enExample) 2017-05-18

Family

ID=55017538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014138731A Pending JP2016018806A (ja) 2014-07-04 2014-07-04 配線基板、配線基板の製造方法

Country Status (5)

Country Link
US (1) US9431333B2 (enExample)
JP (1) JP2016018806A (enExample)
KR (1) KR20160004939A (enExample)
CN (1) CN105246247A (enExample)
TW (1) TWI680701B (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017152477A (ja) * 2016-02-23 2017-08-31 イビデン株式会社 プリント配線板
US10672963B2 (en) 2017-08-31 2020-06-02 Nichia Corporation Method of manufacturing substrate and method of manufacturing light emitting device
JP2020202205A (ja) * 2019-06-06 2020-12-17 イビデン株式会社 プリント配線板とプリント配線板の製造方法
JP2022015758A (ja) * 2020-07-09 2022-01-21 イビデン株式会社 配線基板
US11622446B2 (en) 2020-07-09 2023-04-04 Ibiden Co., Ltd. Wiring substrate
JP2023108213A (ja) * 2022-01-25 2023-08-04 シチズンファインデバイス株式会社 基板の製造方法
JP2024510941A (ja) * 2021-03-23 2024-03-12 クアルコム，インコーポレイテッド パッドオンパッド相互接続部を含む基板を有するパッケージ
US11935822B2 (en) 2020-07-09 2024-03-19 Ibiden Co., Ltd. Wiring substrate having metal post offset from conductor pad and method for manufacturing wiring substrate

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651116B2 (en) 2016-06-30 2020-05-12 Intel Corporation Planar integrated circuit package interconnects
CN108289383B (zh) * 2018-03-05 2020-02-18 东莞市龙谊电子科技有限公司 印制电路板的选择性电镀工艺
US11500489B2 (en) 2019-01-30 2022-11-15 Chengdu Boe Optoelectronics Technology Co., Ltd. Flexible circuit board and manufacturing method, display device, circuit board structure and display panel thereof
WO2020156475A1 (zh) * 2019-01-30 2020-08-06 京东方科技集团股份有限公司 柔性电路板及制作方法、电子装置模组及电子装置
CN111511109B (zh) 2019-01-30 2021-11-23 京东方科技集团股份有限公司 柔性电路板及制作方法、电子装置模组及电子装置
US12127340B2 (en) * 2019-09-30 2024-10-22 Kyocera Corporation Wiring substrate
JP2024094553A (ja) * 2022-12-28 2024-07-10 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
US20240387430A1 (en) * 2023-05-17 2024-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Metal bump structures and methods of forming the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080267A (ja) * 2004-09-09 2006-03-23 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2007103648A (ja) * 2005-10-04 2007-04-19 Hitachi Chem Co Ltd プリント配線板、半導体チップ搭載基板、半導体パッケージ、プリント配線板の製造方法、及び半導体チップ搭載基板の製造方法
JP2008021883A (ja) * 2006-07-13 2008-01-31 Murata Mfg Co Ltd 多層セラミック電子部品、多層セラミック基板、および多層セラミック電子部品の製造方法
JP2010287710A (ja) * 2009-06-11 2010-12-24 Renesas Electronics Corp 半導体装置およびその製造方法
JP2011100957A (ja) * 2009-11-06 2011-05-19 Via Technologies Inc 回路基板及びその製造方法
US20110299259A1 (en) * 2010-06-04 2011-12-08 Yu-Ling Hsieh Circuit board with conductor post structure
JP2013105908A (ja) * 2011-11-14 2013-05-30 Ngk Spark Plug Co Ltd 配線基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI268012B (en) * 2003-08-07 2006-12-01 Phoenix Prec Technology Corp Electrically conductive structure formed between neighboring layers of circuit board and method for fabricating the same
JP4769056B2 (ja) 2005-10-07 2011-09-07 日本特殊陶業株式会社 配線基板及びその製法方法
JP5043743B2 (ja) * 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US20130168132A1 (en) * 2011-12-29 2013-07-04 Sumsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080267A (ja) * 2004-09-09 2006-03-23 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2007103648A (ja) * 2005-10-04 2007-04-19 Hitachi Chem Co Ltd プリント配線板、半導体チップ搭載基板、半導体パッケージ、プリント配線板の製造方法、及び半導体チップ搭載基板の製造方法
JP2008021883A (ja) * 2006-07-13 2008-01-31 Murata Mfg Co Ltd 多層セラミック電子部品、多層セラミック基板、および多層セラミック電子部品の製造方法
JP2010287710A (ja) * 2009-06-11 2010-12-24 Renesas Electronics Corp 半導体装置およびその製造方法
JP2011100957A (ja) * 2009-11-06 2011-05-19 Via Technologies Inc 回路基板及びその製造方法
US20110299259A1 (en) * 2010-06-04 2011-12-08 Yu-Ling Hsieh Circuit board with conductor post structure
JP2013105908A (ja) * 2011-11-14 2013-05-30 Ngk Spark Plug Co Ltd 配線基板

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017152477A (ja) * 2016-02-23 2017-08-31 イビデン株式会社 プリント配線板
US10672963B2 (en) 2017-08-31 2020-06-02 Nichia Corporation Method of manufacturing substrate and method of manufacturing light emitting device
JP2020202205A (ja) * 2019-06-06 2020-12-17 イビデン株式会社 プリント配線板とプリント配線板の製造方法
JP2022015758A (ja) * 2020-07-09 2022-01-21 イビデン株式会社 配線基板
US11622446B2 (en) 2020-07-09 2023-04-04 Ibiden Co., Ltd. Wiring substrate
US11935822B2 (en) 2020-07-09 2024-03-19 Ibiden Co., Ltd. Wiring substrate having metal post offset from conductor pad and method for manufacturing wiring substrate
JP2024510941A (ja) * 2021-03-23 2024-03-12 クアルコム，インコーポレイテッド パッドオンパッド相互接続部を含む基板を有するパッケージ
JP2023108213A (ja) * 2022-01-25 2023-08-04 シチズンファインデバイス株式会社 基板の製造方法
JP7689089B2 (ja) 2022-01-25 2025-06-05 シチズンファインデバイス株式会社 基板の製造方法

Also Published As

Publication number Publication date
KR20160004939A (ko) 2016-01-13
CN105246247A (zh) 2016-01-13
US9431333B2 (en) 2016-08-30
TWI680701B (zh) 2019-12-21
TW201603663A (zh) 2016-01-16
US20160005685A1 (en) 2016-01-07

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