JP2015536521A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2015536521A5 JP2015536521A5 JP2015539863A JP2015539863A JP2015536521A5 JP 2015536521 A5 JP2015536521 A5 JP 2015536521A5 JP 2015539863 A JP2015539863 A JP 2015539863A JP 2015539863 A JP2015539863 A JP 2015539863A JP 2015536521 A5 JP2015536521 A5 JP 2015536521A5
- Authority
- JP
- Japan
- Prior art keywords
- page
- partial
- data
- pages
- programming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 23
- 238000013507 mapping Methods 0.000 claims 9
- 230000003213 activating effect Effects 0.000 claims 2
- 238000002360 preparation method Methods 0.000 claims 2
- 230000036755 cellular response Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000013506 data mapping Methods 0.000 claims 1
- 230000008672 reprogramming Effects 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/661,321 | 2012-10-26 | ||
| US13/661,321 US9318199B2 (en) | 2012-10-26 | 2012-10-26 | Partial page memory operations |
| PCT/US2013/066931 WO2014066829A1 (en) | 2012-10-26 | 2013-10-25 | Partial page memory operations |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015536521A JP2015536521A (ja) | 2015-12-21 |
| JP2015536521A5 true JP2015536521A5 (https=) | 2016-12-15 |
| JP6149117B2 JP6149117B2 (ja) | 2017-06-14 |
Family
ID=50545351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015539863A Active JP6149117B2 (ja) | 2012-10-26 | 2013-10-25 | 部分的なページメモリ動作 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US9318199B2 (https=) |
| EP (1) | EP2912665B1 (https=) |
| JP (1) | JP6149117B2 (https=) |
| KR (1) | KR102274276B1 (https=) |
| CN (1) | CN104903964B (https=) |
| TW (1) | TWI590048B (https=) |
| WO (1) | WO2014066829A1 (https=) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8797806B2 (en) | 2011-08-15 | 2014-08-05 | Micron Technology, Inc. | Apparatus and methods including source gates |
| US10541029B2 (en) | 2012-08-01 | 2020-01-21 | Micron Technology, Inc. | Partial block memory operations |
| US9318199B2 (en) | 2012-10-26 | 2016-04-19 | Micron Technology, Inc. | Partial page memory operations |
| WO2015005634A1 (ko) * | 2013-07-08 | 2015-01-15 | 주식회사 윌러스표준기술연구소 | 메모리 시스템 및 이의 제어 방법 |
| US10310734B2 (en) * | 2014-12-27 | 2019-06-04 | Intel Corporation | Tier mode for access operations to 3D memory |
| JP5940705B1 (ja) * | 2015-03-27 | 2016-06-29 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
| KR20170011645A (ko) * | 2015-07-23 | 2017-02-02 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치를 포함하는 메모리 시스템 및 그것의 동작 방법 |
| US9779829B2 (en) | 2015-11-17 | 2017-10-03 | Micron Technology, Inc. | Erasing memory segments in a memory block of memory cells using select gate control line voltages |
| US9721663B1 (en) * | 2016-02-18 | 2017-08-01 | Sandisk Technologies Llc | Word line decoder circuitry under a three-dimensional memory array |
| US10318378B2 (en) | 2016-02-25 | 2019-06-11 | Micron Technology, Inc | Redundant array of independent NAND for a three-dimensional memory array |
| US10360973B2 (en) * | 2016-12-23 | 2019-07-23 | Western Digital Technologies, Inc. | Data mapping enabling fast read multi-level 3D NAND to improve lifetime capacity |
| KR20180113230A (ko) * | 2017-04-05 | 2018-10-16 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그것의 동작 방법 |
| US10922220B2 (en) * | 2017-07-01 | 2021-02-16 | Intel Corporation | Read and program operations in a memory device |
| US10109339B1 (en) * | 2017-07-28 | 2018-10-23 | Micron Technology, Inc. | Memory devices with selective page-based refresh |
| US10453533B2 (en) | 2017-11-17 | 2019-10-22 | Micron Technology, Inc. | Memory devices with distributed block select for a vertical string driver tile architecture |
| JP2019169207A (ja) * | 2018-03-22 | 2019-10-03 | 東芝メモリ株式会社 | 半導体記憶装置 |
| KR102575476B1 (ko) * | 2018-07-11 | 2023-09-07 | 삼성전자주식회사 | 비휘발성 메모리 장치의 데이터 저장 방법, 데이터 소거 방법 및 이를 수행하는 비휘발성 메모리 장치 |
| US11487454B2 (en) * | 2019-12-05 | 2022-11-01 | Sandisk Technologies Llc | Systems and methods for defining memory sub-blocks |
| US11256617B2 (en) | 2020-04-01 | 2022-02-22 | Micron Technology, Inc. | Metadata aware copyback for memory devices |
| US11327884B2 (en) * | 2020-04-01 | 2022-05-10 | Micron Technology, Inc. | Self-seeded randomizer for data randomization in flash memory |
| TWI784515B (zh) | 2020-05-27 | 2022-11-21 | 台灣積體電路製造股份有限公司 | 記憶體系統以及操作記憶體系統的方法 |
| US11437092B2 (en) | 2020-05-27 | 2022-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems and methods to store multi-level data |
| US12387789B2 (en) | 2022-12-27 | 2025-08-12 | SanDisk Technologies, Inc. | X-direction divided sub-block mode in NAND |
Family Cites Families (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994014196A1 (en) | 1992-12-08 | 1994-06-23 | National Semiconductor Corporation | High density contactless flash eprom array using channel erase |
| US5835396A (en) | 1996-10-17 | 1998-11-10 | Zhang; Guobiao | Three-dimensional read-only memory |
| US6870769B1 (en) | 1996-12-28 | 2005-03-22 | Hyundai Electronics Industries Co., Ltd. | Decoder circuit used in a flash memory device |
| JP3890647B2 (ja) | 1997-01-31 | 2007-03-07 | ソニー株式会社 | 不揮発性半導体記憶装置 |
| JP3805867B2 (ja) | 1997-09-18 | 2006-08-09 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US6272044B2 (en) | 1998-10-26 | 2001-08-07 | Rohm Co., Ltd. | Semiconductor storage device and method of driving thereof |
| DE69937559T2 (de) | 1999-09-10 | 2008-10-23 | Stmicroelectronics S.R.L., Agrate Brianza | Nicht-flüchtige Speicher mit Erkennung von Kurzschlüssen zwischen Wortleitungen |
| US6307781B1 (en) | 1999-09-30 | 2001-10-23 | Infineon Technologies Aktiengesellschaft | Two transistor flash memory cell |
| JP2002245786A (ja) | 2001-02-16 | 2002-08-30 | Sharp Corp | 半導体集積回路装置およびその制御方法 |
| US6771536B2 (en) * | 2002-02-27 | 2004-08-03 | Sandisk Corporation | Operating techniques for reducing program and read disturbs of a non-volatile memory |
| US7233522B2 (en) | 2002-12-31 | 2007-06-19 | Sandisk 3D Llc | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same |
| JP2004326864A (ja) * | 2003-04-22 | 2004-11-18 | Toshiba Corp | 不揮発性半導体メモリ |
| US7023739B2 (en) | 2003-12-05 | 2006-04-04 | Matrix Semiconductor, Inc. | NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same |
| US7599228B1 (en) | 2004-11-01 | 2009-10-06 | Spansion L.L.C. | Flash memory device having increased over-erase correction efficiency and robustness against device variations |
| US7196930B2 (en) | 2005-04-27 | 2007-03-27 | Micron Technology, Inc. | Flash memory programming to reduce program disturb |
| US8032688B2 (en) | 2005-06-30 | 2011-10-04 | Intel Corporation | Micro-tile memory interfaces |
| US7259991B2 (en) | 2005-09-01 | 2007-08-21 | Micron Technology, Inc. | Operation of multiple select gate architecture |
| JP5016832B2 (ja) | 2006-03-27 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
| US7440321B2 (en) | 2006-04-12 | 2008-10-21 | Micron Technology, Inc. | Multiple select gate architecture with select gates of different lengths |
| US7433231B2 (en) | 2006-04-26 | 2008-10-07 | Micron Technology, Inc. | Multiple select gates with non-volatile memory cells |
| US7626866B2 (en) | 2006-07-28 | 2009-12-01 | Micron Technology, Inc. | NAND flash memory programming |
| US7804718B2 (en) * | 2007-03-07 | 2010-09-28 | Mosaid Technologies Incorporated | Partial block erase architecture for flash memory |
| KR101448169B1 (ko) | 2008-01-02 | 2014-10-13 | 삼성전자주식회사 | 멀티-플레인 구조의 3차원 메모리 장치 |
| KR20090106869A (ko) | 2008-04-07 | 2009-10-12 | 삼성전자주식회사 | 3차원 메모리 장치 및 그것의 구동 방법 |
| US8040744B2 (en) * | 2009-01-05 | 2011-10-18 | Sandisk Technologies Inc. | Spare block management of non-volatile memories |
| US8832353B2 (en) * | 2009-04-07 | 2014-09-09 | Sandisk Technologies Inc. | Host stop-transmission handling |
| CN102341865B (zh) | 2009-04-30 | 2014-07-16 | 力晶股份有限公司 | Nand闪存装置的编程方法 |
| KR101635504B1 (ko) | 2009-06-19 | 2016-07-04 | 삼성전자주식회사 | 3차원 수직 채널 구조를 갖는 불 휘발성 메모리 장치의 프로그램 방법 |
| KR101066696B1 (ko) | 2009-06-29 | 2011-09-21 | 주식회사 하이닉스반도체 | 불휘발성 메모리 소자 |
| WO2011019794A2 (en) | 2009-08-11 | 2011-02-17 | Texas Memory Systems, Inc. | Method and apparatus for addressing actual or predicted failures in a flash-based storage system |
| US8320181B2 (en) | 2009-08-25 | 2012-11-27 | Micron Technology, Inc. | 3D memory devices decoding and routing systems and methods |
| JP2011049206A (ja) | 2009-08-25 | 2011-03-10 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
| US8223525B2 (en) | 2009-12-15 | 2012-07-17 | Sandisk 3D Llc | Page register outside array and sense amplifier interface |
| KR20110132820A (ko) | 2010-06-03 | 2011-12-09 | 삼성전자주식회사 | 다수개의 반도체 레이어가 적층 된 반도체 메모리 장치 및 시스템 |
| US20110297912A1 (en) | 2010-06-08 | 2011-12-08 | George Samachisa | Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof |
| US8237213B2 (en) | 2010-07-15 | 2012-08-07 | Micron Technology, Inc. | Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof |
| US8559229B2 (en) * | 2010-09-30 | 2013-10-15 | Samsung Electronics Co., Ltd. | Flash memory device and wordline voltage generating method thereof |
| JP2012119013A (ja) * | 2010-11-29 | 2012-06-21 | Toshiba Corp | 不揮発性半導体記憶装置 |
| JP2013004123A (ja) | 2011-06-14 | 2013-01-07 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US8797806B2 (en) | 2011-08-15 | 2014-08-05 | Micron Technology, Inc. | Apparatus and methods including source gates |
| US9171627B2 (en) | 2012-04-11 | 2015-10-27 | Aplus Flash Technology, Inc. | Non-boosting program inhibit scheme in NAND design |
| US10541029B2 (en) | 2012-08-01 | 2020-01-21 | Micron Technology, Inc. | Partial block memory operations |
| US9318199B2 (en) | 2012-10-26 | 2016-04-19 | Micron Technology, Inc. | Partial page memory operations |
-
2012
- 2012-10-26 US US13/661,321 patent/US9318199B2/en active Active
-
2013
- 2013-10-25 CN CN201380062847.6A patent/CN104903964B/zh active Active
- 2013-10-25 JP JP2015539863A patent/JP6149117B2/ja active Active
- 2013-10-25 EP EP13848265.8A patent/EP2912665B1/en active Active
- 2013-10-25 TW TW102138824A patent/TWI590048B/zh active
- 2013-10-25 KR KR1020157013333A patent/KR102274276B1/ko active Active
- 2013-10-25 WO PCT/US2013/066931 patent/WO2014066829A1/en not_active Ceased
-
2016
- 2016-04-18 US US15/131,719 patent/US9653171B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2015536521A5 (https=) | ||
| KR102611345B1 (ko) | 메모리 컨트롤러 및 그 동작 방법 | |
| US20200183600A1 (en) | Controller and storage device including controller and nonvolatile memory devices | |
| JP6869885B2 (ja) | メモリの異なるメモリプレーンに同時にアクセスするための装置および方法 | |
| KR102717016B1 (ko) | 메모리 장치 및 그 동작 방법 | |
| KR20190092948A (ko) | 저장 장치 및 그 동작 방법 | |
| KR20210076497A (ko) | 스토리지 장치 및 그 동작 방법 | |
| KR20220058224A (ko) | 메모리 시스템 및 이에 포함된 메모리 컨트롤러의 동작 방법 | |
| KR102743807B1 (ko) | 메모리 장치 및 그 동작 방법 | |
| KR102635689B1 (ko) | 메모리 시스템, 메모리 컨트롤러 및 동작 방법 | |
| KR20190109985A (ko) | 저장 장치 및 그 동작 방법 | |
| KR20190127173A (ko) | 저장 장치 및 그 동작 방법 | |
| CN112346652A (zh) | 存储器控制器及其操作方法 | |
| KR20210086990A (ko) | 패리티를 사용한 메모리 액세스 병렬성 증가 | |
| CN113760794A (zh) | 存储装置和操作存储装置的方法 | |
| KR20210062343A (ko) | 메모리 장치 및 그 동작 방법 | |
| KR20220048377A (ko) | 저장 장치 및 그 동작 방법 | |
| US20210173587A1 (en) | Memory system, memory controller, and method for operating same | |
| KR20220107578A (ko) | 메모리 장치 및 그 동작 방법 | |
| KR20210001134A (ko) | 메모리 장치 및 그 동작 방법 | |
| US12072809B2 (en) | Memory system, memory controller, and operation method of memory system for loading and updating mapping information to host memory area | |
| KR20220021761A (ko) | 메모리 장치 및 그 동작 방법 | |
| US11579787B2 (en) | Extended super memory blocks in memory systems | |
| US11474740B2 (en) | Memory system and memory controller | |
| KR20200095130A (ko) | 메모리 컨트롤러 및 그 동작 방법 |