JP2015502660A5 - - Google Patents
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- Publication number
- JP2015502660A5 JP2015502660A5 JP2014542589A JP2014542589A JP2015502660A5 JP 2015502660 A5 JP2015502660 A5 JP 2015502660A5 JP 2014542589 A JP2014542589 A JP 2014542589A JP 2014542589 A JP2014542589 A JP 2014542589A JP 2015502660 A5 JP2015502660 A5 JP 2015502660A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuits
- circuit
- logic
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 8
- 230000004044 response Effects 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000003287 optical effect Effects 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161563001P | 2011-11-22 | 2011-11-22 | |
| US61/563,001 | 2011-11-22 | ||
| US13/680,530 US8902625B2 (en) | 2011-11-22 | 2012-11-19 | Layouts for memory and logic circuits in a system-on-chip |
| US13/680,530 | 2012-11-19 | ||
| PCT/US2012/066236 WO2013078294A2 (en) | 2011-11-22 | 2012-11-21 | Layouts for memory and logic circuits in a system-on-chip |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015502660A JP2015502660A (ja) | 2015-01-22 |
| JP2015502660A5 true JP2015502660A5 (cg-RX-API-DMAC7.html) | 2016-01-07 |
| JP6257044B2 JP6257044B2 (ja) | 2018-01-10 |
Family
ID=48426797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014542589A Expired - Fee Related JP6257044B2 (ja) | 2011-11-22 | 2012-11-21 | システムオンチップ内のメモリ回路および論理回路のレイアウト |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8902625B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP6257044B2 (cg-RX-API-DMAC7.html) |
| CN (1) | CN103946848B (cg-RX-API-DMAC7.html) |
| TW (1) | TWI616764B (cg-RX-API-DMAC7.html) |
| WO (1) | WO2013078294A2 (cg-RX-API-DMAC7.html) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5956964B2 (ja) * | 2013-08-30 | 2016-07-27 | 株式会社東芝 | 半導体装置 |
| TWI576852B (zh) * | 2015-06-30 | 2017-04-01 | 宏碁股份有限公司 | 電子裝置及其固態硬碟的電源管理方法 |
| CN105319964B (zh) * | 2015-09-29 | 2018-06-22 | 上海新跃仪表厂 | 基于配置文件的运载火箭测试发射流程生成方法及系统 |
| US11392748B2 (en) * | 2018-09-28 | 2022-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit design using fuzzy machine learning |
| DE102019124928A1 (de) | 2018-09-28 | 2020-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integriertes schaltungsdesign unter verwendung von fuzzy-maschinenlernen |
| US12314116B2 (en) | 2020-07-31 | 2025-05-27 | Qualcomm Incorporated | Systems and methods for adaptive power multiplexing |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW231343B (cg-RX-API-DMAC7.html) * | 1992-03-17 | 1994-10-01 | Hitachi Seisakusyo Kk | |
| US5657284A (en) * | 1995-09-19 | 1997-08-12 | Micron Technology, Inc. | Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices |
| US5767565A (en) | 1996-07-22 | 1998-06-16 | Alliance Semiconductor Corporation | Semiconductor devices having cooperative mode option at assembly stage and method thereof |
| US5892703A (en) | 1997-06-13 | 1999-04-06 | Micron Technology, Inc, | Memory architecture and decoder addressing |
| US6605962B2 (en) * | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
| JP2003037173A (ja) * | 2001-07-23 | 2003-02-07 | Niigata Seimitsu Kk | アナログ・デジタル混載集積回路 |
| TW525184B (en) * | 2001-08-17 | 2003-03-21 | High Connector Density Inc | Stackable modules with clustered connections |
| US6717430B2 (en) * | 2002-02-13 | 2004-04-06 | Motorola, Inc. | Integrated circuit testing with a visual indicator |
| US6687147B2 (en) * | 2002-04-02 | 2004-02-03 | Hewlett-Packard Development Company, L.P. | Cubic memory array with diagonal select lines |
| TW594991B (en) * | 2003-04-29 | 2004-06-21 | Faraday Tech Corp | Integrated circuit with one metal layer for programming functionality of a logic operation module |
| US8463996B2 (en) * | 2003-08-19 | 2013-06-11 | Oracle America, Inc. | Multi-core multi-thread processor crossbar architecture |
| US20050044320A1 (en) * | 2003-08-19 | 2005-02-24 | Sun Microsystems, Inc. | Cache bank interface unit |
| JP2006156929A (ja) * | 2004-04-19 | 2006-06-15 | Fujitsu Ltd | 半導体集積回路及びその設計方法 |
| JP2006099719A (ja) * | 2004-08-30 | 2006-04-13 | Sanyo Electric Co Ltd | 処理装置 |
| US20060143384A1 (en) * | 2004-12-27 | 2006-06-29 | Hughes Christopher J | System and method for non-uniform cache in a multi-core processor |
| US7353162B2 (en) * | 2005-02-11 | 2008-04-01 | S2C, Inc. | Scalable reconfigurable prototyping system and method |
| JP2006323643A (ja) * | 2005-05-19 | 2006-11-30 | Nec Electronics Corp | 半導体集積回路のフロアプラン設計プログラム、フロアプラン設計装置、および設計方法 |
| JP2006324471A (ja) * | 2005-05-19 | 2006-11-30 | Toshiba Corp | 半導体集積回路装置 |
| TW200743976A (en) * | 2006-05-19 | 2007-12-01 | Nat Applied Res Lab Nat Chip Implementation Ct | Multi-project System-on-Chip platform and the design method thereof |
| KR101297754B1 (ko) | 2006-07-11 | 2013-08-26 | 삼성전자주식회사 | 메모리 컴파일링 시스템 및 컴파일링 방법 |
| JP4951786B2 (ja) * | 2007-05-10 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP5528662B2 (ja) * | 2007-09-18 | 2014-06-25 | ソニー株式会社 | 半導体集積回路 |
| US8102663B2 (en) * | 2007-09-28 | 2012-01-24 | Oracle America, Inc. | Proximity communication package for processor, cache and memory |
| CN101320707B (zh) * | 2008-05-19 | 2010-06-09 | 深圳市国微电子股份有限公司 | 结构化专用集成电路设置和生产方法 |
| US7800936B2 (en) | 2008-07-07 | 2010-09-21 | Lsi Logic Corporation | Latch-based random access memory |
| EP2159799A1 (en) | 2008-08-27 | 2010-03-03 | Panasonic Corporation | Semiconductor memory with shared global busses for reconfigurable logic device |
| JP5401699B2 (ja) * | 2008-09-18 | 2014-01-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR101047059B1 (ko) | 2009-10-30 | 2011-07-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
-
2012
- 2012-11-19 US US13/680,530 patent/US8902625B2/en active Active
- 2012-11-21 JP JP2014542589A patent/JP6257044B2/ja not_active Expired - Fee Related
- 2012-11-21 CN CN201280057348.3A patent/CN103946848B/zh not_active Expired - Fee Related
- 2012-11-21 WO PCT/US2012/066236 patent/WO2013078294A2/en not_active Ceased
- 2012-11-22 TW TW101143703A patent/TWI616764B/zh not_active IP Right Cessation
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