JP2015502660A5 - - Google Patents

Download PDF

Info

Publication number
JP2015502660A5
JP2015502660A5 JP2014542589A JP2014542589A JP2015502660A5 JP 2015502660 A5 JP2015502660 A5 JP 2015502660A5 JP 2014542589 A JP2014542589 A JP 2014542589A JP 2014542589 A JP2014542589 A JP 2014542589A JP 2015502660 A5 JP2015502660 A5 JP 2015502660A5
Authority
JP
Japan
Prior art keywords
memory
circuits
circuit
logic
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2014542589A
Other languages
English (en)
Japanese (ja)
Other versions
JP6257044B2 (ja
JP2015502660A (ja
Filing date
Publication date
Priority claimed from US13/680,530 external-priority patent/US8902625B2/en
Application filed filed Critical
Publication of JP2015502660A publication Critical patent/JP2015502660A/ja
Publication of JP2015502660A5 publication Critical patent/JP2015502660A5/ja
Application granted granted Critical
Publication of JP6257044B2 publication Critical patent/JP6257044B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2014542589A 2011-11-22 2012-11-21 システムオンチップ内のメモリ回路および論理回路のレイアウト Expired - Fee Related JP6257044B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161563001P 2011-11-22 2011-11-22
US61/563,001 2011-11-22
US13/680,530 US8902625B2 (en) 2011-11-22 2012-11-19 Layouts for memory and logic circuits in a system-on-chip
US13/680,530 2012-11-19
PCT/US2012/066236 WO2013078294A2 (en) 2011-11-22 2012-11-21 Layouts for memory and logic circuits in a system-on-chip

Publications (3)

Publication Number Publication Date
JP2015502660A JP2015502660A (ja) 2015-01-22
JP2015502660A5 true JP2015502660A5 (cg-RX-API-DMAC7.html) 2016-01-07
JP6257044B2 JP6257044B2 (ja) 2018-01-10

Family

ID=48426797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014542589A Expired - Fee Related JP6257044B2 (ja) 2011-11-22 2012-11-21 システムオンチップ内のメモリ回路および論理回路のレイアウト

Country Status (5)

Country Link
US (1) US8902625B2 (cg-RX-API-DMAC7.html)
JP (1) JP6257044B2 (cg-RX-API-DMAC7.html)
CN (1) CN103946848B (cg-RX-API-DMAC7.html)
TW (1) TWI616764B (cg-RX-API-DMAC7.html)
WO (1) WO2013078294A2 (cg-RX-API-DMAC7.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5956964B2 (ja) * 2013-08-30 2016-07-27 株式会社東芝 半導体装置
TWI576852B (zh) * 2015-06-30 2017-04-01 宏碁股份有限公司 電子裝置及其固態硬碟的電源管理方法
CN105319964B (zh) * 2015-09-29 2018-06-22 上海新跃仪表厂 基于配置文件的运载火箭测试发射流程生成方法及系统
US11392748B2 (en) * 2018-09-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design using fuzzy machine learning
DE102019124928A1 (de) 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes schaltungsdesign unter verwendung von fuzzy-maschinenlernen
US12314116B2 (en) 2020-07-31 2025-05-27 Qualcomm Incorporated Systems and methods for adaptive power multiplexing

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW231343B (cg-RX-API-DMAC7.html) * 1992-03-17 1994-10-01 Hitachi Seisakusyo Kk
US5657284A (en) * 1995-09-19 1997-08-12 Micron Technology, Inc. Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices
US5767565A (en) 1996-07-22 1998-06-16 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US5892703A (en) 1997-06-13 1999-04-06 Micron Technology, Inc, Memory architecture and decoder addressing
US6605962B2 (en) * 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
JP2003037173A (ja) * 2001-07-23 2003-02-07 Niigata Seimitsu Kk アナログ・デジタル混載集積回路
TW525184B (en) * 2001-08-17 2003-03-21 High Connector Density Inc Stackable modules with clustered connections
US6717430B2 (en) * 2002-02-13 2004-04-06 Motorola, Inc. Integrated circuit testing with a visual indicator
US6687147B2 (en) * 2002-04-02 2004-02-03 Hewlett-Packard Development Company, L.P. Cubic memory array with diagonal select lines
TW594991B (en) * 2003-04-29 2004-06-21 Faraday Tech Corp Integrated circuit with one metal layer for programming functionality of a logic operation module
US8463996B2 (en) * 2003-08-19 2013-06-11 Oracle America, Inc. Multi-core multi-thread processor crossbar architecture
US20050044320A1 (en) * 2003-08-19 2005-02-24 Sun Microsystems, Inc. Cache bank interface unit
JP2006156929A (ja) * 2004-04-19 2006-06-15 Fujitsu Ltd 半導体集積回路及びその設計方法
JP2006099719A (ja) * 2004-08-30 2006-04-13 Sanyo Electric Co Ltd 処理装置
US20060143384A1 (en) * 2004-12-27 2006-06-29 Hughes Christopher J System and method for non-uniform cache in a multi-core processor
US7353162B2 (en) * 2005-02-11 2008-04-01 S2C, Inc. Scalable reconfigurable prototyping system and method
JP2006323643A (ja) * 2005-05-19 2006-11-30 Nec Electronics Corp 半導体集積回路のフロアプラン設計プログラム、フロアプラン設計装置、および設計方法
JP2006324471A (ja) * 2005-05-19 2006-11-30 Toshiba Corp 半導体集積回路装置
TW200743976A (en) * 2006-05-19 2007-12-01 Nat Applied Res Lab Nat Chip Implementation Ct Multi-project System-on-Chip platform and the design method thereof
KR101297754B1 (ko) 2006-07-11 2013-08-26 삼성전자주식회사 메모리 컴파일링 시스템 및 컴파일링 방법
JP4951786B2 (ja) * 2007-05-10 2012-06-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5528662B2 (ja) * 2007-09-18 2014-06-25 ソニー株式会社 半導体集積回路
US8102663B2 (en) * 2007-09-28 2012-01-24 Oracle America, Inc. Proximity communication package for processor, cache and memory
CN101320707B (zh) * 2008-05-19 2010-06-09 深圳市国微电子股份有限公司 结构化专用集成电路设置和生产方法
US7800936B2 (en) 2008-07-07 2010-09-21 Lsi Logic Corporation Latch-based random access memory
EP2159799A1 (en) 2008-08-27 2010-03-03 Panasonic Corporation Semiconductor memory with shared global busses for reconfigurable logic device
JP5401699B2 (ja) * 2008-09-18 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置
KR101047059B1 (ko) 2009-10-30 2011-07-06 주식회사 하이닉스반도체 반도체 메모리 장치

Similar Documents

Publication Publication Date Title
US11687454B2 (en) Memory circuit and cache circuit configuration
JP2015502660A5 (cg-RX-API-DMAC7.html)
US20170125360A1 (en) Semiconductor device including three-dimensional crack detection structure
US20180262198A1 (en) Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
US20150242308A1 (en) Acceleration system in 3d die-stacked dram
JP2009545095A5 (cg-RX-API-DMAC7.html)
WO2013078294A4 (en) Layouts for memory and logic circuits in a system-on-chip
KR20110135299A (ko) 반도체 메모리 장치
WO2010079448A3 (en) System, method and apparatus for memory with control logic to control associative computations
JP2005512229A5 (cg-RX-API-DMAC7.html)
US8817547B2 (en) Apparatuses and methods for unit identification in a master/slave memory stack
US20150199150A1 (en) Performing Logical Operations in a Memory
JP2015529929A5 (cg-RX-API-DMAC7.html)
US9171849B2 (en) Three dimensional dual-port bit cell and method of using same
JPH03123071A (ja) ダイナミックram
US9639649B2 (en) Semiconductor memory device, method for designing semiconductor memory device, and recording medium having designing method recorded therein
KR20120133137A (ko) 반도체 소자의 제조 방법
US9583494B2 (en) Apparatus and method for integrated circuit bit line sharing
US10020030B2 (en) Semiconductor apparatus capable of improving efficiency for a circuit configuration and a signal line interconnection
JP2021099891A (ja) ワイドプリフェッチを行う高帯域幅dramメモリ
US12505060B2 (en) Method to select phys and a configuration of the data path in a multi PHY DRAM
US12520495B2 (en) 3D NAND with IO contacts in isolation trench
US9459672B2 (en) Capacitance management
JPH11163297A (ja) 半導体メモリ
JP2012129337A5 (cg-RX-API-DMAC7.html)