JP6257044B2 - システムオンチップ内のメモリ回路および論理回路のレイアウト - Google Patents

システムオンチップ内のメモリ回路および論理回路のレイアウト Download PDF

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Publication number
JP6257044B2
JP6257044B2 JP2014542589A JP2014542589A JP6257044B2 JP 6257044 B2 JP6257044 B2 JP 6257044B2 JP 2014542589 A JP2014542589 A JP 2014542589A JP 2014542589 A JP2014542589 A JP 2014542589A JP 6257044 B2 JP6257044 B2 JP 6257044B2
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memory
circuits
logic
circuit
memory circuits
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Japanese (ja)
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JP2015502660A5 (cg-RX-API-DMAC7.html
JP2015502660A (ja
Inventor
ホルト、ジョセフ
メイダー、ロイ
グレイナー、ブランドン
ビー． アンダーソン、スコット
ビー． アンダーソン、スコット
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マーベル ワールド トレード リミテッド
マーベル ワールド トレード リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
JP2014542589A 2011-11-22 2012-11-21 システムオンチップ内のメモリ回路および論理回路のレイアウト Expired - Fee Related JP6257044B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161563001P 2011-11-22 2011-11-22
US61/563,001 2011-11-22
US13/680,530 US8902625B2 (en) 2011-11-22 2012-11-19 Layouts for memory and logic circuits in a system-on-chip
US13/680,530 2012-11-19
PCT/US2012/066236 WO2013078294A2 (en) 2011-11-22 2012-11-21 Layouts for memory and logic circuits in a system-on-chip

Publications (3)

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JP2015502660A JP2015502660A (ja) 2015-01-22
JP2015502660A5 JP2015502660A5 (cg-RX-API-DMAC7.html) 2016-01-07
JP6257044B2 true JP6257044B2 (ja) 2018-01-10

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JP2014542589A Expired - Fee Related JP6257044B2 (ja) 2011-11-22 2012-11-21 システムオンチップ内のメモリ回路および論理回路のレイアウト

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Country Link
US (1) US8902625B2 (cg-RX-API-DMAC7.html)
JP (1) JP6257044B2 (cg-RX-API-DMAC7.html)
CN (1) CN103946848B (cg-RX-API-DMAC7.html)
TW (1) TWI616764B (cg-RX-API-DMAC7.html)
WO (1) WO2013078294A2 (cg-RX-API-DMAC7.html)

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TWI576852B (zh) * 2015-06-30 2017-04-01 宏碁股份有限公司 電子裝置及其固態硬碟的電源管理方法
CN105319964B (zh) * 2015-09-29 2018-06-22 上海新跃仪表厂 基于配置文件的运载火箭测试发射流程生成方法及系统
US11392748B2 (en) * 2018-09-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design using fuzzy machine learning
DE102019124928A1 (de) 2018-09-28 2020-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes schaltungsdesign unter verwendung von fuzzy-maschinenlernen
US12314116B2 (en) 2020-07-31 2025-05-27 Qualcomm Incorporated Systems and methods for adaptive power multiplexing

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JP2006099719A (ja) * 2004-08-30 2006-04-13 Sanyo Electric Co Ltd 処理装置
US20060143384A1 (en) * 2004-12-27 2006-06-29 Hughes Christopher J System and method for non-uniform cache in a multi-core processor
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JP5528662B2 (ja) * 2007-09-18 2014-06-25 ソニー株式会社 半導体集積回路
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Also Published As

Publication number Publication date
WO2013078294A3 (en) 2013-07-18
CN103946848B (zh) 2017-04-12
US20130128648A1 (en) 2013-05-23
WO2013078294A4 (en) 2013-09-06
TW201324221A (zh) 2013-06-16
TWI616764B (zh) 2018-03-01
US8902625B2 (en) 2014-12-02
JP2015502660A (ja) 2015-01-22
WO2013078294A2 (en) 2013-05-30
CN103946848A (zh) 2014-07-23

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