TW525184B - Stackable modules with clustered connections - Google Patents

Abstract

The present invention provides a method for improving the performance of high speed, impedance-controlled bussed data subsystems through the reduction of the data path lengths between high speed semiconductor devices such as high speed control elements (e.g., memory controllers, small computer system interface (SCSI) drivers, peripheral component interconnect (PCI) chipsets and bridges and their intended target devices on the channel (e.g., SDRAM, DDR SDRAM, RAMBUS, FLASH, static RAM, SCSI drives, PCI devices, I/O cards and mezzanines), and an optimized electronic package for interconnecting the devices. The clustered shape and relatively centered placement of the interconnection pads on the circuit members in the electronic package, as well as the potential stacking of multiple circuit members, further enhance the performance and reduce costs.

Description

525184 V. Description of the invention (1) [Related patent applications] This patent application is related to US Patent No. 6, 1 72, 895 and was proposed by Brown et al. As "High-speed memory with built-in high-speed bus terminal" "Module" "U.S. Patent Application No. 0 9/457, 776, filed on December 9, 1999, and U.S. Patent Application No. 09 / 645,860, 009 /, filed on August 24, 2000 645,859,09 / 6,45,858. 200 US Patent Application No. 09/774, 857 filed January 31, 2001; 200 US Patent Application No. 09/775, 99 1; 200 filed on February 5, 2001 U.S. Patent Application No. 09/835, 1 23,200 filed on February 26, 2001 U.S. Patent Application Nos. 09/835, 123, and April 20, 2001 filed on May 29, 2001 ^ U.S. Patent Application No. 09/866, 434, among the above patents, is hereby designated as a reference for this patent. [Invention category] The present invention relates to an electrical connection of a semiconductor device with a high-speed, bus data path, and more particularly, a double data rate (DDR) synchronous dynamic random access memory (SDRAM) and Memory devices such as RAMBUS ® devices for high-speed bus data. [Background of the Invention] Nowadays, diversified software executes one or two daggers on high-speed digital computing devices: more dynamic random access memory before or earlier: access memory such as _SDMM. But as the speed of capital equipment in the system increases, the real-life configuration of various interconnected parts becomes very important. Today's personal computers are two models:

525184 V. Description of the invention (2) Interconnection group among many devices such as microprocessor and memory controller 5 2 The array in the breaking zone 5 is interconnected. In some cases, the interconnection is connected via two (for example, permanent grid amy (PGA) technology of baU KM (BGA) technology), and the WV grid array (Pin grid ^ ^ ^^) is separated; nV ； " 'Vh V | £ ^ ^ ^ The group is a rectangle with a rectangular shape] :: == describes the linear array contacts on both sides of the memory module in a personal computer: η The length of the bottom edge of the group depends on the situation # a ΰ + ”to connect. Although the size of the memory module is

Guanyi: It is: the number of contact points of square r is small, and the chip technology changes. The external view is about s i f. A current applicable DDR SDRAM module measures J approximately 5.25 inches long or 15 inches high according to the direction of the system order and the timing memory bus cycle is far away (for example, the memory controller times V ;; J ( Such as the most memorable ginger, body device) and the most delayed impact from it. So the worst case transmission is SDRAM, EDO RAM, and FUSiH, the second memory system (such as M & FLASH) In this case, the memory cycle and the path length between the data are very important. Πΐί ;: 'Bit length minus the shortest path length of the clock source will affect the plastic-to-sin ratio, and will be affected by the shortest of the data _Long production = this f ^ 枓 holding time (affected by the largest change in hold degree ... minus the longest path length of the clock source in any special memory-based memory cycle, the setting time

Page 7 525184 V. Description of the invention (3) J 2: There will be a fixed basic value in order to calculate the extension of the length of the electrical path between the clock and the data in the future. This is the so-called two. PCB) skew. The door and brackets of the vehicle are covered. The time and holding time must be extended to accumulate future factors such as jitter and changes caused by the system, such as * a, Urine "breadth and the fastest exchange rate of the power supply are selected as β ^. The bus-based system N ~ month and output are mainly set by the support device at the set time under the change of the length of all the strip paths And holding = Changzhi's sister 3. Therefore, for SDRAM, the data length is more useful: the t path and the length of the lean material can provide a significant contribution to the required timing and output in this design. "The designers of the Zixie Coffee Memory Subsystem have tried to measure each strobe memory device by strobe signals along 蜮 轸 2; For data from each memory device to the clock, the flash control is used like the local clock. When the length of the flash control signal and the configuration of the bathroom control device will send out a clock ’, and since the flash control signal also needs to encounter two = of it! Process and temperature conditions ... This is a very effective factor that has been used to eliminate the printed circuit board skew factor described in this article. This is the output bottleneck of the shared clock infrastructure system. This data can have infinite output. Designers adopt the < Examination Source Synchronous Design. This design strategy has become very common in high-speed convergence architectures in recent years. No matter there are many reasons in the world, the source synchronization design does not show infinite output and it has become a problematic architecture in high-speed and high-efficiency bus design. Even more, the architecture has a longer bus path

Page 8 525184 ⑷ becomes more difficult to achieve. In source synchronization design, the length matching between the data line and the flash control signal needs to be an important length for the data line. Because the data can no longer be routed directly to its destination, it must be moved back to a more remote and bowl-shaped route to match the length of the data lines and flash control signals on other buses. This final length matching path requires most of the actual space on the board. It is particularly obvious in the design of the conventional dual-row memory module (D IMM). In addition, at present, it is necessary to reduce inter-trace crosstalk and minimize the effect of impedance change in high-speed designs. This means that these paths need a larger path interval to meet the overall signal needs to counteract Reduced noise boundary. The internal path configured in a meandering manner to match the length of the external path will be more difficult to complete without more printed circuit board space for arranging those paths. Also, adjusting the paths in any particular internal serpentine section requires a certain amount of space to minimize self-inductive crosstalk and thereby maintain the integrity of all signal paths. These two effects reinforce each other in the length matching phase design. There is an example of a length matching bus in the conventional DIMM-based memory system. 'The longest path length between two points of three inches needs five to five Lu Liuying's circuit. The shortest path length between the two points of one inch also requires five to six inches of circuitry. Of course, as long as the actual space required for the length matching is sufficient, the skew of the printed circuit board can be reduced to greatly improve the bus setting and holding time, which will make it possible to design based on higher speed buses.

$ 9Page 525184 V. Description of the invention (5) In addition, the effects of the second and third orders such as impedance, process and temperature change, reflection, ringing, ringback, skin effect ( ski n effect), non-linear phase changes, inter-symbol interference (ISI), false triggering, ground bounce, non-ideal return paths, and crosstalk can no longer be ignored. Because of these second- and third-order effects, source-synchronous architectures (such as DDR SDRAM) will quickly enter many design limitations or even performance bottlenecks. Any architecture that can reduce the length of the signal path and strive to design to accommodate these effects has a better opportunity at higher speeds. Because = any; can reduce this worst case, and reduce the average of the electrical path length of the data line and data control U will greatly improve the effectiveness of the system ^ control the improvement of the above problem is to provide a region The arrays have the advantages of this improvement, the placement of the memory modules. This allows the BGA-connected memory 1 and 2 to be closer to the memory module and the worst case D is low. ~ The length of the chanting can be greatly reduced. In order to further improve the performance of the memory subsystem, and to minimize the data line on the memory module and the central position of the data set, various memory devices and areas; -: The solution is to change the memory module area 2 to a memory module that is different from the conventional technology. The memory module has a long square shape and is turned outward. The other is to make the performance of the memory subsystem more prolonged.

Page 10 525184 V. Description of the invention (6) The Brother Brothers system has a large number of memory devices, which are stacked on top of the first memory module to increase the number of memory modules. Connect them together. Compared with the configuration methods used in today's personal computers, for example, four memory modules, each approximately 5.25 inches long and 1.5 inches high and each having 0.5 inch inches on the motherboard Distance, stacked memory modules provide significant performance improvements and other advantages. These advantages include: because only the first memory module in the stack needs to be routed, the wiring of the motherboard can be simplified; reducing the overall signal attenuation caused by reflections caused by signal travel between the motherboard and the memory modules; and Many parts of the motherboard and signal path have almost no high frequency coupling noise. < Because the module of the present invention can make the modules closer to each other by stacking configuration (for example, 'only 3 fflnl distance in one case), compared with the case of a single memory module, it will only increase a very small transmission delay . The improved brother memory module system also provides the advantage of significantly reducing the actual space used by the system board. In the conventional technology using four memory modules, the space used is 20 square inches, which will be reduced to 4 square inches after using the configuration of the present invention. Therefore, the 9 newer memory modules will be packaged to the same height as a memory module of the conventional technology.

The above-mentioned improvements not only save space and reduce the complexity between the system board and the memory module due to the reduction of the wiring length4, but also reduce many worst-case transfer delays, resulting in many possible improvements in the memory subsystem. Many different improvements and structures are interdependent. For example, in many secondary systems based on bus j, the change between path impedance and system characteristic impedance ′ (characteristic impedance) will determine each:

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The reflection of the matching section has a large b # μ length, which must take a longer J2 voltage level. For longer paths, it is very likely to remember huihui :: 旎 to reach steady state. For high-speed busbars, the steady-state voltage has not been reached; the setting in the body === grid is locked or flashed. The concept of incorrect address / control or clustered area array interconnection in the hidden body also allows for the inclusion of different / lower: modules and modules in the stack are shared with the memory modules of the memory device, and item 5 The area arrays are interconnected. Similarly, the same area array interconnects on the system board can also be shared. This is similar to the situation in today's personal computers when the memory is upgraded. The advantages of this concept include simplifying the design of system boards and memory modules, and reducing the need for R & D testing and the limitations of new products. This means that when the newly designed memory module is implemented, the reliability and performance limitations need not be repeated. For other memory technologies, it may be better to place the interconnect and the memory device with a one-bit difference from the DDR memory. For example, for RAMBUS-based memory modules, it may be better to divide the interconnect into two or more smaller parts. Centrally configure the area array (but does not need a center point) and then optimize the Place the memory device. For DDR memory sub-systems, even DDR memory specifications need additional terminations at both ends. 'If the rise time of an electrical path length relative to the required transmission delay through the path is short enough, follow the shorter path The reflected ringing period can be low, so that the second terminal can be saved, thus simplifying and reducing the cost of the memory subsystem. No need for a second terminal. The secondary system used can be electrically modularized into an integrated

Page 12 525184 Description of the invention (8) The degree of lumped or distributed depends on the degree. In practice, this is controlled by the length of the electrical path and the edge rate of the signal as it passes through the path. Shorter path lengths and lower edge rates make the secondary systems used more integrated and less decentralized. The defined lines of a decentralized system are usually regarded as electrical degrees greater than one-sixth the edge rate. So just because a system is decentralized by this criterion, if the electrical path length is short enough, only one terminal can replace two terminals to preserve the integrity of the signal. Other memory technologies that use transmission-saving ways to increase and / or reduce costs, and other memory technologies, will be apparent in this technology. When increasing the path length, the transmission line effect becomes more decisive. As long as the characteristic impedance between a system board and a memory module is 10% mismatch, it is 1 inch compared to all path lengths. All paths with a length of 3 or 4 pairs will have a significant ringing period (overshoot and undershoot) period. The ringing period and the set time can be scaled by the path length. Even in the future, it can be expected that it will become more difficult to settle the signal at one hundredth of the final value at a higher frequency 'within the time allowed by the clock cycle. In one example, a memory chip placed 4 inches away from the controller will receive this signal after about 72 pS (180 pS per inch in FR4). The first three reflected signals will be received sequentially from the source at approximately 2160 pS, 3600 pS, and 5040 pS. 〇 It becomes more urgent that the reflected signal round-trip time (ronundtrip) and the clock cycle will become comparable, so the driver will be within one clock cycle

525184 V. Description of the invention (9) Sending logic "1" on the data path can decide to send logic "0" in the next clock cycle, but the signal reflected from the original "1" will exist on the line depending on the lack, which may disturb The driver is trying to transmit the noise edge and boundary of “〇”. In addition, if the drive tries to transmit "1" again in the next clock cycle, this will enhance the reflection from the previous week or even be reflected later. The first reflection can come back as soon as the drive is switching. A drive When switching states, it passes its maximum power usage. If the signal reflected from all long-production matching lines returns when the driver switches states, and its electrical level is enhanced by the driver, this situation will easily increase power consumption and ( Reduce the life of the memory controller. Even worse, if the boosted voltage level output of the driver results in a bounce on the supplied voltage for a long enough time, a typical CMOS-based device driver, If its input / output driver is in contact with the power supply or ground for a long enough period of time, it may be sensitive to lockout. P Wen Fuping 乂

For non- = memory devices, when their supply voltage enters the boundary of the signal, the control signal line will ring too much, causing errors, or avoiding errors or address / control / data signal line is more urgent (critiCa " The second clock of the foot position will become more and more significant. In the system: the t-direction rate (siew rate) increases. The plane of the source appears like a ground pressure and The voltage level and response of different electric lines-drive 525184 V. Description of the invention 1 ~~-A three-dimensional topographic map of the dynamic changes of the shape of the dynamic conditions. In this way, reducing the electrical path length of the signal line may also increase the signal The degree of electrical integration. The clock frequency continues to increase, not only the length matching becomes tighter, but also the electrical loss and the resistance loss caused by the skin effect will make the current memory module design more difficult in the path length. Tolerance, because the signal's attenuation loss factor (factor) along the signal path decreases as the noise boundary decreases ^ This result will be particularly obvious in the design of longer buses such as high-density RAMBUS form, The streamer must be operated along a long, air path and a capacitive signal load path with a higher clock rate with a signal path with an attenuation loss factor of three to seven percent typical. _ — At higher frequencies (For example, greater than GHz) Printed circuit boards are no longer treated as fixed impedance transmission lines and exhibit linear phase changes, so other effects will become more significant. 'It will replace frequency-dependent resistance and will exhibit a frequency-dependent nonlinear phase change. This is due to the increase in channel conductance of higher frequency parts. There are two effects on high frequency signals worth noting. First, no longer, it may be possible to treat circuit = impedance as a frequency-dependent resistor and use a single resistor to It should be used to match the path impedance of the parts with relatively high frequency. The matching network composed of a plurality of resistors and capacitors is approaching to the path impedance of the higher frequency channel. This appeal is similar to the design of high resolution, low frequency The MX plane, voice mail system, and seismology of the matching network will be similar to the technology included in this case. The first plant, because the frequency varies depending on the phase Digital transmission signal in common wave pulse (Pulse) by a pulse-shaped channel, changing their outer

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Because of these high-frequency effects, length becomes more beneficial. The present invention combines better spatial solutions to improve many emergency designs. High-frequency digital signal transmission technology that will reduce the channel will appear cleverly different parameters and execution efficiency, to establish a cluster area array interconnect in the memory system of the present invention also provides a significant improvement on board. All printed circuit boards have a fixed warp on two planes. A printed circuit board has a typical characteristic of thousands of warp changes per inch or width. Warp warps make it more difficult to use all contacts reliably with low volume or contact force in any area array connector. . By maintaining interconnections in many smaller areas, the warp effect can be minimized. For land grid array (LGA) connectors and clamps, this will simplify design requirements and reduce size and / or cost. Interconnecting 'clusters for soldering connectors such as ball grid array (BGA) and column grid array (CGA) and surface-adhered pGA connectors also provide improved stability of the mechanism. This is due to the reduced distance from the neutral point (DNP), which can minimize the instability of the mechanism caused by the mismatch of the coefficient of thermal expansion (CTE). In addition, productivity is increased because non-planarity is less than corners in a smaller area. The above-discussed ideas can be used in many applications and requirements, so 'can be implemented in more diverse electronic packages. Some influences achieved

525184 V. Description of the invention (12) The parameters for the decision are the number of stages required for stability, the separation of the required site, the size of the package, the specific chip technology or technology, the speed of the bus, the number of devices to be interconnected, and mass production factors. And costs. These parameters affect many items including the interconnection method from the package to the system board, the interconnection method inside the package, the use of materials, the number and complexity of circuit components required, the method of clamping and cooling, and so on. For example, the interconnection method from the package to the system board and inside the package is application specific. It may be combined with soldering, PGA, LGA. For a preferred example of an LGA connector and clamp, refer to some of the aforementioned U.S. patent applications. Therefore, one object of the present invention is to enhance the technology of the high-speed, bus data subsystem. Another object of the present invention is to provide a high-speed module, which has a bus array device that is interconnected to a cluster array contact of a system board and allows additional modules to be stacked with the same contacts as the original when the signals are properly arranged. It is still another object of the present invention that the above-mentioned module and a system board are at least separated. Another object of the present invention is to provide the module with a low profile. Another object of the present invention is that the device of the above-mentioned module can also operate stably when the temperature increases. Another object of the present invention is to improve the performance of the mechanism provided by the module. [Overview of Invention]

1. ^ I provides a method for improving high-speed performance by controlling the impedance bus data subsystem by reducing the lean path length of the same-speed conductor devices such as memory controllers and DDR SDRAM and RAMBUS devices, and A 525184 V. Description of the invention (13) Optimized electrons for the interconnection of memory devices. The interconnection points of the circuit components in the assembly are placed in a centralized manner for efficiency and cost reduction. And the position of the son is even more enhanced. The improved memory space is 4 i ^ ^ space. In addition, Fong Lu has greatly reduced the real use of system boards ’to simplify the design requirements and reduce the minimum product size and / or u of any pinch effect. Connector clips * Some packaged parts on the use side may be changed according to the specific purpose. The methods, materials used, and the interconnections required in the package are carefully considered. The number and complexity of circuit components The method of cooling. For example, from 1 array pattern, and clamps and two, for example, from the system board to the packaging and packaging method can be a combination of BGA, PGA and LGA. [Brief description of the drawings] In order to make the reviewing committee better understand the structure and characteristics of the present invention, the drawings and detailed descriptions of the preferred embodiments are attached. Schematic diagram of a bus device and a plurality of memory modules interconnected in a memory system arrangement; Figure 2 is a bus interconnection between a memory controller device and an area array contact of a target device. Bottom view; Figure 3a is a centralized configuration of circuit element area array contact interconnections of a memory system based on a DDR SDRAM, one of the preferred embodiments of the present invention. (14) Top view. Figure 3b is a top view of another configuration of the DDR in a preferred embodiment of the present invention in 3a; SDRAM-based memory sub-system, another configuration of the circuit element area array contacts interconnection 9 views 3c is a sectional view. FIG. 5 is an enlarged side view of the complex circuit element in the preferred embodiment of FIG. 3a. Figure 3d is a cross-sectional view which is a side view of the preferred embodiment of Figure 3c. Other devices are provided to provide additional functions. Figure 4a is a circuit element area of a RAMBUS-based memory win system according to a preferred embodiment of the present invention. Top view of the centralized configuration of the array contact interconnection after modification. Figure 9b is a top view of the plurality of circuit elements in the preferred embodiment of Figure 4a being more closely combined. Figure 4c is a better view according to Figure 4a. One embodiment of the RAMBUS-based memory sub-system. The top view of the centralized arrangement of the circuit element area array contact interconnections after correction is modified. Figure 4d is a cross-sectional view that expands the complex number in the preferred embodiment of Figure 4a. Side view of each circuit element> Fig. 4e shows the way of the RAMBUS channel in the preferred embodiment of Fig. 4d Figure _ Intention 1 Figure 4f shows another top view of the RAMBUS basic memory sub-system in the preferred embodiment of Figures 4a to 4c; and Figure 4g shows the preferred embodiment of Figure 4f Top view of another configuration of the RAMBUS base memory sub-system.

Page 19 525184 Description of the invention (15) [Detailed description of the preferred embodiment]: Generally, the present invention provides a method for improving high-speed performance by reducing the speed of a semiconductor device such as a high-speed control device such as a memory Controller 'Small Computer System Interface (SCS 丨) Driver, Peripheral Device (PCI) Interconnect Chipset and Bridge and Target Device on its Channel (eg SDRAM, DDR SDRAM, RAMBUS, FLASH, SRAM, SCSI Driver' PC I device 'I / o card, etc.), and an optimized electronic package for device interconnection. The cluster shape and the interconnection of circuit component interconnection points in the electronic package are placed in a centralized manner' and multiple when the number of devices is guaranteed The position of circuit components when stacked on each other, enhances execution efficiency and reduces costs. The plurality of circuit components can make the cost-effective printed circuit board line width and space to form a commonly known printed circuit card. The printed circuit board A device with a package or unpackage is directly attached to a plurality of circuit elements, and is more likely to include a = selective bus terminal. The package can also be Contains clamp device, thermal management structure, and device for aligning lines when needed. Refer to Figure 1 'It shows the memory sub-system in the conventional technique. 丨 On the system board 12, it contains a memory. Schematic diagram of the bus interconnects between the controller 14 and a plurality of memories f. In this example, although there are two or two other technologies that can be applied, the memory subsystem 10 is based on DDR SDRAM technology. 圮The memory controller 4 is connected to the memory modules 16a-16d via a plurality of bus interconnects, where each memory is composed of a plurality of memory devices 28. In order to provide higher density ^ 雨 Ϊ ίMemory The device 28 can be placed on the memory module 16a] 6d and stacked on one or both sides. This type of stacking is

Page 20 525184 V. Description of the invention (16) There are costs, but they are not reliable and difficult to repeat. In addition, it is very difficult for such stacked devices to dissipate heat. The memory controller 14 is connected to the system board 12 via a BGA solder joint 20 (shown in FIG. 2) at the bottom 22 thereof. The length “M” of the memory controller 14 is about 1 inch, which makes the size of the device about 1 square inch. The memory modules 16a-16d are about 5.25 inches long and 1.5 inches high Modules 16a-16d have a P distance of 0 · 5 夬 忖. Contacts 2 4 are provided along the lower edges of the modules 16a to 16d. The contacts 24 are provided via an edge connector The electrical connection of the system board 12 is not shown in the figure and will not be described in detail. Memory modules 1 6 a -1 6 d are typically printed circuit structures made of epoxy_glass-based (epoxy) -glass-based) material (for example, FR4) and contains one or more conductive layers (for example, signal, power, and / or ground). Because of strict electrical specifications, the impedance of the signal path must be the same as that of the system board 1 The impedance of the corresponding path on 2 is matched, and the error can only be within 10%. The distance "W" between each memory controller 14 and the first memory module 16a is provided in plural. Bus interconnects i8a-18 (1 The area connected to them. Due to the memory technology requirements, most of the multiple bus interconnects 18a-18d Must be within 0.1 inch. This will result in a lot of inefficient wiring. So although it seems that the interconnect 18a will be directly connected from the memory controller " memory 14 " to the central contact 24 of the memory module 16a , But additional length must be added to match the longer path of interconnect 18b, especially 18c and 18d. This additional wiring will cause the distance "w ,," to increase, from an optimal ^ English leaf to a more practical 3 In the case of British time, 3 Ge has 36 /

525184 V. Description of the invention (π) Transmission delay. The total area required on the system board 12 for the memory controller 14 and the memory module group 16 a interconnect 1 8 a-18 d is about 20 square inches. The matching of the interconnection length between the memory modules 16a to 16d will also occur, which will increase the transmission delay and wiring conflicts. It must be understood that when the frequency is constantly increasing, the length matching of interconnects 18a-18d does not guarantee the normal function of the bus system. This is due to the longer path length along many of the other electrical effects described above. Please refer to FIG. 2 ′, which shows the memory sub-system 3 according to the present invention. The areas between the memory controller 14 and the target memory device 28 (FIG. 3 a) (area array interconnection points 3 and 2 partial buses) Bottom view of the interconnect. The concepts mentioned in the figure can be applied not only to DDR SDRAM, but also to all forms of bus interconnects. The memory controller 4 is interconnected by a plurality of buses 34a-34c Connected to the memory device 28 (Fig. 3a). The memory controller 14 is connected to the system board 12 via an array of BGA solder joints 20 on its bottom 22. The length "μ" of the memory controller 4 is about 1 inch, The size of the device is about 1 square inch. In this case, the length "c" of the area array interconnection point 32 is the same as the length of the memory controller 4. The area array interconnection point 32 is from the system board 12 Many connection methods are allowed to a plurality of circuit elements 36, 38, ^ (Fig. 3c). Including BGA solder joint attachment, pGa attachment and LGA attachment, all possible choices depend on specific design requirements. "Memory Controller The distance between 14 and the area array interconnection point 32 is provided by X Multiple bus interconnects 34a-34c and the area they connect to On page 22, 525184 V. Description of the invention (18) In the case of a single memory module, the worst case of path length is reduced from 2.91 inches to 1.34 inches, which can reduce the dielectric properties in FR4. The path flight time of 283 pS (time -1 0-f 1 y), and in the case of four memory modules, the worst case of path length is even reduced from 3.78 inches to 1.94 inches, This can reduce the path flight time of 349 pS in the FR4 dielectric. Reducing the bus path length can reduce the signal transmission delay, so the data output rate can be increased. It can also reduce the cycle time of the line reflection and adjacent signals The number of far-end crosstalk between the lines, so as to protect the integrity of the signal when working at high frequencies. In addition, it can also simplify the requirements of the terminal. The reduction of the terminal requirements and the actual space used for wiring can also reduce all systems Cost. Following The description will describe that this concept can also reduce the interconnection length between a plurality of circuit elements 36, 38, 40 (FIG. 3c). Referring to FIG. 3a, a memory subsystem according to a preferred embodiment of the present invention is shown. 30, which includes a top view of a memory controller 14 and a circuit element ° 36, and a centralized configuration of the area array interconnection points 32 of the circuit element 36 in the memory sub-system 30 based on DDR SDRAM. Π At least A plurality of memory devices are included in the-surface, and it can be seen that the j memory devices 28 and the area array interconnection point 32 are close to the same distance, so the wiring distance between the memory device 28 and the worst case interval can be greatly reduced. According to Li M 9 Yi: J interconnection point 32 < specific implementation of the connection and the circuit element and circuit element 36 can be placed in more connections than shown in Figure 3, ^ = 疋 'memory controller 14 connection point 32 Office. Area array mutual closer to circuit element 36. Memory controller 14 and area array interconnection point 3 2 Other suitable configurations

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The system board 12 is typically a printed circuit board structure composed of an epoxy-glass-based (ePoxy-glass-based) material (for example, FR4) and its contacts can also be used. For example, 'As long as there is a large space between the area array interconnection points 32 of the memory device 28 and the circuit element 36, the memory device 28 can also be configured in other configurations, including circular' symmetrical polygons, or JL's preferred geometry Graphic (not shown). /. In the example shown in FIG. 3a, the area array interconnection point 32 has an appearance very similar to & This allows the shortest matching length of the signal path between the two arrays, because of other design considerations, it is unlikely to match in this way. Fig. 3b shows another configuration. In this example, the area array interconnection points 32 of the circuit elements 36 in the memory subsystem 30 are closer to a rectangular shape. Although the area array interconnection point 32 is not the optimized shape of the area array interconnection point 32 as shown in Fig. 3a, it can still provide a significant improvement over the conventional technology (Fig. 1). Referring now to FIG. 3c, a cross-sectional view is shown, which is an enlarged side view of the plurality of circuit components in the preferred embodiment of FIG. 3a. This example demonstrates many possible options among possible technologies. The memory controller 4 communicates with the memory device 28 via a printed circuit path (not shown) of the system board 2. Contains one or more conductive layers (eg, signal, power, and / or ground) in it. Other materials may be used for different reasons, including electrical effects, wiring properties, and thermal performance, but epoxy-glass-based materials have a cost-effect ive and a coefficient of thermal expansion (CTE) to match the surroundings structure. Because of strict electrical specifications, the impedance of the signal path must match the impedance of the corresponding path on the system board 12 with an error of only 10%

Page 24 525184 V. Description of Invention (20). This embodiment includes 3 circuit elements 36, 38, 40, each of which is composed of a plurality of memory devices 28 surrounding the central areas 36c, 38c, 40c, respectively. 'It contains a plurality of contacts on the lower and higher surfaces 4 2 to allow interconnection of other circuit elements and connection of the system board 12 Q multiple contacts 42 are arranged and interconnected to allow circuit elements 36, 38, 40 to be stacked regardless of circuit elements 3 6, 3 8, 4 0 being stacked Any one of the position memory devices 28 can work normally. Examples of suitable circuit components include printed circuit boards, circuit modules, and the like. The term "printed circuit board π includes, but is not limited to, a multilayer circuit board structure that includes one or more conductive layers (eg, signal, power, and / or ground). This printed circuit board, usually also It is called a printed wiring board, and it is known in the industry. It will not be described in detail below. The "circuit module" means that it contains a substrate or similar components with different electronic parts (for example, semiconductor wafers, conductive circuits, conductive pins, etc. Etc.), which can be composed of parts. This module is also known to the industry and will not be described in detail below. The substrates 36s, 38s, and 40s corresponding to the circuit elements 36, 38, and 40 may be composed of a wide variety of dielectric materials. In one example, the substrates 36s, 38s, and 40s are made of epoxy-glass-based materials typically used in printed circuit board production, and also include one or more conductive layers therein. Because of strict electrical specifications, the signal path impedance must match the system impedance with an error of only ten percent. These materials are suitable because their CTE strictly matches the CTE of the surrounding structure (especially the LGA connector 50), and because they are relatively inexpensive. It must be understood that the technology disclosed in the present invention is not

525184 V. Description of the invention (21) " "-Different materials can be used for the same parts, instead of the specific materials disclosed in the aforementioned embodiments of the invention, without departing from the spirit of the invention. The f memory devices 28 may be packaged or unpackaged devices with many attachment options including, but not limited to, surf ace mounted 'BGA and wire bonds. It must be understood that other electronic components ', including but not limited to resistors and capacitors, typically interconnect to a plurality of memory devices 28. They are not shown here for illustrative purposes only. The first circuit element 36 has a plurality of pins 44 connected to the contacts 42 on the bottom surface thereof. The pins 44 are used to be inserted into the climbing base 46 located in a housing 47. In this case, the feet 46 are adhered to the corresponding contacts 42 of the system board 12 on the surface. A pin 44 array is useful for applications that require site isolation (ield separability), allow electrical discontinuities, limit the number and density of connections, and that a separate clamp is not allowed or not provided. The first circuit element 36 includes a selectively protruding central region 36c on its bottom surface 36b to allow the memory device 28 and other components such as a cooling structure (not shown) to have a greater degree without disturbing the interconnection of the bottom surface 36b. A lot of space_ The contact 42 on the upper surface 36t of the first circuit element 36 is connected to the contact 42 on the bottom surface 38b of the second circuit element 38 via the BGA solder joint 48. Solder joints 48 are not reusable, but when used appropriately, they provide a highly reliable method of interconnecting the surfaces of two planes. Second circuit element 38 on its upper surface

Page 26 525184 V. Description of the invention (22) 38t includes a selectively protruding central area 38c to allow the memory device 28 and other components such as cooling structures (not shown) to be present without interfering with the 38t interconnection on the upper surface. More space. The contact 42 on the upper surface 38t is removed to allow the LGA connector 50 to provide electrical connection to the third circuit element 40 via the contact 42 on the bottom surface 40b of the third circuit element 40. Compared with the PGA connector, the LGA connector 50 of the present invention (especially referring to the US patent in the aforementioned application) provides improved performance, increased density, lower height, and a CTE that better matches the surrounding structure. In addition, because the force required for each contact of the connector 50 is low, the number of contacts allowed to increase significantly with a certain reserve of force. Because the retention force is not inherent in the pin-and-socket PGA interconnection described above, a 'jaw mechanism (not shown) can be used to create the required force to ensure each contact element 52 is compressed in use by an appropriate number to form the interconnections of contacts 42 on the circuit elements 38,40. This jaw can be implemented in many ways. The circuit element 40 can be clamped to the circuit element 38, to the circuit element 36, or even to the system board 12 as required by the application. In this stable structure, the nipper mechanism does not require any mounting holes. It is more suitable to provide an array of control elements 52 and a consistent replacement force to avoid the problem of combining with the CTE mismatch. , And isolated space to facilitate user maintenance and upgrade. It must be noted that by maintaining interconnect clusters in a smaller space, the warpage effect of these circuit elements 38, 40 can be minimized. This will simplify design requirements and reduce the size and / or cost of the jaws. The circuit element 40 also includes a portion between its two upper surfaces 40t and the bottom surface 40b.

Page 525184

The nine Lt areas are convex to allow the memory device 28 and other components such as cold U (not shown in the figure) to have more space without disturbing the interconnection. The contacts 42 on the upper surface 40t are pressed to allow more connections. Although this embodiment does not specifically show a device aligned in a row of 40, a method that can be implemented. One is used to make the circuit element 38. There are already many circuit elements 36, 38, and 40 in the art. Aa & ^ ^ This also includes a thermal and electrical conductive layer 54 to modify all aspects of the D memory sub-system. Effectiveness. For example, the central regions 36c, 38c, 40c may provide protection for longer through holes, respectively. Although it is not common for all the different circuit components and interconnection options to appear simultaneously in a package application at the same time, it must be understood that this description is only for the purpose of opening the road 6¾. This interconnection use will depend on the specific needs of the known application. For example, if an application does not require site isolation, BGA solder joint interconnects will provide the most cost-effective and reliable interconnection option for stacking. However, if it is a high-speed, site isolation design with the highest electrical integration is required. Instead of pins, only LGA connectors (preferably with cladding) and BGA solder joint interconnections can be considered. Referring now to FIG. 3d, a cross-sectional view is shown, which is an enlarged side view of the comparative embodiment of FIG. 3c, by including other devices to provide additional functions. f In this example, part 56 is used as a plurality of blocking capacitors and / or decoupling capacitors of a power-off circuit component of a terminal component similar to a resistor (replacing the aforementioned US Patent No. 6,172,895 The US $ 12 board has many recognized benefits, including reduced interconnection, saving two rooms, and improving system performance. In other cases parts 5 6 can be made by other

525184 V. Description of the Invention (24) The device is composed of, for example, a microprocessor or a controller, so as to further enhance the performance of the secondary system. Please refer to FIG. 4a, which shows a partial top view of a memory subsystem 60, which is a preferred embodiment of the present invention, which includes a memory controller 62 and a first circuit element 64. The circuit element 64 of the memory sub-system 60 is provided with a cluster area array contact interconnection 70. The circuit element 6 4 includes a plurality of memory devices 58 on at least one surface. As shown, the path of the RAMBUS channel 76 passes through the plurality of memory devices 58 of the first circuit element 64. Because of the difference between RAMBUS technology and DDR SDRAM, the location of the cluster area array contact 70 and the multiple memory devices 58 must be adjusted. The cluster area array contact interconnect 70 is composed of two smaller arrays: an input array 70a and an output array 70b. These arrays 70a and 70b are placed near one edge of the circuit element 64, which is the opposite of the case of the DDR SDRAM device in Fig. 3c, thus allowing the distance from the memory controller 62 to be minimized. It is not critical that the distance between each memory device 58 and the cluster area array contact interconnect 70 on the circuit element 64 be equalized. The path length from the input array 70a and the output array 70b to the first and last memory device 58 is minimized. In any case, as long as the path length from the memory device 58 to _ is minimized, by reducing All transmission delays will provide a significant improvement in all performance of the memory subsystem 60. Reference is now made to Fig. 4b, which illustrates a top view of the plurality of circuit elements being tightly coupled in the preferred embodiment of Fig. 4a. These two embodiments are functionally equivalent. The embodiment shown in Figure 4b is more efficient in the use of space.

Page 29, 525184 V. Description of the invention (25) '" " ^ Please refer to FIG. 4c, which illustrates a top view of a part of the memory, system 60, according to one of the preferred embodiments of FIG. 4a, which includes A memory controller 62 and a first circuit element 64. The area array contact interconnects 70 of the circuit elements 64 'of the RAMBUS-based memory subsystem 60 are placed in the center and considered as an extension of the embodiment shown in Fig. 4a. The circuit element 64 includes at least a large number of memory devices 58 on one surface. As shown in the figure, the road control of the RAMBUS channel 76 passes through the first circuit element 64 and a plurality of memory devices 58. Because of the difference between RAMBUS technology and DDR SDRAM, the position of the cluster area array contact 70 and the plurality of memory devices 58 must be adjusted. The cluster area array contact interconnection 70 'is composed of two smaller arrays: an input array 70a' and an output array 70b. These arrays 70a, and 70b are placed at one end near the edge, which is the opposite of the case of the ddr SDRAM device in FIG. 3C, which allows the distance from the memory controller 62 to be minimized. It is not critical that the distance between each memory device 58 on the circuit element 64 'and the cluster area array contact interconnect 70' is equalized. The path length from the input array 70a 'and the output array 70b' to the first and last memory devices 58 is minimized. In any case, as long as the path length from the memory devices 58 to 8 is minimized, by reducing All transmission delays will provide a significant improvement in all performance of the memory subsystem 60 '. Please refer to FIG. 4d, which illustrates a cross-sectional view, which is an enlarged side view of the plurality of circuit components in the preferred embodiment of FIG. 4a; and FIG. 4e illustrates the RAMBUS channel 76 of FIG. 4d through different components. Schematic diagram of the path. The memory controller 62 of the RAMBUS memory subsystem 60 includes a direct RAMBUS clock generator (1) 1 ^ 0) circuit 6 23 and a direct 1 ^% 61 ^ cell (1) 1 ^ (:)

Page 30 525184 V. Invention Description (26) One of the main devices 62b is implemented on the system board 12. In the RAMBUS memory subsystem 60, the data path starts from the memory controller 62 and passes through each circuit element of the subsystem 60 until it finally reaches a bus terminal 74 (please refer to FIG. 4e). Placed after the system board 12 or on the last circuit element on the path. By carefully configuring the different signals, power, and ground connections of the RAMBUS to specific contacts 42, in a known amount of memory (for example, 256MB), simply by vertically reversing each different circuit element in the stack It is possible to create a single circuit element part number. This allows the contacts 42 of the output array 70b in a circuit element I to be placed vertically below the input array 70a of the next circuit element in the stack and vice versa. This concept also allows other circuit elements with different amounts of memory to be used in the stack, as long as the configuration of the area array contact interconnection 70 contact 42 is unchanged. Please refer to FIG. 4d again, this example demonstrates again some of the possible technical options and includes three circuit elements 64, 66, 68. The memory controller 62 communicates with the memory device 58 through a printed circuit board (not shown) in the system board 12. Furthermore, because of the strict electrical specifications of the high-speed bus system, the signal path must match the impedance of the system and the error can only be within 10%. j Each circuit element 64, 66, and 68 includes a plurality of memory devices 58 surrounding the central regions 64c, 66c, and 68c, respectively. On the lower and upper surfaces, it includes a plurality of contacts 42 to allow communication with other circuit elements and Interconnection of the system board 丨 2. The contacts 4 2 are arranged and interconnected to allow the stack and the memory device 58 to work normally regardless of the position of the circuit elements 64, 66, and 68 in the stack.

Page 31

525184 V. Description of the invention (27) The substrates 64s, 66s, and 68s corresponding to the circuit components 64, 66, and 68 can be composed of a variety of dielectric materials. In one example, the substrates 64s, 66s, and 68s are made of epoxy-glass-base materials typically used in printed circuit board production, and also include one or more conductive layers therein. Because of strict electrical specifications, the signal path impedance must match the system impedance and the error can only be within a predetermined range. These materials are suitable because their CTE strictly matches the CTE of the surrounding structure (especially the LGA connector 72) and because they are relatively inexpensive. Furthermore, other possible materials are polyimide (po1y i m i de). The memory device 58 can be a packaged or unpackaged device with many attachment options including but not limited to surface adhesion. "." Mounted), BGA and wire bonding. Other electronic components, such as resistors and capacitors, are typically interconnected to a plurality of memory devices 58. As shown in the figure, the input array 70a of the first circuit element 64 on the bottom surface 64b has a plurality of contacts 42, and allows electrical connection to the system board 12 through the plurality of contacts 52 of the corresponding lga connector 72.之 接点 42。 Contact 42. For this example, it can be seen that the plurality of contacts 52 of the LGA connector 72 are also divided to match the positions of the contacts 42 in the input array 70a and the output array 701). The first electrical circuit element 64 includes a protruding central area 64c between its two upper surfaces 64t and the bottom surface 64b to allow the memory device 58 and other components such as a cooling structure (not shown) to More space. The contacts 42 of the output array 70b of the first circuit element 64 on the upper surface 64t are provided to allow other LGA connectors 72 to pass above the second circuit element 66.

Page 32 525184 V. Description of the invention (28) The contact 42 of the input array 70a of the surface 66A provides electrical connection. It should be noted that the circuit element 66 is connected to the upper surface and not the bottom surface, so in a single design, the circuit element 66 is rotated vertically to obtain a proper signal path. In addition, because the reserve force is not inherent in the pin-and-socket type interconnection in the first embodiment (see FIG. 3c), a “nipper mechanism (not shown)” may be used. It is used to create the necessary force to ensure that the contact elements 52 of each LGA connector 72 are compressed to an appropriate number when in use to form the contact 4 2 interconnects on the circuit elements 64, 66. This jaw can be implemented in many ways. The second circuit element 66 includes a protruding central area 66c between its two upper surfaces 66t and the bottom surface 66b to allow the memory device 58 and other components such as a cooling structure (not shown) to More space. The contacts 42 of the output array 70b of the second circuit element 66 on the upper surface 66b are connected to the contacts 42 of the input array 70a of the third circuit element 68 via a BGA pad 48. The third circuit element 68 includes a protruding central region 68c between the upper surface 68t and the bottom surface 68b thereof to allow the memory device 58 and other components such as a cooling structure (not shown) to have more without interfering with the interconnection. Space. The contacts 42 of the output array 70b on the upper surface 68 'are provided to allow more connections. · As mentioned above, a RAMBUS basic subsystem 60 requires a bus terminal 74 (see FIG. 4e) to follow the last memory device 58 in the path. If the bus terminal 74 is placed on the circuit element 68 (refer to FIG. 4e) or an additional only-termination module (not shown), only half of the interconnection is required. The other half of the interconnect can be omitted to support one

Page 33 525184 V. Description of the invention (29) The second memory channel, or provides a return path for the system board 2 to reach the final bus terminal 74. In addition, a voltage regulation module and a plurality of decoupling capacitors (both are not shown) are included near the bus terminal to improve electrical performance. As shown in the figure, although the DRCG circuit 62a (refer to Figures 4d and 4e) is placed in the system board 12 for the purpose of disclosure, it can be more optimally placed in other locations, such as the —The circuit element 68 of the terminal (refer to FIG. 4e) or other modules (not shown) with only terminals (oniy — terinination). The DRCG circuit 62a generates a differential clock pair, which travels in the opposite direction to all other signals in the sub-system 60. Signal attenuation occurs along the path of all RAMBUS channels, especially on the connector. It can be seen that all bus path lengths and all transmission delays of the memory sub-system 600 of the present invention will be greatly reduced compared with the general RAMBUs base sub-system. Generally speaking, by improving the quality of the RAMBUS channel (ie reducing the length, channel delay, crosstalk, etc.), a higher memory access speed can be obtained. This reduced path length can reduce the number of pins and socket-type connectors between terminals on multiple memory cards and modules, and greatly improve electrical integration. Although this embodiment does not specifically show a device for making the circuit elements 64, 66, and 68 in the system board 2 a line, there are many methods that can be implemented in this technology. The circuit elements 64, 66, 68 may further include a thermal and electrical conductive layer 54 to improve the performance of various aspects of the memory subsystem. For example, in the central area

Page 525184

64c, 66c, 68c can provide protection for longer through holes, respectively.

Because the chips in the memory devices 28 and 58 are cracked to: an effective heat transfer medium and in the direction of the air flow (ie, the system: the board; 2 lack of flatness and lack of air) makes the memory subsystem 3 The natural cooling coefficients of 0 and 60 are low. Today's relatively large memory devices 28, 58 and close to other heat-generating memory devices 28, 58 in this package exacerbate the cooling problem. The thermal management structure 59 may be included in the system of the present invention to optimize heat conduction and radiation, thus allowing maximum circuit density without thermal build-up, which will be reduced = memory device 28, 58 performance and reliability. One of the thermal management structures 59; in Figure 4d. The thermal management structure 59 attempts to absorb heat from the memory devices 28, 58 and can be implemented in multiple ways. They may be a simple layer of thermally conductive material, such as aluminum, attached to the memory devices 28, 58 by thermally enhanced mixing or clamps. The thermal management structure 59 may be more complex and include, for example, fins to enhance heat dissipation. Other approaches may include the use of 'consistent liquid cancer heat transfer material pouches, thin heat pipes, and thermoelectric devices. Other solutions to heat dissipation problems will be apparent in the art. Please refer to FIG. 4 f ′, which is another configuration of the embodiment of FIGS. 4 a-4 c. For applications that require higher memory subsystem output rates, a system designer may include multiple memory channels. A top view of a RAMBUS-based circuit element 80 is shown in FIG. 4F, which includes a first memory channel 82, a second memory channel 82 ', and a plurality of memory devices 58 on at least one surface. And centralization / localization of area array contact interconnection 84

525184 V. Description of the invention (31) Configuration. It is also shown that the paths of the RAM BUS channels 86 and 86 'pass through the plurality of memory devices 58 of the first circuit element 80. The area array contact interconnection 8 4 is composed of four smaller arrays, the input arrays 84a and 84a 'and the output arrays 84b and 84b. These small arrays are placed

It is located closer to the center of the circuit element 80. It is not critical that the distance between each memory device 58 on the circuit element go and the cluster area array contact interconnections 84 be equalized. The path lengths from the input arrays 8 4 a and 8 4 a ′ and the round-out arrays 8 4 b and 84 b ′ to the first and last memory devices 58 are minimized. The path length is minimized, and all performance of the memory subsystem (not shown) will be greatly improved by reducing all transmission delays. Number of figures. The number of RAMBUS channels 92 is configured. Element 90 and each output 90

Referring to Fig. 4g, which shows the embodiment shown in Fig. 4f when the installation is small (for example, each channel is two or four), all the dimensions of the extended path element also become smaller. A top view of a basic circuit element 90 is shown in FIG. 4g, which includes a first memory: a second memory channel 92, which has at least one surface with fewer memory devices 58, and an area array interface. The clusters of the dot interconnects 94 and 96 also show the RAMBUS channels 98 and 98, the path of which passes through the first memory device 58. The zone array is connected // connected with 94 electrical power; It is composed of two smaller arrays, such as input arrays 94a and 943, arrays 96b and 96b '. These small arrays are placed on the opposite edge of the first electrical day. This example is adjacent to each other and demonstrates the clustering of the foregoing embodiments. The input arrays 94a and 94a and the output arrays 96b and 96b are also adjacent to each other. But because of electricity

525184 V. Description of the invention (32) The circuit element 90 is very small compared with the circuit element composed of many memory devices 58 described previously. The DNp and CTE for larger circuit elements will no longer be an issue. There is no need for four arrays. The separate input and output arrays 94 and 96 provide circuit elements 9 0 with improved wiring capabilities without affecting the stability of the mechanism. Although the implementation of the above embodiment shows that the memory device has three circuit elements for the purpose of disclosure, it can be clearly known that a plurality of parameters such as the quantity 'specific appearance' size and the material of the card, the plurality of memory devices The layout and packaging will change according to specific needs. These modifications are also within the scope of the present invention. _ In addition, the disclosed principles are not used for a variety of these inclusive applications. They are different from the previous examples. Although the drawings are limited in scope and scope, when DDR SDRAM- and RAMBUS-based memory The secondary system was selected for the purpose. It is obvious that the teaching of the present invention can only be applied to other high-speed memory secondary systems, and can also be applied to other high-speed, impedance-controlled bus data secondary systems and applications. But it is not limited to microprocessors, digital signal processors, and communication based and sub-systems, and other applications disclosed above. In the description, the present invention refers to specific exemplified concrete explanations, but obviously does not deviate from the amendments and changes of the present invention, as shown in the application of the malignant decay m ^ m ^ as a reference rather than limitation Γ. This description (Second issue: The month has been disclosed as above with a preferred embodiment, but it is not intended to be used for this skill. ☆ Without leaving the fine field of the present invention, you can make a few changes and retouching, so Subject to the scope of the attached patent application.

525184 V. Description of the invention (33)-*-[Brief description of the diagram] Figure 1 is a bus interconnecting arrangement of a memory controller device and a plurality of memory modules in a memory subsystem in a conventional technique The schematic. Figure 2 is a bottom view of the bus interconnects of the area array contacts of the memory controller device and the target device. # FIG. 3a is a top view of a centralized configuration of circuit element area array contact interconnections of a DDR sdraM-based memory system according to a preferred embodiment of the present invention. FIG. 3b is a top view of another set of states of the circuit element area array contacts of a memory system based on a DDR SDRAM based on a preferred embodiment of the present invention in FIG. 3a. ^ Fig. 3c is a sectional view showing an enlarged side view of the plurality of circuit elements in the preferred embodiment of Fig. 3a. Fig. 3d is a cross-sectional view, which is an enlarged side view of the preferred embodiment of Fig. 3c, by including other devices to provide additional functions. FIG. 4a is a top view of a RAMBUS-based memory sub-system according to a preferred embodiment of the present invention, in which the centralized configuration of the interconnection of the circuit element area array contacts is modified. Fig. 4b is a top view of the plurality of circuit elements in the preferred embodiment of Fig. 4a being more tightly coupled. Fig. 4c is a top view of a modified, centralized arrangement of circuit element area array contact interconnections of a RAMBUs-based memory sub-system according to one of the preferred embodiments of Fig. 4a, after modification. Fig. 4d is a cross-sectional view, which is an enlarged view of the complex number in the preferred embodiment of Fig. 4a

Page 38 525184 V. Description of the invention (34) Side view of circuit components. Fig. 4e is a schematic diagram showing the path of the RAMBUS channel in the preferred embodiment of Fig. 4d. Fig. 4f shows a top view of another configuration of the RAMBUS base memory subsystem in the preferred embodiment of Figs. 4a to 4c. Figure 4g shows a top view of another configuration of the RAMBUS base memory subsystem in the preferred embodiment of Figure 4f. [Illustration of component numbers of diagrams] Memory sub-system 10 System board 12 Memory controller 14 Memory modules 16a-16d Bus interconnect 1 8 a -1 8 d BGA solder joint 20 Bottom 22 Contact 24 Memory device 28 Memory Subsystem 30 Area Array Interconnection Point Bus Interconnect Circuit Components Bottom Surface Central Area Substrate Upper Surface 32, 32, 34a-34c 36 H 40 36b, 38b, 40b 36c " 38c ^ 40c 36s' 38s ^ 40s 36t ^ 38t-40t Contacts 42 Pins 44 Pins 46 Housings 4 7 BGA Solder Joints 48 LGA Connectors 50 Contact Elements 52 Electrically Conductive Layers 54

Page 39 525184 V. Description of the invention (35) Parts 56 Memory device 58 Thermal management structure 59 Memory subsystem 60 > 60, Memory controller 62 Clock generator circuit 62a Main device 62b Circuit elements 64, 64 ' , 66, 68 bottom surface 64b, 66b, 68b central area 64c '66c ^ 68c substrate 64s ^ 66s-68s upper surface 641, 66t, 68t cluster area array contact interconnection 70 > 70' input array 70a, 70a 'output Array 70b, 70b 'LGA connector 72 Bus terminal 74 RAMBUS channel 76 Circuit element 80 First memory channel 82 Second memory channel 82J Area array contact interconnection 84 Input array 84a, 84a' Output array 84b, 84b ' RAMBUS channel 86 ^ 86? Circuit element 90 first memory channel 92 second memory channel 92J area array contact interconnection 94, 96 input array 94a, 94a 'output array 96b, 96b'

Page 525184

Page 41

Claims (1)

525184 6. Scope of patent application 1. A stackable electronic module includes: a) a substrate having a first surface and a second surface; a surface and a surface substantially parallel to the first surface b) a first A two-dimensional style Zhongshan-the style is arranged on the base of the base plate ::; a number of electrical contacts-the first external bus; the surface can be adjusted to connect a c) a plurality of electrical connection points The first pattern of the composition is formed to: effectively connect to the plurality of electrical devices, expand the bus; and expand the first surface and the first external bus on at least one of the two surfaces; Illegal devices can be selectively connected to the pattern 2. If the external connection 3. If the expansion resistors are included, the characteristic resistance 4. If the middle and multiple electricity 5 • If the middle == middle These devices are arranged next to the first patent application bus composed of the electrical contacts, including a number of patent application patent buses, and these exchange reactances. Shenyan patent range 排 Terminal mounting @ 复 Multiple patent applications The resistance is a stackable electronic module as described in item 1 above, one of the characteristic impedances. The terminal of the stackable electronic module described in item 2 is installed, and the terminal is effectively connected to the external bus terminal device. An impedance that substantially matches the stackable electronic module described in item 3 is provided. Contains at least one electrical part of the following group ... capacitors and multiple inductors. The stackable electronic module described in item 4 is composed of a distributed resistor. ’, 525184 VI. Application for patent scope 6 # As in Item 5 of the scope of patent application, these resistors are composed of an array of resistors. (7) In the electronic module, the resistors such as the stackable electronic module described in item 6 of the scope of the sixth item are composed of a solid-state resistive device. ^ As described in item 丨 of the patent application, these devices include at least one memory device. The stackable electronic module described in item 1 of the 隹 stack electronics group 组: 可: The stackable electronic module described in the first item of the range includes a plurality of solder joints. The second-degree electrical module is a stackable electronic module as described in the first item of the second item / the second item. The middle-shoulder electrical connection device includes a PGA connector. 11 · The electrical connection device described in item 丨 of the patent application scope includes an LGA connector. Tea chess set 12. The stackable electrical device as described in item u of the patent application range wherein the LGA connector is one of the 'SuperbuttonTM-based' connectors provided by High Connection Density Corporation. 1 3 · The substrate of the stackable electronic module according to item 丨 of the patent application scope includes at least one insulating material. 1 4 · The stackable electronic module as described in item 3 of the scope of patent application, wherein at least one kind of insulation material of δH is epoxy-glass-based ° 15 The stackable electronic module according to item 14, wherein the at least one insulating material comprises FR4. 1 6. The stackable electronic module according to item 13 of the scope of patent application, wherein at least one of the insulating materials comprises a polyimide. Page 43 Its Ml Its 苴 525184 VI. Application for patent Fangu which should be applied as little as possible "Second benefit: stackable electronic module described in Shiwei Item 13, ^ An insulating material contains ceramics. Which should be applied as little as possible "# 种 专 绝 ^ 二 分 分. The materials include a polymer (Polymeric) stackable electronic module connected to the first item of the νΛ patent scope, where the first type system consisting of contacts is clustered together. Among them, the stackable electronic module as described in item 19 of the patent scope is a square: the shape formed by the-pattern consisting of dots is essentially (stackable electronics as described in item 19 of the patent scope) The module is: the outer shape formed by the first pattern composed of squared contact points is substantially 22. the outer shape formed by the first pattern composed of stackable electrical contacts as described in item 19 of the scope of patent application Essentially 2 3 · The stackable electronic module as described in item 1g of the scope of the patent application, wherein the outer shape formed by the first pattern composed of the electrical contacts is polygonal. Λ M J1 2 4 · 如The stackable electronic module described in item 19 of the scope of the patent application, wherein the third pattern consisting of four specialized electrical contacts includes at least two smaller patterns composed of a plurality of electrical contacts clustered together. 25. The stackable electronic module according to item 19 of the scope of patent application, further comprising a plurality of numbers in a second two-dimensional pattern on the second surface of the substrate. Page 44 525184 /, Shen Qing patent range one of the electrical contacts composed of a second style, at least one of the first style composed of electrical contacts, the device is connected, the point constitutes at least the second style of the second style One point. . To these electrical connections 26. If the scope of the patent application is No. 25, where the electrical contact is composed of the first: electronic module, the contact is composed of the i-style. & sample is substantially equal to the electrical 27. As described in item 26 of the patent application, where the connected devices expand the external bus to the electronic module ^ sub-module. The arch is hidden to a second stackable electric pain 28. The stackable electronic module described in item 19 of the scope of patent application, further includes an external printed circuit board structure ', and wherein the external printed circuit board structure and the external printed circuit board structure parallel. Buy the 29. The stackable electronic module as described in item 28 of the scope of patent application, wherein the external printed circuit board structure further includes a third two-dimensional pattern composed of a plurality of electrical contacts and arranged on the external One of the printed circuit board structures is on the first surface and is suitably connected to the external bus. 3 0 · The stackable electronic module described in item 29 of the scope of patent application, wherein the third pattern system composed of the electrical contacts is clustered together '3 1 · as described in item 30 of the scope of patent application The stackable electronic module, wherein the outer shape formed by the third pattern composed of the electrical contacts is qualitatively equal to the outer shape formed by the first pattern composed of the electrical contacts. 32. The stackable electronic module according to item 31 of the scope of patent application, wherein the external shape formed by the third pattern composed of the electrical contacts is solid Page 45 525184 VI. Scope of patent application The shape which is similar to the first pattern composed of these electrical contacts is qualitatively similar. 33. The stackable electronic module according to item 1 of the scope of patent application, wherein the devices surround at least two sides of the first pattern composed of the electrical contacts. 34. The stackable electronic module according to item 13 of the scope of patent application, wherein the insulating material has a coefficient of thermal expansion (CTE) to substantially match the coefficient of thermal expansion (CTE) of the structural material connected internally. ). 35 · — A stackable electronic module with multiple channels, including: a) — a substrate having a first surface and a first surface substantially parallel to the first surface; b) a first surface One of the two-dimensional patterns is composed of a plurality of electrical contacts. The first pattern is disposed on the first surface of the substrate and is suitably connected to an external bus; ~ c) A plurality of electrical connection devices are effectively connected to The first pattern composed of the electrical points to form the two external buses d): a group of a plurality of devices, which are adhered to at least one surface of the first table of the substrate = a surface, each group is individually One of the external buses; drink Λ — group in which the two groups of plural devices are arranged in the first pattern next to the J member. Cutting point group