JP2012129337A5 - - Google Patents

Download PDF

Info

Publication number
JP2012129337A5
JP2012129337A5 JP2010278926A JP2010278926A JP2012129337A5 JP 2012129337 A5 JP2012129337 A5 JP 2012129337A5 JP 2010278926 A JP2010278926 A JP 2010278926A JP 2010278926 A JP2010278926 A JP 2010278926A JP 2012129337 A5 JP2012129337 A5 JP 2012129337A5
Authority
JP
Japan
Prior art keywords
bit line
memory cells
data
word line
complementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010278926A
Other languages
English (en)
Japanese (ja)
Other versions
JP5648460B2 (ja
JP2012129337A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2010278926A priority Critical patent/JP5648460B2/ja
Priority claimed from JP2010278926A external-priority patent/JP5648460B2/ja
Publication of JP2012129337A publication Critical patent/JP2012129337A/ja
Publication of JP2012129337A5 publication Critical patent/JP2012129337A5/ja
Application granted granted Critical
Publication of JP5648460B2 publication Critical patent/JP5648460B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2010278926A 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器 Active JP5648460B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010278926A JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010278926A JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Publications (3)

Publication Number Publication Date
JP2012129337A JP2012129337A (ja) 2012-07-05
JP2012129337A5 true JP2012129337A5 (cg-RX-API-DMAC7.html) 2014-01-30
JP5648460B2 JP5648460B2 (ja) 2015-01-07

Family

ID=46646074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010278926A Active JP5648460B2 (ja) 2010-12-15 2010-12-15 記憶装置、集積回路装置、及び電子機器

Country Status (1)

Country Link
JP (1) JP5648460B2 (cg-RX-API-DMAC7.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12073919B2 (en) * 2021-06-25 2024-08-27 Advanced Micro Devices, Inc. Dual read port latch array bitcell

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2821063B2 (ja) * 1991-07-18 1998-11-05 富士通株式会社 半導体集積回路装置
US5966317A (en) * 1999-02-10 1999-10-12 Lucent Technologies Inc. Shielded bitlines for static RAMs
US6504246B2 (en) * 1999-10-12 2003-01-07 Motorola, Inc. Integrated circuit having a balanced twist for differential signal lines
JP3835220B2 (ja) * 2001-08-31 2006-10-18 セイコーエプソン株式会社 半導体記憶装置
JP4052192B2 (ja) * 2003-03-14 2008-02-27 セイコーエプソン株式会社 半導体集積回路
JP4914034B2 (ja) * 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
JP5217042B2 (ja) * 2007-07-06 2013-06-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5549079B2 (ja) * 2009-01-14 2014-07-16 セイコーエプソン株式会社 半導体集積回路

Similar Documents

Publication Publication Date Title
JP6799520B2 (ja) Ｄｒａｍ基盤プロセシングユニット
KR101854251B1 (ko) 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치
JP6465846B2 (ja) 半導体メモリ装置
JP6785738B2 (ja) Ｄｒａｍ基盤のプロセシングユニット
US20130083591A1 (en) Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets
US20090097348A1 (en) Integrated circuit including a memory module having a plurality of memory banks
JP2005260014A5 (cg-RX-API-DMAC7.html)
JP2009545095A5 (cg-RX-API-DMAC7.html)
JP2017224377A5 (ja) メモリ装置、半導体装置、電子部品および電子機器
TW201816619A (zh) Dpu操作用的系統
WO2013025262A3 (en) Memory devices and methods for high random transaction rate
JP6321650B2 (ja) メモリセルの分散されたサブブロックにアクセスすることを伴う装置および方法
TWI265526B (en) Semiconductor memory device and arrangement method thereof
JP2007059026A5 (cg-RX-API-DMAC7.html)
KR101183739B1 (ko) 멀티포트 메모리 슈퍼셀 및 데이터 경로 스위칭 회로를 갖는 집적 회로
US7761668B2 (en) Processor architecture having multi-ported memory
JP2019537186A (ja) Ｃｐｕソケット毎に追加メモリモジュールスロットを備えた拡張プラットフォーム
US20150117091A1 (en) Multi-channel, multi-bank memory with wide data input/output
JP2011222985A5 (cg-RX-API-DMAC7.html)
JP2021048266A (ja) 半導体記憶装置
JP2012129337A5 (cg-RX-API-DMAC7.html)
WO2002019129A3 (en) Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
JP2010010369A5 (cg-RX-API-DMAC7.html)
WO2017105776A1 (en) Dram data path sharing via a split local data bus and a segmented global data bus
KR100599444B1 (ko) 글로벌 데이터 버스 연결회로를 구비하는 멀티-포트메모리 소자