JP2015502039A - 自己整合コンタクト及びローカル相互接続を形成する方法 - Google Patents
自己整合コンタクト及びローカル相互接続を形成する方法 Download PDFInfo
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Abstract
Description
Claims (24)
- 半導体装置の製造方法であって、
複数の置換金属ゲートを含むトランジスタを、ソース及びドレインを有する第1のゲートと、前記第1のゲートから分離された少なくとも1つの第2のゲートと共に半導体基板上に設けるステップであって、前記トランジスタは、前記第1のゲートの周囲の第1の絶縁材料からなるゲートスペーサと、前記ゲートスペーサ間の第2の絶縁材料からなる第1の絶縁層とを含み、前記第2の絶縁材料のうち少なくとも一部が、前記第1のゲートのソース及びドレイン上に設けられる、ステップと、
前記ゲート上に整合された1つ以上の絶縁マンドレルを形成するステップであって、前記絶縁マンドレルは前記第1の絶縁材料を含む、ステップと、
前記絶縁マンドレルの周囲にマンドレルスペーサを形成するステップであって、前記マンドレルスペーサは前記第1の絶縁材料を含む、ステップと、
前記第2の絶縁材料からなる第2の絶縁層を前記トランジスタ上に形成するステップと、
前記絶縁マンドレル間の前記トランジスタの部分から前記第2の絶縁材料を除去することにより、前記第1のゲートの前記ソース及びドレインまでの1つ以上の第1のトレンチを形成するステップと、
前記第2のゲートの上方の前記第1の絶縁材料及び前記第2の絶縁材料の部分を除去することにより、前記第2のゲートまでの第2のトレンチを形成するステップと、
導電性材料を前記第1のトレンチ及び前記第2のトレンチに充填して、前記第1のゲートの前記ソース及びドレインに対する第1のコンタクトと、前記第2のゲートに対する第2のコンタクトとを形成するステップと、
を含む、半導体装置の製造方法。 - 前記第1のトレンチ及び前記第2のトレンチに対して導電性材料を単一のプロセスで充填するステップをさらに含む、請求項1に記載の半導体装置の製造方法。
- 前記絶縁マンドレルは、下側のゲートとほぼ同じ幅を有し、絶縁マンドレルは、少なくとも下側のゲートと同じ幅である、請求項1に記載の半導体装置の製造方法。
- 前記マンドレルスペーサは、下部においてより幅広であり、且つ、上部においてより幅狭な傾斜状の外形を有する、請求項1に記載の半導体装置の製造方法。
- 前記マンドレルスペーサのうち少なくとも一部は、前記第1のトレンチ内で露出する、請求項1に記載の半導体装置の製造方法。
- 前記絶縁マンドレルの縁部は、前記ゲートの縁部を超えて延在する、請求項1に記載の半導体装置の製造方法。
- 前記マンドレルスペーサの縁部は、前記ゲートスペーサの縁部を超えて延在する、請求項1に記載の半導体装置の製造方法。
- 第2の絶縁材料を選択的に除去し、且つ、第1の絶縁材料を除去しないプロセスにおいて、前記第2の絶縁材料を除去することによって、前記第1のゲートの前記ソース及びドレインまでの前記第1のトレンチを形成するステップをさらに含む、請求項1に記載の半導体装置の製造方法。
- 前記絶縁マンドレルを形成する前に、前記第2の絶縁材料からなる肉薄層を前記トランジスタ上に形成するステップをさらに含む、請求項1に記載の半導体装置の製造方法。
- 前記第1のコンタクトは、前記マンドレルスペーサの傾斜によって決定される傾斜を含む、請求項1に記載の半導体装置の製造方法。
- 前記第1のトレンチ及び前記第2のトレンチに導電性材料を充填した後に、前記トランジスタを平坦化するステップをさらに含む、請求項1に記載の半導体装置の製造方法。
- 前記第1のトレンチ及び前記第2のトレンチを形成するステップは、前記第1のトレンチ及び前記第2のトレンチを規定する、CAD(コンピュータ支援設計)設計されたレジストパターンを用いて実行される、請求項1に記載の半導体装置の製造方法。
- 前記トランジスタ上に第3の絶縁層を形成するステップと、
前記第3の絶縁層の一部を除去することにより、前記第3の絶縁層を通じて前記第1のコンタクト及び前記第2のコンタクトまでの第3のトレンチを形成するステップと、
前記第3の絶縁層を通じて形成された前記第3のトレンチ内に導電性材料を堆積させることにより、前記第1のコンタクト及び前記第2のコンタクトに対してローカル相互接続を形成するステップと、
をさらに含む、請求項1に記載の半導体装置の製造方法。 - 第1の絶縁材料を選択的に除去し、且つ、第2の絶縁材料を除去しないプロセスにおいて、前記トレンチが前記ゲートに対して整合するように、前記ゲートの上方の前記第1の絶縁材料の部分を除去するステップをさらに含む、請求項1に記載の半導体装置の製造方法。
- 半導体装置であって、
半導体基板上の複数の置換金属ゲートであって、第1のゲートはソース及びドレインを有し、少なくとも1つの第2のゲートは、前記第1のゲートから分離されている、複数の置換金属ゲートと、
前記第1のゲートの周囲の第1の絶縁材料からなるゲートスペーサと、
前記ゲートスペーサ間の第2の絶縁材料からなる第1の絶縁層であって、前記第2の絶縁材料のうち少なくとも一部は、前記第1のゲートのソース及びドレインの上に設けられている、第1の絶縁層と、
前記ゲート上に整合された1つ以上の絶縁マンドレルであって、前記絶縁マンドレルは前記第1の絶縁材料を含む、1つ以上の絶縁マンドレルと、
前記絶縁マンドレルの周囲のマンドレルスペーサであって、前記マンドレルスペーサは前記第1の絶縁材料を含む、マンドレルスペーサと、
前記マンドレルスペーサ間の前記第1の絶縁層を通じた、前記第1のゲートの前記ソース及びドレインに対する第1のコンタクトと、
前記第2のゲートの上方の前記第1の絶縁材料を通じた、前記少なくとも1つの第2のゲートに対する第2のコンタクトと、
前記トランジスタ上の第3の絶縁層と、
前記第3の絶縁層を通じて前記第1のコンタクト及び前記第2のコンタクトと接触する1つ以上のローカル相互接続と、
を含む、装置。 - 前記少なくとも1つの第2のゲートに対する前記第2のコンタクトは、前記第2のゲートの上方の前記マンドレルを通じて設けられている、請求項15に記載の装置。
- 前記絶縁マンドレルの幅は、下側のゲートとほぼ同じ幅であり、絶縁マンドレルは、少なくとも下側のゲートと同じ幅である、請求項15に記載の装置。
- 前記マンドレルスペーサは、下部においてより幅広であり、且つ、上部においてより幅狭な傾斜状の外形を有する、請求項15に記載の装置。
- 前記第1のコンタクトは、前記マンドレルスペーサの傾斜に整合する外形を有しており、前記第1のコンタクトは、上部において下部よりも幅広となる、請求項15に記載の装置。
- 前記第1のコンタクトは、前記ゲートに対して短絡しない、請求項15に記載の装置。
- 前記第3の絶縁層は、前記第2の絶縁材料を含む、請求項15に記載の装置。
- 前記第1のゲートは、前記半導体装置の活性領域内に配置され、前記第2のゲートは、前記半導体装置の分離領域内に配置される、請求項15に記載の装置。
- 複数の命令を記憶するコンピュータ可読記憶媒体であって、前記複数の命令が実行されると、半導体プロセスにおいて用いることが可能な1つ以上のレジストパターンが生成され、
前記半導体プロセスは、
複数の置換金属ゲートを含むトランジスタを、ソース及びドレインを有する第1のゲートと、前記第1のゲートから分離された少なくとも1つの第2のゲートと共に半導体基板上に設けることであって、前記トランジスタは、各第1のゲートの周囲の第1の絶縁材料からなるゲートスペーサと、前記ゲートスペーサ間の第2の絶縁材料からなる第1の絶縁層とを含み、前記第2の絶縁材料のうち少なくとも一部は、前記第1のゲートのソース及びドレイン上に設けられることと、
前記ゲート上に整合された1つ以上の絶縁マンドレルを形成することであって、前記絶縁マンドレルは、前記第1の絶縁材料を含むことと、
前記絶縁マンドレルの周囲にマンドレルスペーサを形成することであって、前記マンドレルスペーサは前記第1の絶縁材料を含むことと、
前記トランジスタ上に前記第2の絶縁材料からなる第2の絶縁層を形成することと、
前記絶縁マンドレル間の前記トランジスタの部分から前記第2の絶縁材料を除去することにより、前記第1のゲートの前記ソース及びドレインに対して1つ以上の第1のトレンチを形成することと、
前記第2のゲートの上方の前記第1の絶縁材料及び前記第2の絶縁材料の部分を除去することにより、前記第2のゲートに対する第2のトレンチを形成することと、
前記第1のトレンチ及び前記第2のトレンチに導電性材料を充填して、前記第1のゲートの前記ソース及びドレインに対する第1のコンタクトと、前記第2のゲートに対する第2のコンタクトを形成することと、を含む、
コンピュータ可読記憶媒体。 - 複数の命令を記憶するコンピュータ可読記憶媒体であって、前記複数の命令が実行されると、半導体装置が生成され、
前記半導体装置は、
半導体基板上の複数の置換金属ゲートであって、第1のゲートはソース及びドレインを有し、少なくとも1つの第2のゲートは前記第1のゲートから分離されている、複数の置換金属ゲートと、
前記第1のゲートの周囲の第1の絶縁材料からなるゲートスペーサと、
前記前記ゲートスペーサ間の第2の絶縁材料からなる第1の絶縁層であって、前記第2の絶縁材料のうち少なくとも一部は、前記第1のゲートのソース及びドレイン上に設けられている、第1の絶縁層と、
前記ゲート上に整合された1つ以上の絶縁マンドレルであって、前記絶縁マンドレルは前記第1の絶縁材料を含む、1つ以上の絶縁マンドレルと、
前記絶縁マンドレルの周囲のマンドレルスペーサであって、前記マンドレルスペーサは前記第1の絶縁材料を含む、マンドレルスペーサと、
前記マンドレルスペーサ間の前記第1の絶縁層を通じた、前記第1のゲートの前記ソース及びドレインに対する1つ以上の第1のコンタクトと
前記第2のゲートの上方の前記第1の絶縁材料を通じた、前記少なくとも1つの第2のゲートに対する第2のコンタクトと、
前記トランジスタ上の第3の絶縁層と、
前記第3の絶縁層を通じて前記第1のコンタクト及び前記第2のコンタクトと接触する、1つ以上の局所的相互接続と
を含む、
コンピュータ可読記憶媒体。
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Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8716124B2 (en) * | 2011-11-14 | 2014-05-06 | Advanced Micro Devices | Trench silicide and gate open with local interconnect with replacement gate process |
US8916426B2 (en) * | 2012-03-27 | 2014-12-23 | International Business Machines Corporation | Passive devices for FinFET integrated circuit technologies |
KR101929478B1 (ko) * | 2012-04-30 | 2018-12-14 | 삼성전자주식회사 | 매립 채널 어레이를 갖는 반도체 소자 |
US8895397B1 (en) * | 2013-10-15 | 2014-11-25 | Globalfoundries Singapore Pte. Ltd. | Methods for forming thin film storage memory cells |
US9153483B2 (en) | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US9443851B2 (en) * | 2014-01-03 | 2016-09-13 | Samsung Electronics Co., Ltd. | Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same |
US9231072B2 (en) | 2014-02-12 | 2016-01-05 | International Business Machines Corporation | Multi-composition gate dielectric field effect transistors |
US9379058B2 (en) * | 2014-02-14 | 2016-06-28 | Qualcomm Incorporated | Grounding dummy gate in scaled layout design |
US10490497B2 (en) | 2014-06-13 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective formation of conductor nanowires |
KR102183038B1 (ko) | 2014-07-16 | 2020-11-26 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US9620417B2 (en) * | 2014-09-30 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and method of manufacturing fin-FET devices |
US9799567B2 (en) | 2014-10-23 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming source/drain contact |
US9496394B2 (en) | 2014-10-24 | 2016-11-15 | Globalfoundries Inc. | Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s) |
US9443853B1 (en) | 2015-04-07 | 2016-09-13 | International Business Machines Corporation | Minimizing shorting between FinFET epitaxial regions |
CN106206714B (zh) * | 2015-04-30 | 2020-06-30 | 联华电子股份有限公司 | 半导体器件 |
US9722043B2 (en) | 2015-06-15 | 2017-08-01 | International Business Machines Corporation | Self-aligned trench silicide process for preventing gate contact to silicide shorts |
US9508818B1 (en) | 2015-11-02 | 2016-11-29 | International Business Machines Corporation | Method and structure for forming gate contact above active area with trench silicide |
US10090249B2 (en) | 2015-12-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
US9881872B2 (en) | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a local interconnect in a semiconductor device |
DE102016114724B4 (de) | 2016-03-25 | 2021-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung |
DE102016114779A1 (de) * | 2016-05-19 | 2017-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Struktur und Verfahren für ein Halbleiter-Bauelement |
KR102604564B1 (ko) * | 2016-07-01 | 2023-11-22 | 인텔 코포레이션 | 자기 정렬 게이트 에지 트라이게이트 및 finfet 디바이스들 |
US10096604B2 (en) * | 2016-09-08 | 2018-10-09 | Globalfoundries Inc. | Selective SAC capping on fin field effect transistor structures and related methods |
US10026647B2 (en) | 2016-12-12 | 2018-07-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-metal fill with self-align patterning |
US10199265B2 (en) * | 2017-02-10 | 2019-02-05 | Globalfoundries Inc. | Variable space mandrel cut for self aligned double patterning |
KR102292645B1 (ko) * | 2017-03-09 | 2021-08-24 | 삼성전자주식회사 | 집적회로 소자 |
US11347925B2 (en) | 2017-05-01 | 2022-05-31 | Advanced Micro Devices, Inc. | Power grid architecture and optimization with EUV lithography |
US11211330B2 (en) * | 2017-05-01 | 2021-12-28 | Advanced Micro Devices, Inc. | Standard cell layout architectures and drawing styles for 5nm and beyond |
KR102336827B1 (ko) | 2017-06-08 | 2021-12-09 | 삼성전자주식회사 | 반도체 장치 |
US10186599B1 (en) | 2017-07-20 | 2019-01-22 | International Business Machines Corporation | Forming self-aligned contact with spacer first |
KR102460076B1 (ko) * | 2017-08-01 | 2022-10-28 | 삼성전자주식회사 | 반도체 장치 |
KR102469885B1 (ko) | 2017-09-11 | 2022-11-22 | 삼성전자주식회사 | 반도체 장치 |
KR102342551B1 (ko) * | 2017-09-25 | 2021-12-23 | 삼성전자주식회사 | 아이솔레이션 영역을 포함하는 반도체 소자 |
US10600866B2 (en) * | 2018-02-01 | 2020-03-24 | Qualcomm Incorporated | Standard cell architecture for gate tie-off |
CN110504240B (zh) * | 2018-05-16 | 2021-08-13 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
KR102585881B1 (ko) | 2018-06-04 | 2023-10-06 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법. |
US10700128B1 (en) * | 2018-12-21 | 2020-06-30 | Micron Technology, Inc. | Three-dimensional memory array |
US10978307B2 (en) | 2019-08-20 | 2021-04-13 | Tokyo Electron Limited | Deposition process |
KR20210111396A (ko) | 2020-03-02 | 2021-09-13 | 삼성전자주식회사 | 반도체 소자 및 그의 제조 방법 |
US20220415792A1 (en) * | 2021-06-24 | 2022-12-29 | Intel Corporation | Inverse taper via to self-aligned gate contact |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000114244A (ja) * | 1998-10-05 | 2000-04-21 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US6277727B1 (en) * | 1999-10-20 | 2001-08-21 | United Microelectronics Corp. | Method of forming a landing pad on a semiconductor wafer |
JP2004228570A (ja) * | 2003-01-17 | 2004-08-12 | Samsung Electronics Co Ltd | 半導体装置及びその製造方法 |
US20040166667A1 (en) * | 2003-02-22 | 2004-08-26 | Ju-Bum Lee | Method for manufacturing a semiconductor device |
US7037774B1 (en) * | 2004-10-21 | 2006-05-02 | Integrated Device Technology, Inc. | Self-aligned contact structure and process for forming self-aligned contact structure |
US20070134909A1 (en) * | 2005-12-13 | 2007-06-14 | Veit Klee | Method of making a contact in a semiconductor device |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5912507A (en) | 1998-02-04 | 1999-06-15 | Motorola, Inc. | Solderable pad with integral series termination resistor |
JP3114931B2 (ja) | 1998-03-30 | 2000-12-04 | 日本電気株式会社 | 導電体プラグを備えた半導体装置およびその製造方法 |
KR100352909B1 (ko) * | 2000-03-17 | 2002-09-16 | 삼성전자 주식회사 | 반도체소자의 자기정렬 콘택 구조체 형성방법 및 그에의해 형성된 자기정렬 콘택 구조체 |
TW531873B (en) | 2001-06-12 | 2003-05-11 | Advanced Interconnect Tech Ltd | Barrier cap for under bump metal |
JP3819806B2 (ja) | 2002-05-17 | 2006-09-13 | 富士通株式会社 | バンプ電極付き電子部品およびその製造方法 |
TW558821B (en) | 2002-05-29 | 2003-10-21 | Via Tech Inc | Under bump buffer metallurgy structure |
US20040002210A1 (en) * | 2002-06-28 | 2004-01-01 | Goldberg Cindy K. | Interconnect structure and method for forming |
CN1469434A (zh) * | 2002-07-17 | 2004-01-21 | 茂德科技股份有限公司 | 接触孔的形成方法 |
US7250330B2 (en) | 2002-10-29 | 2007-07-31 | International Business Machines Corporation | Method of making an electronic package |
US7410833B2 (en) | 2004-03-31 | 2008-08-12 | International Business Machines Corporation | Interconnections for flip-chip using lead-free solders and having reaction barrier layers |
KR100549014B1 (ko) * | 2004-07-21 | 2006-02-02 | 삼성전자주식회사 | 스페이서 패턴을 갖는 반도체 장치들 및 그 형성방법들 |
US7126199B2 (en) * | 2004-09-27 | 2006-10-24 | Intel Corporation | Multilayer metal gate electrode |
CN100428414C (zh) | 2005-04-15 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | 形成低应力多层金属化结构和无铅焊料端电极的方法 |
US7663237B2 (en) * | 2005-12-27 | 2010-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Butted contact structure |
US7939939B1 (en) | 2007-06-11 | 2011-05-10 | Texas Instruments Incorporated | Stable gold bump solder connections |
US20090032941A1 (en) | 2007-08-01 | 2009-02-05 | Mclellan Neil | Under Bump Routing Layer Method and Apparatus |
US7915111B2 (en) * | 2007-08-08 | 2011-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with high-K/dual metal gate |
US20090140419A1 (en) | 2007-11-29 | 2009-06-04 | Kenneth Rhyner | Extended plating trace in flip chip solder mask window |
CN102187749A (zh) | 2008-10-21 | 2011-09-14 | 埃托特克德国有限公司 | 用于在衬底上形成焊料沉积物的方法 |
US8099686B2 (en) * | 2009-03-27 | 2012-01-17 | Globalfoundries Inc. | CAD flow for 15nm/22nm multiple fine grained wimpy gate lengths in SIT gate flow |
DE102009043329B4 (de) * | 2009-09-30 | 2012-02-02 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verspannungstechnologie in einer Kontaktebene von Halbleiterbauelementen mittels verspannter leitender Schichten und einem Isolierabstandshalter bei einem Halbleiterbauelement |
DE102010029533B3 (de) * | 2010-05-31 | 2012-02-09 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Selektive Größenreduzierung von Kontaktelementen in einem Halbleiterbauelement |
US8564066B2 (en) * | 2010-06-18 | 2013-10-22 | International Business Machines Corporation | Interface-free metal gate stack |
US20120025315A1 (en) * | 2010-07-30 | 2012-02-02 | Globalfoundries Inc. | Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region |
US20120175772A1 (en) | 2011-01-07 | 2012-07-12 | Leung Andrew K | Alternative surface finishes for flip-chip ball grid arrays |
US8564030B2 (en) * | 2011-06-10 | 2013-10-22 | Advanced Micro Devices | Self-aligned trench contact and local interconnect with replacement gate process |
US8716124B2 (en) * | 2011-11-14 | 2014-05-06 | Advanced Micro Devices | Trench silicide and gate open with local interconnect with replacement gate process |
-
2011
- 2011-11-14 US US13/295,574 patent/US8716124B2/en active Active
-
2012
- 2012-11-01 CN CN201280055885.4A patent/CN103946971B/zh active Active
- 2012-11-01 JP JP2014542328A patent/JP6087943B2/ja active Active
- 2012-11-01 WO PCT/US2012/062959 patent/WO2013081767A1/en active Application Filing
- 2012-11-01 EP EP12798472.2A patent/EP2780937B1/en active Active
- 2012-11-01 KR KR1020147015941A patent/KR101911035B1/ko active IP Right Grant
-
2014
- 2014-03-18 US US14/217,905 patent/US9006834B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000114244A (ja) * | 1998-10-05 | 2000-04-21 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
US6277727B1 (en) * | 1999-10-20 | 2001-08-21 | United Microelectronics Corp. | Method of forming a landing pad on a semiconductor wafer |
JP2004228570A (ja) * | 2003-01-17 | 2004-08-12 | Samsung Electronics Co Ltd | 半導体装置及びその製造方法 |
US20040166667A1 (en) * | 2003-02-22 | 2004-08-26 | Ju-Bum Lee | Method for manufacturing a semiconductor device |
US7037774B1 (en) * | 2004-10-21 | 2006-05-02 | Integrated Device Technology, Inc. | Self-aligned contact structure and process for forming self-aligned contact structure |
US20070134909A1 (en) * | 2005-12-13 | 2007-06-14 | Veit Klee | Method of making a contact in a semiconductor device |
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