JP2015116053A - 半導体装置、並びにそれを用いたオルタネータ及び電力変換装置 - Google Patents
半導体装置、並びにそれを用いたオルタネータ及び電力変換装置 Download PDFInfo
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- JP2015116053A JP2015116053A JP2013256619A JP2013256619A JP2015116053A JP 2015116053 A JP2015116053 A JP 2015116053A JP 2013256619 A JP2013256619 A JP 2013256619A JP 2013256619 A JP2013256619 A JP 2013256619A JP 2015116053 A JP2015116053 A JP 2015116053A
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Abstract
Description
これに対し、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)の同期整流を用いた整流素子があり、MOSFETは内蔵ポテンシャルがなく0Vから順方向電流が立ち上がるため損失が低い。つまり、MOSFETは同じ電流を流すのに、電圧がかからないため、損失が下がる。なお、図24は、本発明のMOSFETを用いた整流素子と従来のダイオードを用いた整流素子の順方向の電流・電圧特性を示す図である。
特に、ダイオードを用いた整流素子で最近の主流となっている圧入による固定を行う場合、方形のパッケージで、回転軸周り方向の位置合わせを厳密に行う必要があり固定が難しい。更に、方形のMOSFETのパッケージを用いると、方形のMOSFETのパッケージを圧入・固定することができる特別なオルタネータを用意する必要が生じ、開発・製造コストが増大すると共に汎用性を阻害するという問題がある。
具体的には、例えば、上記の半導体装置において、前記制御回路に電源を供給するコンデンサを更に備え、前記MOSFETチップと、前記制御回路と、前記コンデンサとは、前記第1の外部電極上に搭載され、前記第1の外部電極と、前記MOSFETチップの前記ドレイン電極と、前記MOSFETチップの前記ソース電極と、前記第2の外部電極とは、下方から上方へ向かってこの順序で積み重なるように配置され、前記MOSFETチップの前記ドレイン電極と前記第1の外部電極とが電気的に接続され、前記MOSFETチップの前記ソース電極と前記第2の外部電極とが電気的に接続されることを特徴とする半導体装置とする。
図1〜図4を参照して、本発明の第1実施形態に係る同期整流MOSFETの整流素子S1の構成について説明する。
図1は、第1実施形態に係る同期整流MOSFETを用いる整流素子のパッケージの一部を省略して示す上面図である。なお、図1では理解を容易にするため、整流素子S1のパッケージ上部に配置されるリード電極107(図2参照)と樹脂108は省略して示す。
図2は、図1のA−A断面図であり、図3は、図1のB−B断面図である。
まず、第1実施形態に係る同期整流MOSFETを用いる整流素子S1の構成要素を説明する。
図1に示すように、整流素子S1は、上面視で円形の外周部101sを有するベース電極101、ベース電極101の上部に設けられる台座102、台座102の上に実装されるMOSFETチップ103と制御回路チップ104とコンデンサ105、および、MOSFETチップ103の上に載せられるリード電極107(図2参照)を有している。
図1に示すように、MOSFETチップ103は、上面視で方形の形状を有しており、四角形のコンデンサ105と制御回路チップ104とは、MOSFETチップ103の長辺に沿って隣接して、配置されている。これにより、MOSFETチップ103、コンデンサ105、および制御回路チップ104は、互いに近接して配置できるとともに互いの間のスペースは狭小で済むため、MOSFETチップ103、コンデンサ105、および制御回路チップ104の実装効率が大に配置できる。
これにより、制御回路チップ104とMOSFETチップ103とコンデンサ105との電気的接続を担うワイヤ115の長さが最も短くでき、電気的接続の信頼性が高い。また、ワイヤ115が少量で済み、組み立て性が良く、コストが抑えられる。
次に、MOSFETチップ103の接続を説明する。
図2に示すように、MOSFETチップ103の下面に設けられたドレイン電極103dは半田109を用いてベース電極101の台座102に固定されている。これにより、MOSFETチップ103は、電気的、熱的にベース電極101に接続される。
“熱的に”とは、MOSFETチップ103のソース電極103sの延在面が、半田109を介在して、リード電極107の下面(延在面)に連結して固定されるので、MOSFETチップ103とソース電極103sとの伝熱面積が広く、MOSFETチップ103の熱が良好にソース電極103sに伝導され放出されることを意味する。
次に、コンデンサ105の接続を説明する。
図3に示すように、コンデンサ105は、絶縁基板106を介してベース電極101の台座102に半田109を用いて固定される。電気的には、コンデンサ105の高電圧側端子110は半田109により絶縁基板106の上面に設けられた第1の電極112に接続され、絶縁基板106の第1の電極112は制御回路チップ104の上面に設けられた第2の電極104bにワイヤ115を用いてワイヤボンディングで接続される。
次に、制御回路チップ104の接続を説明する。
前記したように、制御回路チップ104の上面に設けられた第1の電極104aはMOSFETチップ103の上面に設けられたゲート電極103gに、ワイヤ115を用いてワイヤボンディングで電気的に接続される。また、制御回路チップ104のチップの上面に設けられた第2の電極104bはコンデンサ105の高電圧側端子110と接続された絶縁基板106の上面の第1の電極112にワイヤ115を用いてワイヤボンディングで電気的に接続される。
また、制御回路チップ104のチップの上面に設けられる第4の電極104dは、ベース電極101の台座102に、ワイヤ115を用いてワイヤボンディングで電気的に接続される。
上述した構成により、正座の整流素子S1を実現できる。
続いて、整流素子S1の回路構成を説明する。
図4に、第1実施形態に係る同期整流MOSFETの整流素子の回路図を示す。
図4に示す回路では、L端子がベース電極101であり、H端子がリード電極107である。そして、図1〜図3を用いて説明したMOSFETチップ103、制御回路チップ104、コンデンサ105が、前記したように、電気的に接続され配線される。
図4に示す整流素子S1の回路は次のように動作する。
H端子(リード電極107)の電圧がL端子(ベース電極101)の電圧より低くなると、コンパレータ116は高電圧(もしくは低電圧)の信号をゲートドライバ117に出力する。高電圧(もしくは低電圧)の信号が入力されたゲートドライバ117は、MOSFETチップ103のゲート電極103gの電圧を上げてMOSFETチップ103をオン状態にする。
また、図4に示すコンデンサ105に代えて、外部から電源を供給することとしてもよい。
次に、図1〜図4を用いて説明した第1実施形態に係る同期整流MOSFETの整流素子S1の特徴とその効果を説明する。
図5に、オルタネータの放熱板に固定した圧入型の第1実施形態の同期整流MOSFETの整流素子の側面図を示す。
圧入で固定する場合、図5に示すように、ベース電極101の外周部101sに、上面視で凹凸状の(径方向に凹凸が設けられる)ローレット101rが形成される。
さらに、リード電極107の端子を上面視で整流素子S1のパッケージの中心軸O上に配置することで、MOSFETチップ10の上面視で回転軸(中心軸O)周りの位置合わせが不要である。つまり、整流素子S1のパッケージの芯だしを行うことで、整流素子S1の位置決めを行うことができる。
図7は、第1実施形態に係るMOSFETを用いた整流素子の別の実施形態(変形形態1)の上面図である。なお、図7では、MOSFETチップ103の上に載せられるリード電極107、樹脂108等を省略して示している。
なお、金属板120を用いることなく、図9に示すように、半田109でコンデンサ105の低電圧側端子111を支持する構成としてもよいし、或いは、図10に示すように、金属板120に代えてベース電極101の台座102に凸部102tを設け、該凸部102tでコンデンサ105の低電圧側端子111を、半田109を介して支持する構成としてもよい。
図9、図10の構成により、部品点数が削減され、低コスト化が可能である。
JCRをコンデンサ105、絶縁基板106、リード電極107に塗布することで、これら(105、106、107)と樹脂108との密着性も上げることができる。
なお、溝101mまたは/およびJCRは、実施形態の整流素子S1、後記の整流素子S12、S2に適用してもよい。
次に、変形形態2の整流素子S12について説明する。
図11と図12に、別の実施形態(変形形態2)のツェナーダイオードのチップを搭載した整流素子の上面図と図11のD−D断面図を示す。
整流素子S12にサージ吸収の機能を持たせるために、整流素子S12にツェナーダイオードを搭載してもよい。
次に、本発明の第1実施形態に係る同期整流MOSFETの整流素子S1を組み立てる方法を説明する。
組み立てには、まず、整流素子S1を構成する部品を定められた位置に固定するためのカーボン冶具を用いる。カーボン冶具の台座102の固定位置にベース電極101を入れ、その上にカーボン冶具の蓋をする。
なお、MOSFETチップ103とリード電極107、絶縁基板106とコンデンサ105との間の半田付けの工程を、1回目の半田付けの工程では行わず、ワイヤボンディング工程を行った後に行ってもよい。
ゲート電極103gの配線を形成する工程において、回転軸(図13、図14の外周部101sの中心軸O)周り方向の位置合わせをする方法として、ベース電極101の外周部101sの円形形状の一部に、図13の上面図に示すようなノッチ122もしくは図14の上面図に示すようなオリエンテーションフラット(Orientation Flat)123(以下、オリフラ123と称す)を設ける。
さらに、回転軸(図15の外周部101sの中心軸O)周り方向の位置合わせをする別の方法として、ベース電極101の底部に図15に示すような凹部124を設ける。
例えば、回転軸周り方向の位置合わせをする機構は、コンデンサ105等の部品の配置を確認するCCD等の視認装置、回転位置を制御するモータと、その減速機構と、減速機構で回動され位置合わせを行う回転部材と、回転位置センサと、これらを制御してワイヤボンディングの位置合わせの制御を行う制御装置とを有している。
回転軸(図16の外周部101sの中心軸O)周り方向の位置合わせをする更に別の方法として、図16に示すように、ワイヤボンディングで形成するワイヤの代わりに、接続が可能な形状に形成される銅板もしくは銅線125を半田ボールもしくは半田バンプ126で固定して接続する。
なお、接続を行う導体として、銅板もしくは銅線125を例示したが、銅以外の導体を用いてもよい。
図16では、銅板もしくは銅線125を半田で接続する例を示したが、図17に示すように、バネ機構を有する銅ピンのバネ付ピン146A、146B、148A、148Bを用い、バネ付ピン146A、146B、148A、148Bのバネの弾性力で電気的に接続してもよい。
バネ付きピン146Aは、下部に端子146a1、中央にバネ146b1、上部に固定部146c1を有している。また、バネ付きピン146Bは、下部に端子146a2、中央にバネ146b2、上部に固定部146c2を有している。
バネ付きピン148Aとバネ付きピン148Bとが、銅バー147bで固定されている。
上述した如く、配線にワイヤ115に代えて、上述のバネ付きピン146A、146B、148A、148B等を用いることで、配線の接続不良に対する信頼性を向上させることができる。
図18〜図20を参照して、本発明の第2実施形態に係る同期整流MOSFETの整流素子S2の構成について説明する。
図18は、第2実施形態に係る同期整流MOSFETの整流素子のパッケージの一部を省略して示す下面図である。(以降の第2実施形態の説明では、第1実施形態とは逆に、リード電極107を下に、ベース電極101を上にして上面、下面と呼ぶ。)なお、図18では、分かり易いように、ベース電極101、MOSFETチップ103とベース電極101とを接続する後記の電極ブロック127(図19参照)、樹脂108は省略して示している。
図21は、第1・第2実施形態に係る自律型の同期整流MOSFETの整流素子S1、S2を用いたオルタネータOtの整流回路の回路図である。
これにより、逆座の整流素子S2を実現できる。
図18〜図20に示すように、第2実施形態に係る同期整流MOSFETの整流素子S2は、四角形の外周部107sを有するリード電極107(図18参照)、リード電極107に設けられる電子部品を載せる台座107d、台座107d上に載せられたMOSFETチップ103と制御回路チップ104とコンデンサ105、コンデンサ105の下に敷かれた電極112、113を有する絶縁基板106、MOSFETチップ103の上に載せられた電極ブロック127(図19参照)とベース電極101、ベース電極101に設けられる台座102と電子部品(103、104、105)を覆う樹脂108とを有する。
そして、図18に示すように、MOSFETチップ103の上面のゲート電極103gは、ワイヤ115で制御回路チップ104の上面の第1の電極104aに電気的に接続される。
なお、第2実施形態の整流素子S2に、第1実施形態で説明した整流素子S1、S11、S12の様々な構成を適宜選択して組み合わせて構成してもよい。
図21を参照して、本発明の自律型の同期整流MOSFETの整流素子S1、S2を用いたオルタネータOt(図22参照)の整流回路の構成について説明する。図22に、同期整流MOSFETの整流素子を用いたオルタネータの要部断面図を示す。
図21に示す本発明の同期整流MOSFETの整流素子S1、S2を用いたオルタネータOtの整流回路の動作を説明する。
前記したように、第1実施形態に係る同期整流MOSFETの整流素子S1、S2が円形の外周部101sを持つベース電極101を有することにより、複数の整流素子S1、S2をそれぞれ放熱板119a、119bに簡易に圧入して固定できる。
一方、ロウサイドのU相、V相、W相の整流素子は、MOSFETチップ103のソース端子103sが共通の端子に電気的に接続されるので、ロウサイドにはソース端子103sが放熱性の高いベース電極101に電気的に接続された逆座の整流素子S2を用いる。こうすることで、ロウサイドのU相、V相、W相の整流素子を1つの放熱板119bに固定でき、より大きな放熱板を使うことでより大きな放熱効果を得ることができる。
更に、ハイサイドのU相、V相、W相の整流素子はMOSFETチップ103のソース端子103sと、ロウサイドのU相、V相、W相の整流素子のMOSFETチップ103のドレイン端子103dとは、各相の固定子129の端子と電気的に接続される。ハイサイドに正座の整流素子S1を用い、ロウサイドに逆座の整流素子S2を用いることで、正座の整流素子S1の細いリード電極107と逆座の整流素子S2の細いリード電極107とが対向して配置され、整流素子のリード電極107と固定子129との電気的な接続が容易になる。加えて、正極側放熱板119aと負極側放熱板119bとの間の間隔をより小さくでき、オルタネータをより小型にすることができる。
整流素子S1、S2が円形の外周部101sを持つベース電極101とベース電極101の上部にリード電極107を有することで、より汎用性の高い放熱板119a、119bを用いることができる。
容易に整流素子S1、S2をオルタネータOtに固定できることにより、オルタネータOtの組み立て工程の簡素化が可能であり、低コスト化を図れる。
1.第1・第2実施形態のベース電極101は、上面視で円形の円筒状の外周部101sを例示したが、上面視で円形の曲率をもつ、例えば球状の外周部101sをもつ構成としてもよい。
2.なお、図15に示す凹部124に代えて、ベース電極101の外周部101sまたは底面部に位置決め用凸部を形成し、ベース電極101の外側のセット側に位置決め用凸部が嵌入される凹部を形成し、ベース電極101の位置決め用凸部をセット側の凹部に嵌入し、整流素子S1(S11、S12)、S2の位置決めを行うように構成してもよい。
4.なお、本発明は前記した実施例(形態)に限定されるものでなく、様々な実施例が含まれる。例えば、上記した実施例は本発明を分り易く説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。例えば、説明した構成の一部を含むものであってもよい。
また、ある実施例の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることも可能である。例えば、説明した整流素子S1、S11、S12、S2の種々の構成を適宜選択して組み合わせて構成してもよい。
101s 外周部
102 台座(第1の外部電極の一部)
103 MOSFETチップ
103d ドレイン電極(第1の主端子)
103g ゲート電極(ゲート)
103s ソース電極(第2の主端子)
104 制御回路チップ(制御回路)
104a 第1の電極(電極)
104b 第2の電極(電極)
104c 第3の電極(電極)
104d 第4の電極(電極)
105 コンデンサ
106 絶縁基板
107 リード電極(第2の外部電極、第1の外部電極)
107d 台座
108 樹脂(第1の樹脂)
109 半田
112、113 電極
115 ワイヤ
121 ツェナーダイオード
122 ノッチ(凹部)
123 オリフラ(凹部)
124 凹部
125 銅線もしくは銅板(導体)
146A、146B、148A、148B バネ付ピン(導体機構)
146b1、146b2、148b1、148b2 バネ
O 中心軸(外周部の中心線)
Os 整流装置
Ot オルタネータ(電力変換装置)
S1 正座の整流素子(半導体装置)
S2 逆座の整流素子(半導体装置)
Claims (20)
- オルタネータに取り付けられる上面視で円形の外周部を有する第1の外部電極と、
MOSFETチップと、
前記MOSFETチップに対して前記第1の外部電極の反対側に配置される第2の外部電極と、
前記MOSFETチップのドレイン電極とソース電極の電圧もしくは電流が入力され、当該電圧もしくは電流に基づいて前記MOSFETチップのゲートに供給する制御信号を生成する制御回路と
を備え、
前記第1の外部電極と、前記MOSFETチップの前記ドレイン電極と、前記MOSFETチップの前記ソース電極と、前記第2の外部電極とは、互いに積み重なるように配置され、
前記MOSFETチップの前記ドレイン電極および前記ソース電極の一方と前記第1の外部電極とが電気的に接続され、
前記MOSFETチップの前記ドレイン電極および前記ソース電極の他方と前記第2の外部電極とが電気的に接続される
ことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記制御回路に電源を供給するコンデンサを更に備え、
前記MOSFETチップと、前記制御回路と、前記コンデンサとは、前記第1の外部電極上に搭載され、
前記第1の外部電極と、前記MOSFETチップの前記ドレイン電極と、前記MOSFETチップの前記ソース電極と、前記第2の外部電極とは、下方から上方へ向かってこの順序で積み重なるように配置され、
前記MOSFETチップの前記ドレイン電極と前記第1の外部電極とが電気的に接続され、
前記MOSFETチップの前記ソース電極と前記第2の外部電極とが電気的に接続される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1の外部電極の前記円形の外周部もしくは底面部に、前記円形の外周部の中心線周りの位置決め用の凹部または凸部を有する
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記円形の外周部の中心線上に前記MOSFETチップと前記第2の外部電極が配置される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記MOSFETチップの前記ドレイン電極の延在面と前記第1の外部電極の延在面とが、半田を介してまたは圧接されて連結され、かつ、前記MOSFETチップの前記ソース電極の延在面と前記第2の外部電極の延在面とが、半田を介してまたは圧接されて連結される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記MOSFETチップと前記制御回路、および、前記制御回路と前記コンデンサが、ワイヤにより電気的に接続される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記MOSFETチップと前記制御回路、および、前記制御回路と前記コンデンサは、それぞれ接続が可能に形成された形状の導体またはバネを有する導体機構で電気的に接続され、
前記導体は半田を介して電極に固定され、前記導体機構は前記バネの弾性力による押圧により電極に固定される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記MOSFETチップの形状は長方形であり、前記長方形の長辺に隣接する位置に前記コンデンサと前記制御回路とが配置される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記コンデンサは、絶縁基板を介して、搭載される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記半導体装置は、ツェナーダイオードを更に備え、
前記ツェナーダイオードの第1の主端子と前記第1の外部電極が電気的に接続されるとともに互いの延在面が連結され、
前記ツェナーダイオードの第2の主端子と前記第2の外部電極が電気的に接続されるとともに互いの延在面が連結される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記MOSFETチップ内にツェナーダイオードが内蔵される
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1の外部電極は、前記円形の外周部に収まる大きさの台座を有し、
前記第1の外部電極の前記台座上に前記MOSFETチップ、前記制御回路、および前記コンデンサが搭載され、
前記第1の外部電極の前記台座、前記MOSFETチップ、前記制御回路、および前記コンデンサが第1の樹脂で覆われている
ことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1の外部電極は、前記円形の外周部に収まる大きさの台座を有し、
前記第1の外部電極の前記台座上に前記MOSFETチップ、前記制御回路、および前記コンデンサが搭載され、
前記第1の外部電極の前記台座、前記MOSFETチップ、前記制御回路、および前記コンデンサが第1の樹脂で覆われ、
前記第1の樹脂内で前記MOSFETチップと前記制御回路の半導体チップの側壁が第2の樹脂で覆われ、
前記第2の樹脂は前記第1の樹脂よりも前記両チップとの密着性が高い
ことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記制御回路に電源を供給するコンデンサを更に備え、
前記第2の外部電極は、前記第1の外部電極の円形の外周部に収まる大きさの台座を有し、
前記MOSFETチップと、前記制御回路と、前記コンデンサとは、前記第2の外部電極の前記台座上に搭載され、
前記第2の外部電極と、前記MOSFETチップの前記ドレイン電極と、前記MOSFETチップの前記ソース電極と、前記第1の外部電極とが、下方から上方へ向かってこの順序で積み重なるように配置され、
前記MOSFETチップの前記ドレイン電極と前記第2の外部電極とが電気的に接続され、
前記MOSFETチップの前記ソース電極と前記第1の外部電極とが電気的に接続される
ことを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記第1の外部電極の前記円形の外周部もしくは底面部に、前記円形の外周部の中心線周りの位置決め用の凹部または凸部を有する
ことを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記MOSFETチップの前記ドレイン電極の延在面と前記第2の外部電極の延在面とが、半田を介してまたは圧接されて連結され、かつ、前記MOSFETチップの前記ソース電極の延在面と前記第1の外部電極の延在面とが、半田を介してまたは圧接されて連結される
ことを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記第1の外部電極は、前記円形の外周部に収まる大きさの台座を有し、
前記第1の外部電極の前記台座、前記第2の外部電極の前記台座、前記MOSFETチップ、前記制御回路、および前記コンデンサが第1の樹脂で覆われている
ことを特徴とする半導体装置。 - 請求項1乃至17のいずれか1項に記載の半導体装置を備えるオルタネータ。
- 請求項2乃至13のいずれか1項に記載の半導体装置を整流装置としてハイサイドに、請求項14乃至17のいずれか1項に記載の半導体装置を整流装置としてロウサイドに、それぞれ用いた整流回路を備えるオルタネータ。
- 請求項1乃至17のいずれか1項に記載の半導体装置を備える電力変換装置。
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WO2021079735A1 (ja) | 2019-10-24 | 2021-04-29 | 株式会社日立パワーデバイス | 半導体装置及びそれを用いた整流素子、オルタネータ |
WO2022176271A1 (ja) * | 2021-02-17 | 2022-08-25 | 株式会社日立パワーデバイス | 整流回路、整流回路の制御方法 |
Also Published As
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US10319849B2 (en) | 2019-06-11 |
JP6263014B2 (ja) | 2018-01-17 |
EP3082243A4 (en) | 2017-12-06 |
WO2015087997A1 (ja) | 2015-06-18 |
CN105814785B (zh) | 2019-10-11 |
EP3082243A1 (en) | 2016-10-19 |
TWI530080B (zh) | 2016-04-11 |
CN105814785A (zh) | 2016-07-27 |
TW201531009A (zh) | 2015-08-01 |
US20160315184A1 (en) | 2016-10-27 |
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